IHP - Innovations for High Performance Microelectronics: Heteroepitaxy-4

Concerning the integration of functional semiconductor layers on the technology platform, two main philosophies must be distinguished, depending upon the targeted application:

Integrated device manufacturers (IDM`s) generally focus R&D activities on local integration approaches where the functional semiconductor is deposited on the Si wafer only in the processed window of the future hybrid device.

Substrate supplier companies focus R&D activities on global integration approaches where the functional semiconductor layer is deposited over the whole wafer.

According to NanoMarket`s new report, “The New Thin Film Electronics, Large Area Electronics and Beyond” emerging thin film electronics applications will generate $ 15.5 bn in revenues in 2011 (www.nanomarkets.net). The resulting layer quality is however of utmost importance to realize the desired increase in functionality and / or performance of the thin film and integrated circuit electronics. Depending upon the global or local integration strategy, the following main functional film preparation techniques can be distinguished:

The most important innovation in the field of global integration approaches for preparing engineered Si wafer systems is the so called layer transfer technique [6]. The sketch in Fig. 2 explains the main steps in the process:

Step 1: wafer 1 is oxidized, wafer 2 receives an hydrogen implant (Smart Cut).

Step 2: wafer bonding is used to transfer the Si layer from wafer 2 to wafer 1.

The most important advantage of the layer transfer is its “anything on anything” vision. This term expresses the high flexibility of the approach to bond various materials to each other. However, limitations certainly exist, in especial by the fact that bulk crystal wafers of required quality and diameter do not exist for many interesting compound semiconductor materials (GaAs, GaN etc.).

Strategies exist which intend to adopt the layer transfer to the task of local integration approaches. These are divided into “die to wafer bonding” and “microstructure printing” techniques. First, III-V die to Silicon on insulator (SOI) wafer bonding was demonstrated with the aim to set up III-V / Si photonic hybrid devices [8]. Fig. 3 illustrates the III-V die bonding of unprocessed InP / InGaAsP on SOI wafer, the subsequent removal of the InP substrate and the processing of the III-V devices.

Fig. 3: “Die to wafer bonding” technique for local integration of III-V materials on the Si material platform to fabricate Si photonics hybrid devices [8].

Second, printing techniques are very similar to the die wafer bonding approach but here the functional semiconductor material is already micro-structured [9]. The microstructure is prepared by lithographic means on the bulk wafer of the alternative semiconductor material, lifted-off after applying underetching techniques and subsequently bonded to the bonding pads of the target wafer. An example from Semprius is shown in Fig. 4. Fig. 4(a) shows an under-etched GaN microstructure on a Nitronex GaN-on-silicon (111) wafer which is afterwards bonded to a Si(001) substrate (Fig. 4(b)). In addition, Fig. 4(c) and 4(d) show GaAs ribbons transferred on a glass substrate. In this respect, the die bonding and printing techniques offers similar to the layer transfer in principle a high degree of flexibility and even circumvent the problem of the non-availability of large diameter compound semiconductor wafers. However, due to the recent emergence of these interesting innovations, little is known today about the cost-effectiveness of these rather process intensive integration approaches.

The classical film deposition approach to prepare single crystalline, functional semiconductor layers on Si substrates is heteroepitaxy. The ordered growth of the functional semiconductor layer on Si is carried out either by physical vapour deposition (PVD) (e.g. molecular beam epitaxy (MBE),

pulse laser deposition (PLD) etc.) or chemical vapour deposition (CVD) (e.g. atomic layer deposition (ALD), atomic vapour deposition (AVD) etc.) techniques. Due to the large lattice mismatch of almost all alternative semiconductor materials with respect to Si, the direct heteroepitaxy of these materials on Si results in poor layer quality. Therefore, as depicted in Fig. 5, the heteroepitaxy approach focuses in general on the integration of new semiconductor materials on the Si platform via lattice adjusting buffer layers. The heterostructure is in consequence prepared by two subsequent simple epi-steps:

Step 1: growing lattice adjusted or lattice mismatched buffer structures on Si wafers. A wide class of buffer materials is exploited (dielectrics (oxides, fluorides, nitrides etc.), semiconductors (graded SiGe layers etc), metals (conducting oxides etc.)).

Step 2: depositing functional semiconductors on the buffer film structures. The functional semiconductor layers are either IV-IV (SiGe, SiC etc), III-V (GaAs, GaN etc.) or II-VI (ZnO, ZnSe etc.) materials.

The advantage of the heteroepitaxy approach is clearly its conceptual simplicity. In consequence, it is highly cost-effectiveness in comparison to the competing techniques sketched above. However, the main obstacles in heteroepitaxy to achieve the required layer quality is the fact that the lattice matched or mismatched functional semiconductor layers are grown on foreign materials. Crystal lattice symmetry breaks, geometrical as well as thermal lattice mismatch problems etc. require advanced defect engineering techniques to improve the layers and achieve technologically relevant qualities.



	Fig. 2: Layer transfer technique by Smart Cut with hydrogen implant [7]



	Fig. 4: Examples of “microstructure printing” techniques from Semprius [8]



	Fig. 5: Functional semiconductor integration on the Si material platform by heteroepitaxy via lattice matched or mismatched buffers.