Overview >> MPL - Modular Processor Library
| Goals | The project is used internally to develop a library of verified and re-usable modules based on the IHP BiCMOS (SiGe:C) technology. The focus is low-power processor and multi-processor solutions for high performance wireless communication systems. Additional design support to customers is given in developing reliable systems in short time. |
| Motivation | The MPL project will enable powerful and competitive system-on-chip solutions which can be implemented very flexible and very fast according to actual market requirements. |
| Results | Within the project a design flow is developed to design and implement modules and systems in a hierarchical library under suitable version control management tool. |
| Project Partners |
IHP (chip production and measurement) MIPS Technologies International AG (MIPS processor core) Gaisler Research, Inc. (Leon processor cores and components) Genesys Ltd. (memory generators) Humboldt University of Berlin (e.g. PCB designs) Tool partners (selection): Cadence Design Systems, Inc. (simulation, layout design) Synopsys, Inc. (net list synthesis) Perforce Software, Inc. (version control management) |
| Customers | IHP (several internal customer projects) |