IEEE 802.11a GALS baseband processor
IEEE 802.11a GALS baseband processor
Baseband processor for WLAN standard includes receiver and transmitter datapath structure. In this processor very complex blocks are implemented such as Viterbi decoder, FFT, IFFT, CORDIC processors...
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Partitioning and implementation of the GALS baseband processor
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• Partitioning is separately performed in the receiver and the transmitter. This process has
taken into account possible power saving.
• We have used test strategy based on built-in self-test (BIST) in baseband processor.
• GALS Baseband processor has been fabricated as an ASIC in our in-house 5-metal layer
0.25 µm process.
Power and EMI measurement
• GALS baseband processor was successfully tested and extensively measured.
• The dynamic power dissipated in the pure synchronous baseband processor
was 332 mW, and for the GALS baseband processor slightly lower, at 328 mW.
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• With GALSification we have achieved a 30% reduction in peak power supply current, and
5 dB reduction in spectral noise.