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The Objective
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Shrinking conventional CMOS technology in the sub-50 nm regime requires to reduce the thickness of the conventional SiO2 gate oxide to below 1.5 nm. Direct tunnelling becomes the dominant conduction mechanism across the dielectric layer in this thickness range, which results in unacceptably high leakage currents. A materials science approach to enable further transistor scaling in this regime is to to replace the traditional SiO2 gate oxide with alternative high-k gate dielectrics. more
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