High-k dielectrics for sub 0.1 µm MOSFET technologies

	Fig. 1: Historical point contact transistor [1] in comparison with a 10 nm research MOSFET [3] (from [5]).

1. Development of alternative high-k dielectrics for future MOSFET technologies

Figure 1 at the top shows the dimensions of the historical point contact ransistor built at Bell laboratories by John Bardeen and Walter Brattain in Shockley`s group [1]. The point contact transistor consists of a piece of n-type Ge several mm in size on a metal plate which served as the gate contact and two springs loaded top contacts, called emitter and collector. Biasing the back contact produced an inversion layer in n-Ge on the top side and a hole current was observed between the emitter and the drain. Later on, Si became the semiconductor of choice for integrated circuits due to the higher interface quality of the SiO₂ / Si boundary. Since 1955, when the first metal-oxide-semiconductor field-effect transistor (MOSFET) on Si was developed, its dimensions have been continuously reduced to enable higher speed and packing density of the silicon integrated circuits [2]. The bottom part of Fig. 1 shows a state-of-the art 10 nm research MOSFET prototype from Intel [3].

Particularly challenging in shrinking MOSFET device dimensions in the nanoscale regime is the fact that the SiO₂ gate oxide thickness needs to be decreased to below 1 nm. In this thickness regime, direct tunneling becomes the dominant leakage mechanism, resulting in a rapid rise of the transistors stand-by power to a level which cannot be accepted. This is especially true for portable electronic devices [3]. Therefore, to reduce the power dissipation and enable further miniaturization, an alternative insulator of higher dielectric constant (high-k dielectric) must be integrated in the conventional planar MOSFET technology [4, 6].

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