The alternative high-k dielectric and its interface with silicon must satisfy a wide range of stringent demands. These can be best understood by regarding a modern planar MOSFET device at work, as shown in Fig. 2. The transistor switches from the off- to the on-state by applying a positive voltage to the gate electrode. The p-Si substrate underneath the insulating gate dielectric becomes inverted. Inversion means that the minority carriers of the wafer material, in our case electrons, become the dominant charge carriers in the Si surface region. In that way, a conducting n-channel is formed in the surface region of the p-Si wafer and a current flows from the source to the drain. The latter results because the drain electrode is held at a slightly more positive potential than the source, which is usually connected to ground.

	Fig. 2: Schematic view of a n-channel MOSFET in the on-state [5].

Advanced high-k dielectric materials in future complementary metal-oxide-semiconductor (CMOS) transistor technologies will have to fulfill the following very challenging requirements [5, 6]:

1) equivalent oxide thickness (EOT) < 1 nm

2) gate leakage current advantage over the traditional SiO₂ dielectrics

3) excellent reliability (time dependent dielectric breakthrough (TDDB) characteristics etc.)

4) good microprocessing capability and thermal stability

5) high mobility (electrically stable interface with few defects)

Research in our group is mainly focused on rare earth-based dielectrics with high ionic and electronic polarizabilities which contribute to relatively high dielectric constant values of these compounds [7]. Another family of dielectrics investigated at IHP are HfO₂-based materials.

Screening of new dielectric materials for CMOS applications at IHP involves extensive physical and electrical characterization. The availability of MOSFET test structures from our cleanroom facilities is a special opportunity to study alternative gate dielectrics for CMOS applications at IHP.

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