Research in our group is focussed on the development of dielectric layers for DRAM cells. DRAM is a 1 transistor – 1 capacitor cell technology. Scaling DRAM cells requires reducing the dielectric layer cell in the transistor as well as in the capacitor. It turned out in the past that, due to dielectric breakdown issues, thickness reduction of the dielectric layer in the capacitor is particularly challenging. The scaling rule requires to reduce the thickness of the dielectric proportionally to L2 (L: feature size of the technology node), but this is not possible anymore since the late eighties (4-Mbit generation). Instead, 3D capacitors architectures were integrated, either in form of trenches in the bulk Si wafer (Qimonda) or stacks on top of the wafer (Samsung). Figure 1 shows as a vertical cross-section of the fully integrated 512Mb deep-trench DRAM using the 58 nm technology of Qimonda (www.qimonda.com) (left), and a schematic representation of a deep-trench DRAM cell (right).
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Fig. 1: Vertical cross-section of the fully integrated 512Mb deep trench (DT) DRAM using the 58 nm technology of Qimonda (left), schematic representation of a deep-trench DRAM cell (right). | ||||
For future Gbit DRAM generations manufacturers will have to integrate advanced high-k dielectric materials, fulfilling the following, very challenging requirements [5-7]:
1) Equivalent oxide thickness (EOT) < 1 nm
2) low leakage current (10-7 – 10-8 A / cm2 at 1 V)
3) excellent time dependent dielectric breakthrough (TDDB) characteristics
4) good step coverage for 3-D cells
5) good microprocessing capability and thermal stability
6) small polarization reversal at reversing biases
To fulfill the above requirements Praseodymium- and Hafnium-based high-k dielectric layers are currently being developed at IHP.
These research activities are performed in the framework of the MEGA EPOS project (www.megaepos.de) supported by Federal Ministry of Education and Research (BMBF).