Script list Publications
(1) Simulation-based Performance Analysis of a Single Event Latchup Protection Switch for CMOS Integrated Circuits
M. Andjelkovic, V. Petrovic, Z. Stamenkovic, G. Ristic, G. Jovanovic
Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 255 (2015)
A single event latchup protection switch (SPS) has been developed in the IHP 250 nm bulk CMOS technology. The SPS has been designed as a standard library cell intended for implementation in the radiation-tolerant application specific integrated circuits (ASICs). It provides detection of single event latchup and subsequent shut-down of power supply to critical elements within the chip to restore the normal operation. However, the SPS cell might be also susceptible to single event transients. In that regard, this work presents the simulation-based analysis of the response of SPS cell in the case of single event transients. The dependence of the single event transient response with respect to the injected charge, supply voltage, load and sensing transistor size has been analyzed.
(2) Circuit-Level Simulation of Single Event Transients in an On-Chip Single Event Latchup Protection Switch
M. Andjelkovic, V. Petrovic, Z. Stamenkovic, G.S. Ristic
Journal of Electronic Testing 31, 275 (2015)
The SPS is intended for implementation in radiation tolerant integrated circuit designs, and it provides detection of single event latch-up effect and shut-down of power supply to critical elements within the chip to restore the normal operation. It is based on a PMOS transistor which acts as a latchup sensor, and includes additional PMOS and NMOS transistors for controlling the sensing transistor and interfacing to the external control logic. The initial simulation has confirmed the SPS's functionality in the case of single event latchup, and experimental investigation has proven that the SPS is immune to single event latchup for LET values of up to 74.8 MeV∙cm2/mg. This work extends the previous research by introducing the performance evaluation of the SPS cell in the case of single event transient (SET) effects. The duration of the SET-induced voltage pulse at the SPS’s output was investigated through circuit-level simulations using the square pulse current generator for modeling the SET-induced current. The critical charge necessary to cause the change of voltage level at SPS’s output was estimated to be around 245 fC, and for higher values of injected charge the duration of the SET-induced voltage pulse increased linearly until a saturation level was reached. The duration of the SET-induced voltage pulse also increased with increase of operating temperature. However, with increase of the supply voltage and sensing transistor’s channel length, the SET-induced voltage pulse duration decreased. Hence, as the voltage supply cannon be changed, by increasing the channel width of the sensing transistor it is possible to enhance the SPS’s immunity to SET effects.
(3) A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates
M. Babic, M. Krstic
Proc. 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 217 (2015)
(GASEBO)
The objective of this paper is to propose a coarse model for coupling of switching noise through lightly doped substrates. This could be achieved by assuming a regular placement of substrate contacts in a digital aggressor. Additionally, an approximation of equal ground bounce in an entire digital aggressor is applied. The proposed model is aimed for use as an estimation before placement, i.e. before knowing the exact layout details. Consequently, this model could be utilized as a guideline for determining the optimal floorplanning of digital blocks with regards to substrate noise coupling to sensitive analog modules. Extraction code is written in MATLAB. Evaluation of the model has shown that reasonable accuracy of the estimation could be expected and that the proposed method could be used as a baseline for early exploration of substrate noise characteristics of the design.
(4) Frequency-Domain Modeling of Ground Bounce and Substrate Noise for Synchronous and GALS Systems
M. Babic, X. Fan, M. Krstic
Proc. 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2015), (2015)
(GASEBO)
In this work, the ground bounce noise has been modeled and analyzed in frequency domain, for both synchronous and GALS (globally synchronous, locally synchronous) systems. The analysis has been performed analytically, and validated by numerical simulations in MATLAB. Package parasitics and power distribution network have been coarsely modeled by a simple lumped model, while switching currents have been modeled as periodic triangular pulses. Dominant components of spectrum are determined, and the impact of their distribution on the requirements for substrate modeling has been discussed. It has been concluded that resistive substrate approximation introduces large errors for systems with small decoupling capacitances, while it can be satisfactory for systems with large decoupling capacitances.
(5) Modeling of Substrate Noise Coupling and Ground Bounce for GALS Systems
M. Babic, M. Krstic
Proc. Annual DCPS (Dependable Cyber-Physical Systems) Evaluation Workshop, 70 (2015)
(GASEBO)
This paper presents an overview of some of the early results achieved within the DFG project GASEBO. The final goal of the project is to explore the possibility of actively reducing substrate noise in BiCMOS technologies by applying GALS (globally asynchronous, locally synchronous) methodology in digital design. In order to be able to evaluate such system level methodology, the appropriate high abstraction level models for noise generation and noise propagation, which can be used for coarse estimations in early phases of the design flow, had to be developed. This paper presents a coarse model for estimation of substrate noise propagation in BiCMOS technologies, and a frequency-domain model for ground bounce in both synchronous and GALS systems. Both models have been implemented in MATLAB code, and are intended to be used for comparisons between GALS and synchronous designs in terms of substrate noise, as well as for developing an optimal GALS methodology for substrate noise reduction.
(6) GALS Methodology for Substrate Noise Reduction in BiCMOS Technologies
M. Babic, M. Krstic
Proc. Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), (2015)
(GASEBO)
(7) Towards an OS-independent Code-Update Function for WSN
T. Basmer, I. Kabin, M. Schölzel
Proc. 14. GI/ITG KuVS Fachgespräch "Sensornetze", 61 (2015)
(DIAMANT)
This paper presents the concept of an operating system independent code update function for wireless sensor networks. The code update is separated from the application and the operating system in order to provide a basic input/output functionality that can be used to update the whole operating system. Moreover, we show that such an I/O-functionality can be used to handle particular faults in sensor nodes making them more reliable. In order to achieve this goal it is important that the code-update functionality has a very small memory foot-print.
For that reason we present preliminary results of a prototype
implementation demonstrating the feasibility of the concept.
(8) Recognizing Upper Limb Movements with Wrist Worn Inertial Sensors using k-means Clustering Classification
D. Biswas, A. Cranny, N. Gupta, K. Maharatna, J. Achner, J. Klemke, M. Jöbges, St. Ortmann
Human Movement Science 40, 59 (2015)
(StrokeBack)
In this paper we present a methodology for recognizing three fundamental movements of the human forearm (extension, flexion and rotation) using pattern recognition applied to the data from a single wrist-worn, inertial sensor. We propose that this technique could be used as a clinical tool to assess rehabilitation progress in neurodegenerative pathologies such as stroke or cerebral palsy by tracking the number of times a patient performs specific arm movements (e.g. prescribed exercises) with their paretic arm throughout the day. We demonstrate this with healthy subjects and stroke patients in a simple proof of concept study in which these arm movements are detected during an archetypal activity of daily-living (ADL) – ‘making-a-cup-of-tea’. Data is collected from a tri-axial accelerometer and a tri-axial gyroscope located proximal to the wrist. In a training phase, movements are initially performed in a controlled environment which are represented by a ranked set of 30 time-domain features. Using a sequential forward selection technique, for each set of feature combinations three clusters are formed using k-means clustering followed by 10 runs of 10-fold cross validation on the training data to determine the best feature combinations. For the testing phase, movements performed during the ADL are associated with each cluster label using a minimum distance classifier in a multi-dimensional feature space, comprised of the best ranked features, using Euclidean or Mahalanobis distance as the metric. Experiments were performed with four healthy subjects and four stroke survivors and our results show that the proposed methodology can detect the three movements performed during the ADL with an overall average accuracy of 88% using the accelerometer data and 83% using the gyroscope data across all healthy subjects and arm movement types. The average accuracy across all stroke survivors was 70% using accelerometer data and 66% using gyroscope data. We also use a Linear Discriminant Analysis (LDA) classifier and a Support Vector Machine (SVM) classifier in association with the same set of features to detect the three arm movements and compare the results to demonstrate the effectiveness of our proposed methodology.
(9) Bug-Tolerant Sensor Networks: Experiences from Real-World Applications
M. Brzozowski, P. Langendörfer
Proc. 7th International Conference on Ad Hoc Networks (2015), 1 (2015)
(SAID)
(10) Bug-Tolerant Sensor Networks: Experiences from Real-World Applications
M. Brzozowski, P. Langendörfer
Proc. 7th International Conference on Ad Hoc Networks (2015), 1 (2015)
(ATEM)
(11) Challenges for 100 Gbit/s End to End Communication: Increasing Throughput Through Parallel Processing
S. Buechner, J. Nolte, R. Kraemer, L. Lopacinski, R. Karnapke
Proc. of the 40th IEEE Conference on Local Computer Networks (LCN 2015) (2015)
(DFG-SPP1655)
Today's applications and services become more dependent on fast wireless communication, for the upcoming years data-rate demands of 100Gbit/s can be easily expected. However, fulfilling that demand is a task which cannot simply be solved by upscaling existing technologies. While most of the research tackles the challenges regarding the transmission technology from the physical layer up to base-band processing, we focus on the challenges concerning the handling of that vast amount of data. The overall goal is to bring together the transmission technology with the operating system to create a suitable end-to- end communication solution. In this paper we argue that communication can be understood as a soft-realtime problem and how that helps introducing parallelism into protocol-processing.
(12) Hardware Implementation of a RSS Localization Algorithm for Wireless Capsule Endoscopy
M. Cicic, J. Gutierrez Teran, Z. Stamenkovic
Proc. 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 301 (2015)
The paper presents an algorithm for localization of endoscopic capsules inside the human body. The goal is to determine the position of capsules by measuring the power of received electromagnetic signal on the human skin taking into account losses within the body. The algorithm was first developed and simulated in MATLAB. Simulation results prove its high accuracy and indicate the optimal antenna configuration. Then a C model was generated and modified to comply with standards of system-level modeling languages. Catapult C tool was used for system-level synthesis and generation of a RTL hardware model. Low power dissipation and small hardware area were achieved by ASIC implementation in a 130 nm bulk CMOS technology.
(13) An Analysis of OAM Modes for mm-Wave Wireless Communications
D. Cvetkovski, T. Hälsig, B. Lankl, E. Grass
Proc. URSI Atlantic Radio Science Conference (AT-RASC 2015), 1617 (2015)
(maximumMIMO)
(14) Clockwise Randomization of the Observable Behaviour of Crypto ASICs to Counter Side Channel Attacks
Z. Dyka, Ch. Wittke, P. Langendörfer
Proc. Euromicro Conference on Digital System Design (DSD-2015), 551 (2015)
(MaSCH)
Side channel attacks take advantage from the fact that the behavior of crypto implementations can be observed and provides hints that allow revealing keys. In this paper we present a novel approach to prevent SCA or at least to increase the effort to reveal keys significantly. Our approach is based on the fact that there are some functions used in cryptographic operations that can be implemented using different formulae or algorithms. These algorithms come with their individual complexity that results in individual circuits with individual power consumption. Thus, the observable behavior of each of these algorithms is different. So, if the crypto implementation uses these different algorithms whenever it is executed or if the sequence in which the different algorithms are used is randomized, extracting the key gets extremely challenging if not impossible. Applying our idea of is extremely challenging when it comes to ASIC implementation. The point here is that the functionality is fixed and cannot be altered after production. But we discuss that a runtime permutation of the relation between operands and algorithms used for their processing alters the observable behavior in the same way as executing different algorithms. In order to evaluate the effect of our approach we used a Xilinx Spartan 6 FPGA to implement two multipliers consisting of different partial multipliers and measured the corresponding power traces. These measurements show that attacks that compare the shape of power traces e.g. by subtracting them are no longer successful if our approach is applied.
(15) Individualizing Electrical Circuits of Cryptographic Devices as a Means to Hinder Tampering Attacks
Z. Dyka, T. Basmer, Ch. Wittke, P. Langendörfer
http://eprint.iacr.org/2015/442.pdf
(MaSCH)
(16) Bitwise Key Agreement using Wireless Channel Parameters (Work in Progress)
Z. Dyka, D. Kreiser, P. Langendörfer
Proc. 23rd Crypto-Day, 5 (2015)
(ParSec)
(17) SCREAMER – A Demonstrator Chip for Spectral Noise Optimization By Clock Latency Scheduling
X. Fan, O. Schrape, S. Zeidler, M, Krstic, M. Stegmann, I. Jensen, J. Thorsen, T. Bjerregaard
Proc. IEEE International System-on-Chip Conference (SOCC 2015), (2015)
(IC-NAO)
(18) A Ka/X-Band Digital Beamforming Synthetic Aperture Radar for Earth Observation
S. Gao, F. Qin, C. Mao, M. Younis, G. Krieger, S. Glisic, W. Debski, L. Boccia, G. Amendola, E. Arnieri, M. Krstic, P. Penkala, E. Celton
Proc. 7th International Conference on Recent Advances in Space Technologies - Emerging Private Space - (RAST 2015), (2015)
(Different)
(19) Dual-Band Digital Beamforming Synthetic Aperture Radar for Earth Observation
S. Gao, C. Mao, F. Qin, A. Patyuchenko, C. Tienda, M. Younis, G. Krieger, S. Glisic, W. Debski, L. Boccia, G. Amendola, E. Arnieri, M. Krstic, A. Koczor, P. Penkala, E. Celton
Proc. Asia Pacific Microwave Conference (APMC 2015), (2015)
(Different)
(20) Evaluation of a UWB Radar Interface for Low Power Radar Sensors
D. Genschow, J. Kloas
Proc. European Microwave Week (EuMW 2015), 1343 (2015)
This paper describes a novel energy efficient method of converting a number of subsequent UWB Radar pulses
from time domain to digital domain with picosecond resolution.
The system features multi target capability and only a fraction of the energy consumption of traditional Highspeed ADC or
counter-based solutions with much higher resolution.
The method addresses a key challenge of todays UWB radar systems. The power required to convert ultra short signals from time
domain to digital domain today renders UWB radars unattractive for battery powered systems like remote sensor networks. With the proposed system
it is possible to overcome this limitation.
(21) A Time to Digital Converter for use in Ultra Wide Band Radar Sensor Nodes
D. Genschow
Proc. IEEE Topical Conference on Wireless Sensors and Sensor Networks (WISNET 2015), 38 (2015)
This paper introduces a time to digital converter
(TDC) architecture for use with ultra wideband (UWB)
radar systems. The basic functionality is interfacing UWB
RF-Frontends to standard microcontrollers (C) without
the need of high-speed, high precision analog to digital
converters, high performance memories or large high speed
logic. The device achieves asynchronous conversion of multiple
successive events from time domain to digital domain
with picosecond resolution. Primary fields of application
include short range, low power UWB Radars like ground
penetrating Radars, LIDAR systems or other localization
tasks. Secondary fields are ultrasonic measurements and mid
range radars. A self-calibration feature is implemented to
correct certain nonlinearities and imperfections inherent to
the conversion method.
(22) Dynamically Reconfigurable Optical-Wireless Backhaul/Fronthaul with Cognitive Control Plane for Small Cells and Cloud-RANs
E. Grass, J. Gutierrez Teran, K. Grobe, A. Fehske, R. McConnell, M. Barrett, I. Mesogiti, E. Theodoropoulou, G. Lyberopoulos, D. Camps-Mur, J. Paradells-Aspas, N. Vucic, E. Schulz, J. Bartelt, G. Fettweis, I. Berberana, D. Markovic, D. Simic, V. Petrovic, M. Anastasopoulos, A. Tzanakaki, D. Simeonidou, M. Beach, A. Nix, D. Syrivelis, T. Korakis
Proc. 24th European Conference on Networks and Communications (EuCNC 2015), 687 (2015)
(5G-XHaul)
Small Cells, Cloud-Radio Access Networks (CRAN), Software Defined Networks (SDN) and Network Function Virtualization (NVF) are key enablers to address the demand for broadband connectivity with low cost and flexible implementations. Small Cells, in conjunction with C-RAN, SDN, NVF pose very stringent requirements on the transport network. Here flexible wireless solutions are required for dynamic backhaul and fronthaul architectures alongside very high capacity optical interconnects. However, so far there is no consensus on how both technologies can be most efficiently combined.
(23) Impact of Intercell and Intracell Variability on Forming and Switching Parameters in RRAM Arrays
A. Grossi, D. Walczyk, C. Zambelli, E. Miranda, P. Olivo, V. Stikanov, A. Feriani, J. Sune, G. Schoof, R. Kraemer, B. Tillack, A. Fox, T. Schroeder, Ch. Wenger, Ch. Walczyk
IEEE Transactions on Electron Devices 62(8), 2502 (2015)
DOI: 10.1109/TED.2015.2442412, (RRAM (Resistive RAM))
The intercell variability of the initial state and the impact of dc and pulse forming on intercell variability as well as on intracell variability in TiN/HfO2/Ti/TiN 1 transistor – 1 resistor (1T-1R) devices in 4-kb memory arrays were investigated. Nearly 78% of devices on particular arrays were dc formed with a wordline (WL) voltage VWL = 1.4 V and a bitline (BL) voltage VBL = 2.3 V, whereas 22% of devices were not formed due to the combined effect of the extrinsic process-induced intercell variability of the initial state and the intrinsic intercell variability after dc forming. Furthermore, pulse-induced forming with pulsewidths on the order of 10 μs (VWL = 1.4 V and VBL = 3.5 V) caused for 86% of devices a low-resistance state. Using a retry algorithm, we achieve 100% of formed devices. To assess and confirm the nature of the variability during forming operation and during cycling, the quantum point-contact model was considered. The modeling results demonstrate a relationship between the forming and the device performance. The cells requiring high energy for the forming operation, due to impurities in the HfO2 deposition.
(24) System Design Considerations for a PSSS Transceiver for 100 Gbps Wireless Communication with Emphasis on Mixed Signal Implementation
A.R. Javed, K. Krishnegowda, J.C. Scheytt, R. Kraemer
Proc. IEEE Wireless and Microwave Technology Conference (WAMICON 2015) (2015)
(Real100G.com)
(25) Erzeugung diagnostischer Testmuster unter komplexen Constraints
T. Koal, S. Eggersglüß, M. Schölzel
Proc. 27. GI/ITG - Workshop über Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2015), 12 (2015)
(DIAMANT)
In diesem Beitrag wird die Erzeugung diagnosti-scher Testmuster für den softwarebasierten Selbsttest mit zwei verschiedenen ATPG-Werkzeugen betrachtet und verglichen. Kritisch bei der Erzeugung der diagnostischen Testmuster sind die zahlreichen einzuhaltenden komplexen Constraints. Voran-gegangene Arbeiten haben gezeigt, dass diese bei der Verwen-dung klassischer ATPG-Tools zu sub-optimalen Ergebnissen bei gleichzeitig hohen Laufzeiten führen. Werden dagegen Testmus-ter mit einem SAT-basierten ATPG-Verfahren erzeugt, wie in diesem Beitrag vorgeschlagen, so können die Anzahl der Test-muster und die Laufzeit für deren Erzeugung deutlich reduziert werden. Es kann daraus geschlossen werden, dass die in kom-merziellen Werkzeugen eingesetzten Techniken zur Testmuster-erzeugung für stark Constraint-basierte Entwürfe weniger gut geeignet sind.
(26) Ultra-High Speed Wireless Communications: Challenges and Approaches
R. Kraemer
Proc. International Symposium on Signals, Systems and Electronics 2015 (ISSSE 2015), ext. abstr. 1239 (2015)
(27) Collision-Free Full-Duplex UWB Communication Based on the Standard IEEE.802.15.4a
D. Kreiser, S. Olonbayar
Proc. IEEE Wireless Communications and Networking Conference (WCNC 2015), 81 (2015)
(KUSZ)
Using UWB for wireless short range, low rate
communication is attracting growing interest due to its low power
consumption and very high bandwidth. Regarding these qualities,
it is comprehensible that there is an interest in the automation
industry to use ultra-wideband-based wireless sensor nodes to
replace wired systems, to save energy and to save costs without
reducing the reliability of the whole system. For this reason
optimizations of the standard IEEE.802.15.4a were investigated
in this paper with particular emphasis on latency, data rate,
energy efficiency, and reliability. This paper demonstrates the
optimization potential of the official standard
(28) Erweiterte Sicherheit für industrielle Anlagen
J. Krimmling, A. Sänn
chemie & more 1, (2015)
(29) Towards 100 Gbps Wireless Communication in THz Band with PSSS Modulation: A Promising Hardware in the Loop Experiment
K. KrishneGowda, T. Messinger, A.C. Wolf, R. Kraemer, I. Kallfass, J.C. Scheytt
Proc. IEEE International Conference on Ultra-Wideband (ICUWB) (2015)
(Real100G.com)
(30) Reducing Power Consumption in Fault Tolerant ASICs
M. Krstic
Proc. Workshop Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen (2015), 1381 (2015)
(31) Globally Asynchronous Locally Synchronous Design Methodology in ASICs for Wireless Communications
M. Krstic
Proc. 23rd Austrian Workshop on Microelectronics (Austrochip 2015) abstr. (2015)
(32) Design and Performance Measurements of an FPGA Accelerator for a 100 Gbps Wireless Data Link Layer
L. Lopacinski, M. Brzozowski, R. Kraemer, J. Nolte, S. Buechner
Proc. International Symposium on Signals, Systems and Electronics (ISSSE 2015), ext. abstr. 1118 (2015)
(DFG-SPP1655)
(33) Design and Implementation of an Adaptive Algorithm for Hybrid Automatic Repeat Request
L. Lopacinski, M. Brzozowski, R. Kraemer, J. Nolte, S. Buechner
Proc. 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 263 (2015)
(DFG-SPP1655)
(34) 100 Gbps Wireless – Data Link Layer VHDL Implementation
L. Lopacinski, J. Nolte, S. Buechner, M. Brzozowski, R. Kraemer
Proc. of the 18th Conference on Reconfigurable Ubiquitous Computing 2015, (2015)
(DFG-SPP1655)
In this paper, we describe implementation and hardware used for a wireless 100 Gbps data link layer demonstrator. So fast stream processing requires a highly parallelized approach. The timing requirements of the 100 Gbps networks are so demanding that there is no chance to deal with this task as a single stream in a field programmable gate array (FPGA). Due to this reason, we introduce and validate one of possible architectures that can solve the task. The 100 Gbps implementation is explained in details, and the most important parameters of the FPGA design are mentioned.
(35) A 100 Gbps Data Link Layer with a Frame Segmentation and Hybrid Automatic Repeat Request
L. Lopacinski, M. Brzozowski, R. Kraemer
Proc. Science and Information Conference (SAI), 1062 (2015)
(DFG-SPP1655)
(36) Parallel RS Error Correction Structures Dedicated for 100 Gbps Wireless Data Link Layer
L. Lopacinski, J. Nolte, S. Buechner, M. Brzozowski, R. Kraemer
Proc. IEEE International Conference on Ultra-Wideband (ICUWB 2015), (2015)
(DFG-SPP1655)
one of the most calculation intensive operations for a 100 Gbps wireless packet processing is a forward error correction (FEC). We are using standard field programmable gate arrays (FPGAs) to prepare a data link layer demonstrator. Therefore, we need to find a high-parallelized FEC structure for our device. The difficulty is to design the 100 Gbps FEC engine that can be realized in an FPGA. In one of previous papers, we have proposed a solution based on convolutional coding, but the engine consumed equivalent logic of 23 FPGAs [1]. That solution could not be implemented in nowadays FPGAs. In this paper, we propose parallel Reed-Solomon (RS) coders to reach the 100 Gbps throughput. The main task is to select the best candidates from available correction codes for the targeted 100 Gbps wireless communication and fit it to one or two high-end FPGAs. At the end, we demonstrate a system with two FPGAs, which is achieving continuous user data transfer rate of 97 Gbps and is negotiating the RS parameters according to the channel bit error rate
(37) A 100 Gbps Data Link Layer with an Adaptive Algorithm for Forward Error Correction
L. Lopacinski, M. Brzozowski, R. Kraemer
Proc. IEICE Information and Communication Technology Forum (IEICE ICTF), (2015)
(DFG-SPP1655)
(38) Energy Management using the Business Model Approach
B. Matusiak, K. Piotrowski, F. Melo
Proc. of 12th International Conference on the European Energy Market, (2015)
(e-balance)
This paper presents the results of the work on the Business Models (BM) for the e-balance project, which that aims to create an application for balancing local production and consumption of the energy in an intelligent and cost-effective environment, (e-balance 2013-2017; #609132) . The consumer’s needs were investigated and consumers’ profiles were definedbuilt. These profiles were determined by conducting social research in three countries on the needs of requirements for the e-balance application in three countries. The test results provide a good basis forof the first Business Model description for the proposed services, well fitted in with customers’ needs using the BM approach. In this paper the business model verification method for the e-balance project is shortly presented, and the first stage of the BM consideration and results are described.
(39) Internet of Things in e-Balance Project
B. Matusiak, K. Piotrowski, J. Zielinski
Proc. Zarzadzanie Energia i Teleinformatyka (ZET 2015), (2015)
(e-balance)
The aim of this paper is to consider the main principles of the Internet of Things (IoT) and Internet of Everything (IoE) within the context of building a Business Model (BM) and data flow limitations for the e-balance EU project. Authors have addressed the need of creation of a business model type, which will be dedicated to the concept of the Internet of Things. Initial results for the e-balance platform with technical and organizational architecture and BM have also been presented. This application is in the area of IoT and Smart Grid (SG). One of the key conclusions of this paper is a claim that in the near future, energy utilities should seriously rethink their BM and the possibility of designing new services in digitally intensive environments using smart appliances and sensors.
(40) Multi-Level 20 Gbit/s PSSS Transmission Using a Linearity-Limited 240 GHz Wireless Frontend
T. Messinger, K. KrishneGowda, F. Boes, D. Meier, A. Wolf, A. Tessmann, R. Kraemer, I. Kallfass
Proc. IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS 2015), (2015)
(Real100G.com)
(41) Concurrent Generation of Pseudo Random Numbers with LFSR of Fibonacci and Galois Type
E. Milovanovic, M. Stojcev, I. Milovanovic, T. Nikolic, Z. Stamenkovic
Computing and Informatics 34(4), 941 (2015)
We have considered implementation of parallel test pattern generator based on a linear feedback shift register (LFSR) with multiple outputs used as a building block in buili-in-self-test (BIST) design within SoC. The proposed design can drive several circuits under test (CUT)simultaneously. The mathematical procedure for concurrent pseudo random number (PRN) generation is described. We have implemented LFSRs that generate two and three PRNs in FPGA and ASIC technology. The design was tested at the operating frequency of 400 MHz.
Performance which relate to silicon area, dynamic power consumption and speed of operation were estimated. Synopsis Design Compiler and IHP's 130 nm CMOS ASIC design kit were used for synthesis, routing and mapping of LFSR design. Total silicon area of the LFSR with three parallel outputs and polynomial of degree 32, is 0.012mm2, and dynamic power consumption is less than 1.3 mW. Obtained results indicate that the area overhead and power consumption are small enough and proportional to the degree of feedback polynomial.
(42) Software-Based Self-Repair for Heterogenous Multi-Core Systems
S. Müller, H.T. Vierhaus, M. Schölzel
Proc. Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'15), 67 (2015)
(DIAMANT)
This paper describes a software-based technique for building heterogeneous fault tolerant multi-core systems, which are able to handle temporary and permanent hardware faults autonomously in two system layers. The fault tolerance technique relies on a single concept for adapting the binary code of the user application to the current fault state of a single core. Thereby this scheme is used either for a local repair of each core or for a glob-al repair. By the global repair, the task assigned to a faulty core may be rescheduled to another core that provides enough re-sources for the execution of the task. Thereby the local repair scheme is reused for the adaptation of the rescheduled task. It is shown that the reliability of a multi-core system can be improved significantly, when using the global repair together with the local repair instead of using the local repair only.
(43) A Multi-Layer Software-Based Fault-Tolerance Approach for Heterogenous Multi-Core Systems
S. Müller, T. Koal, S. Scharoba, H.T. Vierhaus, M. Schölzel
Proc. IEEE Latin American Test Symposium (LATS 2015), (2015)
(DIAMANT)
(44) Polarity Reception for IR-UWB in Wireless Fading Channel
S. Olonbayar, D. Kreiser, R. Kraemer, G. Fischer, D. Martynenko, O. Klymenko
Proc. European Wireless (EW2015), 283 (2015)
(KUSZ)
A digital baseband was designed and implemented according to the standard IEEE802.15.4a both in FPGA and as well as ASIC. The baseband supports data rates 850 Kb/s, 6.81 Mb/s and 27.24 Mb/s running at the clock speed of 31.2 MHz. The transmitter and receiver were tested by introducing various distortions to the signal being received. The baseband was shown to be fully functional being able to receive even under heavy distortion. Both the synchronization and data detection performance are robust. The baseband tested with a FPGA was further made as an ASIC in the 250 nm BiCMOS technology from IHP, Germany.
(45) Autonomous Execution of Reliable Sensor Network Applications on Varying Node Hardware
St. Ortmann, P. Langendörfer
Handbook of Research on Innovations in Systems and Software Engineering, IGI Global, 602 (2015)
(StrokeBack)
(46) Assessing the Success of Stroke Rehabilitation with Wearable Sensors
St. Ortmann, D. Biswas, A. Cranny, K. Maharatna, J. Achner, J. Klemke
Proc. Technically Assisted Rehabilitation (TAR 2015), (2015)
(StrokeBack)
(47) A Power-Gated Sensor Node Microcontroller for Security Applications
G. Panic, T. Basmer, O. Schrape
Proc. International Symposium on Signals, Systems and Electronics (ISSSE 2015), ext. abstr. 1576 (2015)
(48) Low Power Design Techniques
G. Panic
Proc. Informatik 2015, 1379 (2015)
(Telediagnostics)
The demand for portable electronic devices that offer greater functionality and performance at lower costs and smaller sizes has increased rapidly. This market trend is driving the need for efficient System-on-Chip (SoC) designs, where the power arises as the one of the biggest problems. The microprocessor design has traditionally focused on dynamic power (active power) consumption as the limiting factor in system integration. As technology has shrunk to 90 nm and below, static power (leakage power) is posing new challenges to low power design.
Historically, CMOS technology has dissipated much less power than earlier technologies such as transistor-transistor and emitter-coupled logic. In fact, when not switching, CMOS transistors consumed negligible power. However, with the increase in device speed and chip density, the power of CMOS increased dramatically. According to technology trends, the dynamic power per device decreases over the time. However, if it is assumed that the number of on-chip devices doubles every two years, total dynamic power increases on per-chip basis. Additionally, the shrinking of feature sizes makes static power dissipation grow exponentially. Consequently, the packaging and cooling costs as well as the limited power capacity of batteries become unsustainable.
The reduction of power growth below the predicted numbers has become one of the most important tasks for designers. To cope with the power challenges, a number of advanced power saving techniques have been developed that can efficiently target both static and dynamic power loss. The existing and future trends in low power design show that efficient power management is greatly determined by design decisions made in early phase of system design. Thus, the selection of power saving strategy becomes one of the most important challenges for designers.
This presentation starts by covering basic sources of power consumption in CMOS, including both static and dynamic power loss. Furthermore, the presentation gives a detailed overview on existing low power techniques including standard techniques developed for mature technologies, process-level techniques, and advanced low power techniques used in deep-submicron CMOS. Also, some attention is given to the selection of power saving strategy for design and early power estimation. Finally, future trends in low power design are discussed as well.
(49) Activity Profiling and Power Estimation for Embedded Wireless Sensor Node Design
G. Panic, Z. Stamenkovic
Proc. 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 231 (2015)
(50) Highly Integrated Dual-Band Digital Beamforming Synthetic Aperture Radar
A. Patyuchenko, M. Younis, G. Krieger, Z. Wang, S. Gao, F. Qin, C. Mao, S. Glisic, W. Debski, L. Boccia, G. Amendola, E. Arnieri, M. Krstic, E. Celton, P. Penkala
Proc. European Radar Conference (EuRAD), 1 (2015)
(Different)
(51) Innovative Methodology to Define Stakeholders’ Requirements for Smart Systems
J. Peralta, N. Jimenez, A. Casaca, F. Melo, K. Piotrowski
Proc. of the 23rd International Conference and Exhibition on Electricity Distribution (CIRED 2015), (2015)
(e-balance)
The presented methodology aims at facilitating the definition of stakeholders’ requirements for new system architectures. It is composed of 4 steps which allow identifying the links between stakeholders and/or systems and writing the necessary information. A preliminary step is necessary and focused on the conceptual map and template design. The former is a block diagram that includes all the stakeholders, management units and energy systems and their relations. The latter is a self-questionnaire to describe the requirements. This approach has allowed defining 204 requirements for the 28 use cases of the e-balance project by 10 researchers of different expertise areas without ambiguities. The requirement details have also allowed prioritizing the most relevant requirements with a statistical approach, what has allowed optimising the project planning. Finally, both the methodology and the first outputs and conclusions obtained of the requirement implementation in e-balance are explained.
(52) Implementation of Coherent IEEE 802.15.4 Receiver on Software Defined Radio Platform
U. Pesovic, D. Gliech, P. Planinsic, Z. Stamenkovic, S. Randjic
Proc. 23rd Telecommunications Forum (TELFOR 2015), 224 (2015)
Coherent receivers have better demodulation characteristics then non-coherent receivers when demodulating signals with higher bit error probability. They require synchronization with received signal using preamble which is transmitted at beginning of IEEE 802.15.4 packet. Software defined radio doesn’t allow adjustment of local oscillator frequency using Costas Loop circuitry, so synchronization need to be performed by software synchronization in baseband. This paper represents implementation of coherent IEEE 802.15.4 receiver on software defined radio.
(53) A Fast Link Initialization Protocol for Beam Steering based Cellular Backhaul Systems
M. Petri, M. Ehrig, M. Günther
Network Protocols and Algorithms 7(2), 113 (2015)
To deal with the enormous increase of mobile data traffic, new cellular network topologies are necessary. The reduction of cell area and the usage of light-weighted base stations serving only a handful of users, commonly known as the small cell approach, seems to be a suitable solution addressing changes in user expectations and usage scenarios. This paper is an extended version of [1], where current challenges of small cell deployments were presented from a backhaul perspective. A mesh-type backhaul network topology based on beam-steering millimeter-wave systems was proposed as a future-proof solution. In this paper, we focus on a link initialization protocol for beam steering with highly directive antennas. Special requirements and problems for link setup are analysed. Based on them, a fast protocol for link initialization is presented and it is evaluated in terms of the resulting initialization speed-up compared to state-of-the-art solutions. Furthermore, a potential approach for extending the fast link initialization protocol to support point-to-multipoint connections is given.
(54) Verbesserter TMR-Strahlungsschutz für ASIC-Layouts
V. Petrovic, G. Schoof, M. Krstic
Proc. 27. GI/ITG - Workshop über Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2015), 82 (2015)
(Different)
(55) Designflow for Radhard TMR Flip-Flops
V. Petrovic, M. Krstic
Proc. 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 203 (2015)
(Different)
Protection against radiation effects in digital ASICs chip can be reached using different design approaches. One of the popular approaches for increasing the reliability is the hardware triplication. However, the triplication of hardware doesn’t mean that the problems with radiation effects are automatically solved. The automatic random placement of standard cells can bring the higher power consumption as well as more occupied silicon area, with marginal improvement of the linear energy transfer threshold (LET) value. Additionally, the TMR approach usually requires changes in the of standard design ASIC flow, even requesting significant modifications of RTL code. In this paper, we will investigate the issues of design flow for TMR flip-flops, addressing both issues of compliance to the standard ASIC design methodology, enabling the use of non-modified RTL code, as well as layout generation of radhard TMR flip-flops, based on standard non-hardened flip-flop components.
(56) Bezpieczenstwo w Systemach Smart Grid na Przykladzie Projektu E-Balance
K. Piotrowski, J.J. Peralta Escalante
Zdalne Odczyty: Kryptologigia a Biznes - Bezpieczenstwo Stosowane, Wydawnictwo BTC, 87 (2015)
(e-balance)
(57) Bezpieczenstwo w Systemach Smart Grid na Przykladzie Projektu E-Balance
K. Piotrowski, J.J. Peralta Escalante
Proc. Konferencja Naukowo-Przemyslowa: Kryptologia a Biznes, Bezpieczenstwo Stosowane (KBBS), I.42015 (2015)
(e-balance)
(58) Neue Standards für WIFI - Um die Ecke gefunkt
J. Rähm, M. Kloiber, E. Grass
Deutschlandfunk – Computer und Kommunikation, (2015)
(Prelocate)
(59) Customer Integration and Voice-of-Customer Methods in the German Automotive Industry
A. Rese, A. Sänn, F. Homfeldt
International Journal of Automotive Technology and Management (IJATM) 15, 1 (2015)
(ESCI)
(60) Configurable Software Defined Radio System for two Way Time of Flight Ranging
V. Sark, E. Grass
Proc. International Symposium on Signals, Systems and Electronics 2015 (ISSSE 2015), ext. abstr. 1402 (2015)
(PROWILAN)
(61) PHY-Layer Limitations of Distance Measurements Using Round Trip Time of Flight (RTToF)
V. Sark, E. Grass
Proc. XII. International Conference on Electronics, Telecommunications, Automation and Informatics (ETAI), 11.1 (2015)
(Prelocate)
Many popular applications require precise ranging and localization. This is
mainly needed in indoor scenarios and urban area scenarios, i.e. where
GPS precision is poor or not available at all. Another, also popular,
requirement is the use of the same radio interface for data communication and
ranging.
In this paper, a general overview of the physical layer limitations are presented.
The Round Trip Time of Flight (RTToF) method for distance measurement (ranging) is
used. The first limitation addressed is the noise. Some proposed solutions were
tested and confirmed. The second limitation is the finite channel bandwidth. It
will distort the signal, so precise estimation of the distance is difficult.
The ranging (localization) system also introduces limitations due to the hardware used.
The finite sample rate of the A/D converter is a common system limitation. Interpolation is one good and standard solution.
Different interpolation methods were tested and some results are presented here.
Also, a solution for minimization of the clock inaccuracy error is proposed.
At last, the NLOS problem is addressed. One solution for detection of LOS/NLOS
scenario is proposed and preliminary simulation results are presented.
(62) An FPGA Debugging Tool for High Speed Multi-Channel Data Converter Add-on Boards
V. Sark, J. Gutierrez Teran, E. Grass
Proc. XII International Conference on Electronics, Telecommunications, Automation and Informatics (ETAI), 5.1. (2015)
(Prelocate)
Future wireless communication systems are constantly under pressure
for supplying more and more bandwidth. The next generation wireless
systems are expected to offer data rates of 100 Gbps. Also, precise
localization is getting more and more interest from the research community.
High speed data communication
and precise RF ranging require high speed data converters (A/D and D/A).
Testing and configuring these converters can be a painstaking process,
even if reconfigurable hardware, e.g. Field Programmable Gate Array (FPGA)
are available. The debugging tools supplied by the FPGA vendors, usually
the initial choice for this purpose, offer very poor performance. Setting up
and testing of many parameters takes an enormous amount of time when using these
tools. In this paper, a debugging tool for testing high speed data converters
is presented. The tool was developed in order to test 1 Gsps A/D and D/A converters
on an FPGA platform. The tool allows easy programming of common repetitive operations.
Thus, the time needed for deploying high speed data converters on an FPGA system
is extremely reduced. On the other hand, the tool allows automatic
configuration of some parameters, which is also presented in this paper.
(63) Multi-Way Ranging With Clock Offset Compensation
V. Sark, E. Grass, J. Gutierrez Teran
Proc. International Scientific Conference on Advances in Wireless and Optical Communications (RTUWO 2015), (2015)
(Prelocate)
This paper presents a new approach for reducing the ranging error due to the crystal clock offset. This approach is applicable in cooperative ranging methods like N-Way or Multi-Way ranging, which are mainly used in Wireless Sensor Networks (WSN). Leaving the crystal clock offset error uncompensated leads to propagation of the ranging error through the WSN. In our approach, the crystal clock offset between the nodes is estimated and used to compensate the ranging error.
The main advantage of our approach is the smaller number of transmissions compared to other crystal clock offset mitigation techniques. This reduces the energy consumption and minimizes the wireless medium usage for ranging purposes. The simulation results show that, even when a coarse estimation of the clock offset is performed, it has a significant impact on the reduction of the ranging error.
(64) Reduction of the Clock-Offset Induced Error in Multi-Way Ranging Scenarios
V. Sark, E. Grass, J. Gutierrez Teran
Proc. 1st International Scientific Conference on Advances in Wireless and Optical Communications 2015, RTU Press Riga, 158 (2015)
(Prelocate)
This paper presents a new approach for reducing the ranging error due to the crystal clock offset. This approach is applicable in cooperative ranging methods like N-Way or Multi-Way ranging, which are mainly used in Wireless Sensor Networks (WSN). Leaving the crystal clock offset error uncompensated leads to propagation of the ranging error through the WSN. In our approach, the crystal clock offset between the nodes is estimated and used to compensate the ranging error.
The main advantage of our approach is the smaller number of transmissions compared to other crystal clock offset mitigation techniques. This reduces the energy consumption and minimizes the wireless medium usage for ranging purposes. The simulation results show that, even when a coarse estimation of the clock offset is performed, it has a significant impact on the reduction of the ranging error.
(65) On Implementation of TPMS receiver for Traffic Data Collection
N. Savic, M. Krstic
Proc. International Symposium on Signals, Systems and Electronics (ISSSE 2015), ext. abstr. 1363 (2015)
(66) On the Feasibility of Handling Manufacturing Faults in Embedded Memories by Software Means
M. Schölzel, P. Skoncej, F. Vater
Proc. IEEE International Workshop of Electronics, Control, Measurement, Signals and their application to Mechatronics, 161 (2015)
(MOTARO)
(67) On the Feasibility of Handling Manufacturing Faults in Embedded Memories by Software Means
M. Schölzel, P. Skoncej, F. Vater
Proc. IEEE International Workshop of Electronics, Control, Measurement, Signals and their application to Mechatronics, 161 (2015)
(DIAMANT)
(68) Software-based Repair for Memories in Tiny Embedded Systems
M. Schölzel, P. Skoncej, F. Vater
Proc. European Test Symposium (ETS), (2015)
(MOTARO)
This paper presents a software-based technique for handling permanent faults in low-cost memories for embedded systems. Basically the technique is based on an adaptation of the program code that avoids the usage of faulty memory words. With this technique it is possible to handle permanent manufacturing faults as well as permanent aging faults in simple and cheap memories without any kind of hardware-based fault management in the memory. This is of particular interest for long living low-cost embedded systems like sensor nodes that make use of such memories. Different methods for handling memory faults in data and program memory are discussed. The methods for program memories are evaluated with flash memory devices. Based on real test data for the flash memories it is shown that with the software-based technique a significant amount of hardware-overhead in the memory can be avoided without losing the capabilities of handling memory faults.
(69) Software-based Repair for Memories in Tiny Embedded Systems
M. Schölzel, P. Skoncej, F. Vater
Proc. European Test Symposium (ETS), (2015)
(DIAMANT)
This paper presents a software-based technique for handling permanent faults in low-cost memories for embedded systems. Basically the technique is based on an adaptation of the program code that avoids the usage of faulty memory words. With this technique it is possible to handle permanent manufacturing faults as well as permanent aging faults in simple and cheap memories without any kind of hardware-based fault management in the memory. This is of particular interest for long living low-cost embedded systems like sensor nodes that make use of such memories. Different methods for handling memory faults in data and program memory are discussed. The methods for program memories are evaluated with flash memory devices. Based on real test data for the flash memories it is shown that with the software-based technique a significant amount of hardware-overhead in the memory can be avoided without losing the capabilities of handling memory faults.
(70) Integrated Circuit Failure Mechanisms and the Impacts of Technology Downscaling
A. Simevski
Proc. International Conference on Electronics, Telecommunications, Automation and Informatics (ETAI 2015), 5.5 (2015)
Integrated circuit reliability is of primary impor-
tance for applications in space, aviation, car safety, medical
equipment, etc. This paper presents an overview of the reliability
failure mechanisms of integrated circuits that lead to transient
and permanent faults. If special care is not taken, these faults
may further introduce errors and system failures. A classification of faults and failure mechanisms is given, followed by a comprehensive description of the most significant failure mechanisms, i.e., aging (wear out) and single event effects. The impact of integrated circuit technology downscaling on these effects is also revisited. CMOS technology, as the most popular one, is in the main focus.
(71) Softwarebasierte Selbstreparatur von Flash-Speichern für fehlertolerante mikrocontroller-basierte Systeme
P. Skoncej, F. Mühlbauer, M. Schölzel
Proc. Workshop für Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen, Informatik, 1461 (2015)
(DIAMANT)
(72) Softwarebasierte Selbstreparatur von Flash-Speichern für fehlertolerante mikrocontroller-basierte Systeme
P. Skoncej, F. Mühlbauer, M. Schölzel
Proc. Workshop für Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen, Informatik, 1461 (2015)
(MOTARO)
(73) Projekt Smartie: Bezpieczenstwo, Prywatnosc i Poufnosc w Zarzadzaniu Danymi w Inteligentych Miastach
A. Sojka-Piotrowska
Zdalne Odczyty: Kryptologia a Biznes - Bezpieczentswo Stosowane, Wydawnictwo BTC, 99 (2015)
(SMARTIE)
The growing popularity of using the Internet of Things in large-scale, mission-critical environments, e.g. cities, causes the need for investigation of new techniques ensuring the security and trust for data exchange between Internet of Things devices and the data owners or consumers. The main objective of SMARTIE project is to create a distributed framework for smart city applications sharing large volumes of heterogeneous data. The purpose of this framework is the provision of end-to-end security and trust in information delivery for decision-making purposes taking the data owners’ privacy into consideration. The feasibility and utility of SMARTIE approach will be tested in real environments (Traffic, Transport and Energy) with real users of the city infrastructures. The cities involved are Novi Sad (Serbia), Murcia (Spain) and Frankfurt an der Oder (Germany). This paper presents the security approach developed within the SMARTIE project.
(74) Projekt Smartie: Bezpieczenstwo, Prywatnosc i Poufnosc w Zarzadzaniu Danymi w Inteligentych Miastach
A. Sojka-Piotrowska
Proc. II Konferencja Naukowo-Przemyslowa: Kryptologia a Biznes, Bezpiechenstwo Stosowane (KBBS 2015), (2015)
(SMARTIE)
The growing popularity of using the Internet of Things in large-scale, mission-critical environments, e.g. cities, causes the need for investigation of new techniques ensuring the security and trust for data exchange between Internet of Things devices and the data owners or consumers. The main objective of SMARTIE project is to create a distributed framework for smart city applications sharing large volumes of heterogeneous data. The purpose of this framework is the provision of end-to-end security and trust in information delivery for decision-making purposes taking the data owners’ privacy into consideration. The feasibility and utility of SMARTIE approach will be tested in real environments (Traffic, Transport and Energy) with real users of the city infrastructures. The cities involved are Novi Sad (Serbia), Murcia (Spain) and Frankfurt an der Oder (Germany). This paper presents the security approach developed within the SMARTIE project.
(75) A Secure Isolation of Software Activities in Tiny Scale Systems
O. Stecklina
Proc. Ph.D. Forum on Pervasive Computing and Communications (PerComm), 245 (2015)
(UNIKOPS)
All visions of pervasive computing share the idea of smart,
small, and cheap devices that improve our everyday life. But
devices like smart sensor or deeply embedded controllers as
fundamental part of cyber-physical systems (CPSs) are also
able to do many things that we do not want. In fact, they will
be always vulnerable to doing the bidding of attackers, to the
detriment of their owners. This work presents a concept for a
security architecture for tiny scale systems (TSSs) with their
limited resources. The concept is based on well-understood
technologies of desktop systems, which are tailor-made for
TSSs in a compile- and run-time co-design process.
(76) Intrinsic Code Attestation by Instruction Chaining for Embedded Devices
O. Stecklina, P. Langendörfer, F. Vater, T. Kranz, G. Leander
Proc. 11th EAI International Conference on Security and Privacy in Communication Networks, (2015)
(UNIKOPS)
In this paper we present a novel approach to ensure that
no malicious code can be executed on resource constraint devices such
as sensor nodes or embedded devices. The core idea is to encrypt the
code and to decrypt it after reading it from the memory. Thus, if the
code is not encrypted with the correct key it cannot be executed due
the incorrect result of the decryption operation. A side effect of this is
that the code is protected from being copied. In addition we propose to
bind instructions to their predecessors by cryptographic approaches. This
helps us to prevent attacks that reorder authorized code such as return-oriented programming attacks. We present a thorough security analysis
of our approach as well as simulation results that prove the feasibility
of our approach. The performance penalty as well as the area penalty
depend mainly on the cipher algorithm used. The former can be as small
as a single clock cycle if Prince a latency optimized block cipher is used,
while the area overhead is 45 per cent for a commodity micro controller
unit (MCU).
(77) A Novel Compact Dual-Band Bandpass Waveguide Filter
S. Stefanovski, M. Potrebic, D. Tosic, Z. Stamenkovic
Proc. 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 51 (2015)
A novel design of second-order dual-band H-plane bandpass waveguide filter is presented in this paper. Filter design is relatively simple and is based on the use of complementary split ring resonators, implemented as metal septa, with properly shaped slots, in the transverse planes of the standard (WR-90) rectangular waveguide. The positions of the resonators on the same septum are chosen in such a manner that there is no mutual coupling between them. This approach is used for the design of the waveguide resonator with two resonant frequencies (9 GHz and 11 GHz). Further, the second-order dual-band bandpass waveguide filter, with symmetrically positioned folded septa, is presented. The equivalent circuits of the considered resonators and filters are developed. The proposed dual-band bandpass filter design is verified by a good agreement of the filter responses obtained for three-dimensional electromagnetic models and equivalent microwave circuits. Finally, the method for filter miniaturization is introduced and applied to the second-order dual-band filter. The required filter response is preserved.
(78) Autonomous Sensor Capsule for Usage in Bioreactors
N. Todtenberg, S.-T. Schmitz-Hertzberg, J. Klatt, F. Jorde, B. Jüttner, K. Schmalz, R. Kraemer
IEEE Sensors Journal 15(7), 4093 (2015)
(Telediagnostics)
An autonomous biochemical sensor capsule for the remote monitoring of an algae culture cultivated in a photobioreactor is presented. The encapsulated system has a spherical shape with a diameter of 44 mm. Radio communication with a carrier frequency of 433 MHz is used to transfer the acquired sensor data in the bioreactor to a base station outside. Experiments with the first prototype inside the bioreactor filled with nutrient solution were performed to determine the reliability of the communication link. The Packet Error Rate (PER) converged to 26 % and the path loss on average was 96 dB. The functionality of the signal processing chain of acquired biochemical sensor values was evaluated using an experimental setup: Our second capsule prototype with potentiometric sensors demonstrates the pH-measurements of different buffer solutions trickled on the sensor electrodes with a pipette.
(79) Securing the Internet of Things - Security and Privacy in a Hyperconnected World
E.Z. Tragos, H.C. Pöhls, R. Staudemeyer, D. Slamanig, A. Kapovits, S. Suppan, A. Fragkiadakis, G. Baldini, R. Neisse, P. Langendörfer, Z. Dyka, Ch. Wittke
Building the Hyperconnected Society - Internet of Things Research and Innovation - Value Chains, Ecosystem and Markets
(80) Multiple Fault Testing in Systems-on-Chip with High-Level Decision Diagrams
R. Ubar, M. Schölzel, S.A. Oyeniran, H.T. Vierhaus
Proc. IEEE International Design & Test Symposium (IDT), 66 (2015)
(DIAMANT)
(81) Compiler-Centered Microprocessor Design (CoMet) - From C-Code to a VHDL MOdel of an ASIP
R. Urban, M. Schölzel, H.T. Vierhaus, E. Altmann, H. Selig
Proc. 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 17 (2015)
(82) Möglichkeiten der Nutzung von RRAM in Low-Power Microcontrollern
F. Vater, G. Panic, S. Schölzel
Proc. Workshop Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen (Informatik 2015), INFORMATIK 2015, Lecture Notes in Informatics (LNI), Gesellschaft für Informatik, 1475 (2015)
(DIAMANT)
Die Energieeffizienz aktueller Microcontroller wird durch die aggressive Nutzung von verschiedenen Ruhe- und Schlafmodi erreicht. Eine vollständige Abschaltung des Microcontrollers ist dabei aufwendig, da die Zustände in flüchtigen Speichern nicht beibehalten werden. Nichtflüchtige Speicher bieten die Möglichkeit auf einfach Weise die Daten zwischenzuspeichern. In diesem Paper werden die verschiedenen Speichertechnologien in Hinblick auf ihre Energieeffizenz unter Berücksichtigung von Schreib-/Lesegeschwindigkeit sowie Lebensdauer untersucht. Dabei findet eine sehr genaue und technologienahe Simulation auf Basis von Transistormodellen statt.
(83) Neue Methodik zur Implementierung fehlertoleranter pipeline-basierter Architekturen
S. Weidling, M. Krstic
Proc. 27. GI/ITG - Workshop über Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2015), 86 (2015)
(84) Influence of Electrical Circuits of ECC Designs on Shape of Electromagnetic Traces Measured on FPGA
Ch. Wittke, Z. Dyka, P. Langendörfer
über: http://eprint.iacr.org/
(MaSCH)
Side channel attacks take advantage from the fact that the behavior of crypto implementations can be observed and provides hints that simplify revealing keys. The energy consumption of the chip that performs a cryptographic operation depends on its inputs, on the used cryptographic key and on the circuit that realizes the cryptographic algorithm. An attacker can experiment with different inputs and key candidates: he studies the influence of these parameters on the shape of measured traces with the goal to extract the key. The main assumption is here that the circuit of the attacked devices is constant. In this paper we investigated the influence of variable circuits on the shape of electromagnetic traces. We changed only a part of the cryptographic designs i.e. the partial multiplier of our ECC designs. This part calculates always the same function in a single clock cycle. The rest of the design was kept unchanged. So, we obtained designs with significantly different circuits: in our experiments the number of used FPGAs LUTs differs up to 15%. These differences in the circuits caused a big difference in the shape of electromagnetic traces even when the same data and the same key are processed. Our experiments show that the influence of different circuits on the shape of traces is comparable with the influence of different inputs. We assume that this fact can be used as a protection means against side channel attacks, especially if the cryptographic circuit can be changed before the cryptographic operation is executed or dynamically, i.e. while the cryptographic operation is processed.
(85) A Survey about Testing Asynchronous Circuits
St. Zeidler, M. Krstic
Proc. 22nd European Conference on Circuit Theory and Design (ECCTD 2015), (2015)
(Design for Testability)
Even though the asynchronous design methodology is considered to be a promising solution to upcoming challenges of designing complex integrated circuits (ICs), it is not widely accepted by the industry. Besides the lack of mature design tools, a further key inhibitor of using this design style is the widespread assumption that asynchronous circuits are difficult to test due to problems with system timing during test, nondeterminism, and difficulties with applying standard test approaches such as scan. However, there is a huge variety of approaches to handle these testing issues. This paper summarizes the different available test methodologies for asynchronous and globally-asynchronous locally-synchronous (GALS) designs and addresses their strengths and weaknesses. Moreover, it gives an overview of a methodology for testing based on the use of specific test processor, developed by IHP.
(86) A Design Preconditioning Flow for Low-Noise Circuits
St. Zeidler, X. Fan, O. Schrape, M. Krstic
Proc. 18th IEEE International Symposium Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 191 (2015)
(IC-NAO)
Mitigating switching noise in highly complex integrated circuits (ICs) is one of the challenging issues in current design flows. The common way to optimize the noise characteristics is to apply current shaping techniques, which introduce clock skew to distribute the switching activity of the circuit. However, this is typically done at late backend design stages, i.e., in layout after cell placement, which limits the maximum clock phase insertion between the domains. Therefore, we propose a novel preconditioning flow, which considers noise optimization up frontend design, \ie, design coding stage. By this, RTL-level techniques, such as clock inversion, can be applied to further optimize the noise characteristics, while common current shaping strategies can still be applied in the backend design.
M. Andjelkovic, V. Petrovic, Z. Stamenkovic, G. Ristic, G. Jovanovic
Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 255 (2015)
A single event latchup protection switch (SPS) has been developed in the IHP 250 nm bulk CMOS technology. The SPS has been designed as a standard library cell intended for implementation in the radiation-tolerant application specific integrated circuits (ASICs). It provides detection of single event latchup and subsequent shut-down of power supply to critical elements within the chip to restore the normal operation. However, the SPS cell might be also susceptible to single event transients. In that regard, this work presents the simulation-based analysis of the response of SPS cell in the case of single event transients. The dependence of the single event transient response with respect to the injected charge, supply voltage, load and sensing transistor size has been analyzed.
(2) Circuit-Level Simulation of Single Event Transients in an On-Chip Single Event Latchup Protection Switch
M. Andjelkovic, V. Petrovic, Z. Stamenkovic, G.S. Ristic
Journal of Electronic Testing 31, 275 (2015)
The SPS is intended for implementation in radiation tolerant integrated circuit designs, and it provides detection of single event latch-up effect and shut-down of power supply to critical elements within the chip to restore the normal operation. It is based on a PMOS transistor which acts as a latchup sensor, and includes additional PMOS and NMOS transistors for controlling the sensing transistor and interfacing to the external control logic. The initial simulation has confirmed the SPS's functionality in the case of single event latchup, and experimental investigation has proven that the SPS is immune to single event latchup for LET values of up to 74.8 MeV∙cm2/mg. This work extends the previous research by introducing the performance evaluation of the SPS cell in the case of single event transient (SET) effects. The duration of the SET-induced voltage pulse at the SPS’s output was investigated through circuit-level simulations using the square pulse current generator for modeling the SET-induced current. The critical charge necessary to cause the change of voltage level at SPS’s output was estimated to be around 245 fC, and for higher values of injected charge the duration of the SET-induced voltage pulse increased linearly until a saturation level was reached. The duration of the SET-induced voltage pulse also increased with increase of operating temperature. However, with increase of the supply voltage and sensing transistor’s channel length, the SET-induced voltage pulse duration decreased. Hence, as the voltage supply cannon be changed, by increasing the channel width of the sensing transistor it is possible to enhance the SPS’s immunity to SET effects.
(3) A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates
M. Babic, M. Krstic
Proc. 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 217 (2015)
(GASEBO)
The objective of this paper is to propose a coarse model for coupling of switching noise through lightly doped substrates. This could be achieved by assuming a regular placement of substrate contacts in a digital aggressor. Additionally, an approximation of equal ground bounce in an entire digital aggressor is applied. The proposed model is aimed for use as an estimation before placement, i.e. before knowing the exact layout details. Consequently, this model could be utilized as a guideline for determining the optimal floorplanning of digital blocks with regards to substrate noise coupling to sensitive analog modules. Extraction code is written in MATLAB. Evaluation of the model has shown that reasonable accuracy of the estimation could be expected and that the proposed method could be used as a baseline for early exploration of substrate noise characteristics of the design.
(4) Frequency-Domain Modeling of Ground Bounce and Substrate Noise for Synchronous and GALS Systems
M. Babic, X. Fan, M. Krstic
Proc. 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2015), (2015)
(GASEBO)
In this work, the ground bounce noise has been modeled and analyzed in frequency domain, for both synchronous and GALS (globally synchronous, locally synchronous) systems. The analysis has been performed analytically, and validated by numerical simulations in MATLAB. Package parasitics and power distribution network have been coarsely modeled by a simple lumped model, while switching currents have been modeled as periodic triangular pulses. Dominant components of spectrum are determined, and the impact of their distribution on the requirements for substrate modeling has been discussed. It has been concluded that resistive substrate approximation introduces large errors for systems with small decoupling capacitances, while it can be satisfactory for systems with large decoupling capacitances.
(5) Modeling of Substrate Noise Coupling and Ground Bounce for GALS Systems
M. Babic, M. Krstic
Proc. Annual DCPS (Dependable Cyber-Physical Systems) Evaluation Workshop, 70 (2015)
(GASEBO)
This paper presents an overview of some of the early results achieved within the DFG project GASEBO. The final goal of the project is to explore the possibility of actively reducing substrate noise in BiCMOS technologies by applying GALS (globally asynchronous, locally synchronous) methodology in digital design. In order to be able to evaluate such system level methodology, the appropriate high abstraction level models for noise generation and noise propagation, which can be used for coarse estimations in early phases of the design flow, had to be developed. This paper presents a coarse model for estimation of substrate noise propagation in BiCMOS technologies, and a frequency-domain model for ground bounce in both synchronous and GALS systems. Both models have been implemented in MATLAB code, and are intended to be used for comparisons between GALS and synchronous designs in terms of substrate noise, as well as for developing an optimal GALS methodology for substrate noise reduction.
(6) GALS Methodology for Substrate Noise Reduction in BiCMOS Technologies
M. Babic, M. Krstic
Proc. Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), (2015)
(GASEBO)
(7) Towards an OS-independent Code-Update Function for WSN
T. Basmer, I. Kabin, M. Schölzel
Proc. 14. GI/ITG KuVS Fachgespräch "Sensornetze", 61 (2015)
(DIAMANT)
This paper presents the concept of an operating system independent code update function for wireless sensor networks. The code update is separated from the application and the operating system in order to provide a basic input/output functionality that can be used to update the whole operating system. Moreover, we show that such an I/O-functionality can be used to handle particular faults in sensor nodes making them more reliable. In order to achieve this goal it is important that the code-update functionality has a very small memory foot-print.
For that reason we present preliminary results of a prototype
implementation demonstrating the feasibility of the concept.
(8) Recognizing Upper Limb Movements with Wrist Worn Inertial Sensors using k-means Clustering Classification
D. Biswas, A. Cranny, N. Gupta, K. Maharatna, J. Achner, J. Klemke, M. Jöbges, St. Ortmann
Human Movement Science 40, 59 (2015)
(StrokeBack)
In this paper we present a methodology for recognizing three fundamental movements of the human forearm (extension, flexion and rotation) using pattern recognition applied to the data from a single wrist-worn, inertial sensor. We propose that this technique could be used as a clinical tool to assess rehabilitation progress in neurodegenerative pathologies such as stroke or cerebral palsy by tracking the number of times a patient performs specific arm movements (e.g. prescribed exercises) with their paretic arm throughout the day. We demonstrate this with healthy subjects and stroke patients in a simple proof of concept study in which these arm movements are detected during an archetypal activity of daily-living (ADL) – ‘making-a-cup-of-tea’. Data is collected from a tri-axial accelerometer and a tri-axial gyroscope located proximal to the wrist. In a training phase, movements are initially performed in a controlled environment which are represented by a ranked set of 30 time-domain features. Using a sequential forward selection technique, for each set of feature combinations three clusters are formed using k-means clustering followed by 10 runs of 10-fold cross validation on the training data to determine the best feature combinations. For the testing phase, movements performed during the ADL are associated with each cluster label using a minimum distance classifier in a multi-dimensional feature space, comprised of the best ranked features, using Euclidean or Mahalanobis distance as the metric. Experiments were performed with four healthy subjects and four stroke survivors and our results show that the proposed methodology can detect the three movements performed during the ADL with an overall average accuracy of 88% using the accelerometer data and 83% using the gyroscope data across all healthy subjects and arm movement types. The average accuracy across all stroke survivors was 70% using accelerometer data and 66% using gyroscope data. We also use a Linear Discriminant Analysis (LDA) classifier and a Support Vector Machine (SVM) classifier in association with the same set of features to detect the three arm movements and compare the results to demonstrate the effectiveness of our proposed methodology.
(9) Bug-Tolerant Sensor Networks: Experiences from Real-World Applications
M. Brzozowski, P. Langendörfer
Proc. 7th International Conference on Ad Hoc Networks (2015), 1 (2015)
(SAID)
(10) Bug-Tolerant Sensor Networks: Experiences from Real-World Applications
M. Brzozowski, P. Langendörfer
Proc. 7th International Conference on Ad Hoc Networks (2015), 1 (2015)
(ATEM)
(11) Challenges for 100 Gbit/s End to End Communication: Increasing Throughput Through Parallel Processing
S. Buechner, J. Nolte, R. Kraemer, L. Lopacinski, R. Karnapke
Proc. of the 40th IEEE Conference on Local Computer Networks (LCN 2015) (2015)
(DFG-SPP1655)
Today's applications and services become more dependent on fast wireless communication, for the upcoming years data-rate demands of 100Gbit/s can be easily expected. However, fulfilling that demand is a task which cannot simply be solved by upscaling existing technologies. While most of the research tackles the challenges regarding the transmission technology from the physical layer up to base-band processing, we focus on the challenges concerning the handling of that vast amount of data. The overall goal is to bring together the transmission technology with the operating system to create a suitable end-to- end communication solution. In this paper we argue that communication can be understood as a soft-realtime problem and how that helps introducing parallelism into protocol-processing.
(12) Hardware Implementation of a RSS Localization Algorithm for Wireless Capsule Endoscopy
M. Cicic, J. Gutierrez Teran, Z. Stamenkovic
Proc. 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 301 (2015)
The paper presents an algorithm for localization of endoscopic capsules inside the human body. The goal is to determine the position of capsules by measuring the power of received electromagnetic signal on the human skin taking into account losses within the body. The algorithm was first developed and simulated in MATLAB. Simulation results prove its high accuracy and indicate the optimal antenna configuration. Then a C model was generated and modified to comply with standards of system-level modeling languages. Catapult C tool was used for system-level synthesis and generation of a RTL hardware model. Low power dissipation and small hardware area were achieved by ASIC implementation in a 130 nm bulk CMOS technology.
(13) An Analysis of OAM Modes for mm-Wave Wireless Communications
D. Cvetkovski, T. Hälsig, B. Lankl, E. Grass
Proc. URSI Atlantic Radio Science Conference (AT-RASC 2015), 1617 (2015)
(maximumMIMO)
(14) Clockwise Randomization of the Observable Behaviour of Crypto ASICs to Counter Side Channel Attacks
Z. Dyka, Ch. Wittke, P. Langendörfer
Proc. Euromicro Conference on Digital System Design (DSD-2015), 551 (2015)
(MaSCH)
Side channel attacks take advantage from the fact that the behavior of crypto implementations can be observed and provides hints that allow revealing keys. In this paper we present a novel approach to prevent SCA or at least to increase the effort to reveal keys significantly. Our approach is based on the fact that there are some functions used in cryptographic operations that can be implemented using different formulae or algorithms. These algorithms come with their individual complexity that results in individual circuits with individual power consumption. Thus, the observable behavior of each of these algorithms is different. So, if the crypto implementation uses these different algorithms whenever it is executed or if the sequence in which the different algorithms are used is randomized, extracting the key gets extremely challenging if not impossible. Applying our idea of is extremely challenging when it comes to ASIC implementation. The point here is that the functionality is fixed and cannot be altered after production. But we discuss that a runtime permutation of the relation between operands and algorithms used for their processing alters the observable behavior in the same way as executing different algorithms. In order to evaluate the effect of our approach we used a Xilinx Spartan 6 FPGA to implement two multipliers consisting of different partial multipliers and measured the corresponding power traces. These measurements show that attacks that compare the shape of power traces e.g. by subtracting them are no longer successful if our approach is applied.
(15) Individualizing Electrical Circuits of Cryptographic Devices as a Means to Hinder Tampering Attacks
Z. Dyka, T. Basmer, Ch. Wittke, P. Langendörfer
http://eprint.iacr.org/2015/442.pdf
(MaSCH)
(16) Bitwise Key Agreement using Wireless Channel Parameters (Work in Progress)
Z. Dyka, D. Kreiser, P. Langendörfer
Proc. 23rd Crypto-Day, 5 (2015)
(ParSec)
(17) SCREAMER – A Demonstrator Chip for Spectral Noise Optimization By Clock Latency Scheduling
X. Fan, O. Schrape, S. Zeidler, M, Krstic, M. Stegmann, I. Jensen, J. Thorsen, T. Bjerregaard
Proc. IEEE International System-on-Chip Conference (SOCC 2015), (2015)
(IC-NAO)
(18) A Ka/X-Band Digital Beamforming Synthetic Aperture Radar for Earth Observation
S. Gao, F. Qin, C. Mao, M. Younis, G. Krieger, S. Glisic, W. Debski, L. Boccia, G. Amendola, E. Arnieri, M. Krstic, P. Penkala, E. Celton
Proc. 7th International Conference on Recent Advances in Space Technologies - Emerging Private Space - (RAST 2015), (2015)
(Different)
(19) Dual-Band Digital Beamforming Synthetic Aperture Radar for Earth Observation
S. Gao, C. Mao, F. Qin, A. Patyuchenko, C. Tienda, M. Younis, G. Krieger, S. Glisic, W. Debski, L. Boccia, G. Amendola, E. Arnieri, M. Krstic, A. Koczor, P. Penkala, E. Celton
Proc. Asia Pacific Microwave Conference (APMC 2015), (2015)
(Different)
(20) Evaluation of a UWB Radar Interface for Low Power Radar Sensors
D. Genschow, J. Kloas
Proc. European Microwave Week (EuMW 2015), 1343 (2015)
This paper describes a novel energy efficient method of converting a number of subsequent UWB Radar pulses
from time domain to digital domain with picosecond resolution.
The system features multi target capability and only a fraction of the energy consumption of traditional Highspeed ADC or
counter-based solutions with much higher resolution.
The method addresses a key challenge of todays UWB radar systems. The power required to convert ultra short signals from time
domain to digital domain today renders UWB radars unattractive for battery powered systems like remote sensor networks. With the proposed system
it is possible to overcome this limitation.
(21) A Time to Digital Converter for use in Ultra Wide Band Radar Sensor Nodes
D. Genschow
Proc. IEEE Topical Conference on Wireless Sensors and Sensor Networks (WISNET 2015), 38 (2015)
This paper introduces a time to digital converter
(TDC) architecture for use with ultra wideband (UWB)
radar systems. The basic functionality is interfacing UWB
RF-Frontends to standard microcontrollers (C) without
the need of high-speed, high precision analog to digital
converters, high performance memories or large high speed
logic. The device achieves asynchronous conversion of multiple
successive events from time domain to digital domain
with picosecond resolution. Primary fields of application
include short range, low power UWB Radars like ground
penetrating Radars, LIDAR systems or other localization
tasks. Secondary fields are ultrasonic measurements and mid
range radars. A self-calibration feature is implemented to
correct certain nonlinearities and imperfections inherent to
the conversion method.
(22) Dynamically Reconfigurable Optical-Wireless Backhaul/Fronthaul with Cognitive Control Plane for Small Cells and Cloud-RANs
E. Grass, J. Gutierrez Teran, K. Grobe, A. Fehske, R. McConnell, M. Barrett, I. Mesogiti, E. Theodoropoulou, G. Lyberopoulos, D. Camps-Mur, J. Paradells-Aspas, N. Vucic, E. Schulz, J. Bartelt, G. Fettweis, I. Berberana, D. Markovic, D. Simic, V. Petrovic, M. Anastasopoulos, A. Tzanakaki, D. Simeonidou, M. Beach, A. Nix, D. Syrivelis, T. Korakis
Proc. 24th European Conference on Networks and Communications (EuCNC 2015), 687 (2015)
(5G-XHaul)
Small Cells, Cloud-Radio Access Networks (CRAN), Software Defined Networks (SDN) and Network Function Virtualization (NVF) are key enablers to address the demand for broadband connectivity with low cost and flexible implementations. Small Cells, in conjunction with C-RAN, SDN, NVF pose very stringent requirements on the transport network. Here flexible wireless solutions are required for dynamic backhaul and fronthaul architectures alongside very high capacity optical interconnects. However, so far there is no consensus on how both technologies can be most efficiently combined.
(23) Impact of Intercell and Intracell Variability on Forming and Switching Parameters in RRAM Arrays
A. Grossi, D. Walczyk, C. Zambelli, E. Miranda, P. Olivo, V. Stikanov, A. Feriani, J. Sune, G. Schoof, R. Kraemer, B. Tillack, A. Fox, T. Schroeder, Ch. Wenger, Ch. Walczyk
IEEE Transactions on Electron Devices 62(8), 2502 (2015)
DOI: 10.1109/TED.2015.2442412, (RRAM (Resistive RAM))
The intercell variability of the initial state and the impact of dc and pulse forming on intercell variability as well as on intracell variability in TiN/HfO2/Ti/TiN 1 transistor – 1 resistor (1T-1R) devices in 4-kb memory arrays were investigated. Nearly 78% of devices on particular arrays were dc formed with a wordline (WL) voltage VWL = 1.4 V and a bitline (BL) voltage VBL = 2.3 V, whereas 22% of devices were not formed due to the combined effect of the extrinsic process-induced intercell variability of the initial state and the intrinsic intercell variability after dc forming. Furthermore, pulse-induced forming with pulsewidths on the order of 10 μs (VWL = 1.4 V and VBL = 3.5 V) caused for 86% of devices a low-resistance state. Using a retry algorithm, we achieve 100% of formed devices. To assess and confirm the nature of the variability during forming operation and during cycling, the quantum point-contact model was considered. The modeling results demonstrate a relationship between the forming and the device performance. The cells requiring high energy for the forming operation, due to impurities in the HfO2 deposition.
(24) System Design Considerations for a PSSS Transceiver for 100 Gbps Wireless Communication with Emphasis on Mixed Signal Implementation
A.R. Javed, K. Krishnegowda, J.C. Scheytt, R. Kraemer
Proc. IEEE Wireless and Microwave Technology Conference (WAMICON 2015) (2015)
(Real100G.com)
(25) Erzeugung diagnostischer Testmuster unter komplexen Constraints
T. Koal, S. Eggersglüß, M. Schölzel
Proc. 27. GI/ITG - Workshop über Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2015), 12 (2015)
(DIAMANT)
In diesem Beitrag wird die Erzeugung diagnosti-scher Testmuster für den softwarebasierten Selbsttest mit zwei verschiedenen ATPG-Werkzeugen betrachtet und verglichen. Kritisch bei der Erzeugung der diagnostischen Testmuster sind die zahlreichen einzuhaltenden komplexen Constraints. Voran-gegangene Arbeiten haben gezeigt, dass diese bei der Verwen-dung klassischer ATPG-Tools zu sub-optimalen Ergebnissen bei gleichzeitig hohen Laufzeiten führen. Werden dagegen Testmus-ter mit einem SAT-basierten ATPG-Verfahren erzeugt, wie in diesem Beitrag vorgeschlagen, so können die Anzahl der Test-muster und die Laufzeit für deren Erzeugung deutlich reduziert werden. Es kann daraus geschlossen werden, dass die in kom-merziellen Werkzeugen eingesetzten Techniken zur Testmuster-erzeugung für stark Constraint-basierte Entwürfe weniger gut geeignet sind.
(26) Ultra-High Speed Wireless Communications: Challenges and Approaches
R. Kraemer
Proc. International Symposium on Signals, Systems and Electronics 2015 (ISSSE 2015), ext. abstr. 1239 (2015)
(27) Collision-Free Full-Duplex UWB Communication Based on the Standard IEEE.802.15.4a
D. Kreiser, S. Olonbayar
Proc. IEEE Wireless Communications and Networking Conference (WCNC 2015), 81 (2015)
(KUSZ)
Using UWB for wireless short range, low rate
communication is attracting growing interest due to its low power
consumption and very high bandwidth. Regarding these qualities,
it is comprehensible that there is an interest in the automation
industry to use ultra-wideband-based wireless sensor nodes to
replace wired systems, to save energy and to save costs without
reducing the reliability of the whole system. For this reason
optimizations of the standard IEEE.802.15.4a were investigated
in this paper with particular emphasis on latency, data rate,
energy efficiency, and reliability. This paper demonstrates the
optimization potential of the official standard
(28) Erweiterte Sicherheit für industrielle Anlagen
J. Krimmling, A. Sänn
chemie & more 1, (2015)
(29) Towards 100 Gbps Wireless Communication in THz Band with PSSS Modulation: A Promising Hardware in the Loop Experiment
K. KrishneGowda, T. Messinger, A.C. Wolf, R. Kraemer, I. Kallfass, J.C. Scheytt
Proc. IEEE International Conference on Ultra-Wideband (ICUWB) (2015)
(Real100G.com)
(30) Reducing Power Consumption in Fault Tolerant ASICs
M. Krstic
Proc. Workshop Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen (2015), 1381 (2015)
(31) Globally Asynchronous Locally Synchronous Design Methodology in ASICs for Wireless Communications
M. Krstic
Proc. 23rd Austrian Workshop on Microelectronics (Austrochip 2015) abstr. (2015)
(32) Design and Performance Measurements of an FPGA Accelerator for a 100 Gbps Wireless Data Link Layer
L. Lopacinski, M. Brzozowski, R. Kraemer, J. Nolte, S. Buechner
Proc. International Symposium on Signals, Systems and Electronics (ISSSE 2015), ext. abstr. 1118 (2015)
(DFG-SPP1655)
(33) Design and Implementation of an Adaptive Algorithm for Hybrid Automatic Repeat Request
L. Lopacinski, M. Brzozowski, R. Kraemer, J. Nolte, S. Buechner
Proc. 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 263 (2015)
(DFG-SPP1655)
(34) 100 Gbps Wireless – Data Link Layer VHDL Implementation
L. Lopacinski, J. Nolte, S. Buechner, M. Brzozowski, R. Kraemer
Proc. of the 18th Conference on Reconfigurable Ubiquitous Computing 2015, (2015)
(DFG-SPP1655)
In this paper, we describe implementation and hardware used for a wireless 100 Gbps data link layer demonstrator. So fast stream processing requires a highly parallelized approach. The timing requirements of the 100 Gbps networks are so demanding that there is no chance to deal with this task as a single stream in a field programmable gate array (FPGA). Due to this reason, we introduce and validate one of possible architectures that can solve the task. The 100 Gbps implementation is explained in details, and the most important parameters of the FPGA design are mentioned.
(35) A 100 Gbps Data Link Layer with a Frame Segmentation and Hybrid Automatic Repeat Request
L. Lopacinski, M. Brzozowski, R. Kraemer
Proc. Science and Information Conference (SAI), 1062 (2015)
(DFG-SPP1655)
(36) Parallel RS Error Correction Structures Dedicated for 100 Gbps Wireless Data Link Layer
L. Lopacinski, J. Nolte, S. Buechner, M. Brzozowski, R. Kraemer
Proc. IEEE International Conference on Ultra-Wideband (ICUWB 2015), (2015)
(DFG-SPP1655)
one of the most calculation intensive operations for a 100 Gbps wireless packet processing is a forward error correction (FEC). We are using standard field programmable gate arrays (FPGAs) to prepare a data link layer demonstrator. Therefore, we need to find a high-parallelized FEC structure for our device. The difficulty is to design the 100 Gbps FEC engine that can be realized in an FPGA. In one of previous papers, we have proposed a solution based on convolutional coding, but the engine consumed equivalent logic of 23 FPGAs [1]. That solution could not be implemented in nowadays FPGAs. In this paper, we propose parallel Reed-Solomon (RS) coders to reach the 100 Gbps throughput. The main task is to select the best candidates from available correction codes for the targeted 100 Gbps wireless communication and fit it to one or two high-end FPGAs. At the end, we demonstrate a system with two FPGAs, which is achieving continuous user data transfer rate of 97 Gbps and is negotiating the RS parameters according to the channel bit error rate
(37) A 100 Gbps Data Link Layer with an Adaptive Algorithm for Forward Error Correction
L. Lopacinski, M. Brzozowski, R. Kraemer
Proc. IEICE Information and Communication Technology Forum (IEICE ICTF), (2015)
(DFG-SPP1655)
(38) Energy Management using the Business Model Approach
B. Matusiak, K. Piotrowski, F. Melo
Proc. of 12th International Conference on the European Energy Market, (2015)
(e-balance)
This paper presents the results of the work on the Business Models (BM) for the e-balance project, which that aims to create an application for balancing local production and consumption of the energy in an intelligent and cost-effective environment, (e-balance 2013-2017; #609132) . The consumer’s needs were investigated and consumers’ profiles were definedbuilt. These profiles were determined by conducting social research in three countries on the needs of requirements for the e-balance application in three countries. The test results provide a good basis forof the first Business Model description for the proposed services, well fitted in with customers’ needs using the BM approach. In this paper the business model verification method for the e-balance project is shortly presented, and the first stage of the BM consideration and results are described.
(39) Internet of Things in e-Balance Project
B. Matusiak, K. Piotrowski, J. Zielinski
Proc. Zarzadzanie Energia i Teleinformatyka (ZET 2015), (2015)
(e-balance)
The aim of this paper is to consider the main principles of the Internet of Things (IoT) and Internet of Everything (IoE) within the context of building a Business Model (BM) and data flow limitations for the e-balance EU project. Authors have addressed the need of creation of a business model type, which will be dedicated to the concept of the Internet of Things. Initial results for the e-balance platform with technical and organizational architecture and BM have also been presented. This application is in the area of IoT and Smart Grid (SG). One of the key conclusions of this paper is a claim that in the near future, energy utilities should seriously rethink their BM and the possibility of designing new services in digitally intensive environments using smart appliances and sensors.
(40) Multi-Level 20 Gbit/s PSSS Transmission Using a Linearity-Limited 240 GHz Wireless Frontend
T. Messinger, K. KrishneGowda, F. Boes, D. Meier, A. Wolf, A. Tessmann, R. Kraemer, I. Kallfass
Proc. IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS 2015), (2015)
(Real100G.com)
(41) Concurrent Generation of Pseudo Random Numbers with LFSR of Fibonacci and Galois Type
E. Milovanovic, M. Stojcev, I. Milovanovic, T. Nikolic, Z. Stamenkovic
Computing and Informatics 34(4), 941 (2015)
We have considered implementation of parallel test pattern generator based on a linear feedback shift register (LFSR) with multiple outputs used as a building block in buili-in-self-test (BIST) design within SoC. The proposed design can drive several circuits under test (CUT)simultaneously. The mathematical procedure for concurrent pseudo random number (PRN) generation is described. We have implemented LFSRs that generate two and three PRNs in FPGA and ASIC technology. The design was tested at the operating frequency of 400 MHz.
Performance which relate to silicon area, dynamic power consumption and speed of operation were estimated. Synopsis Design Compiler and IHP's 130 nm CMOS ASIC design kit were used for synthesis, routing and mapping of LFSR design. Total silicon area of the LFSR with three parallel outputs and polynomial of degree 32, is 0.012mm2, and dynamic power consumption is less than 1.3 mW. Obtained results indicate that the area overhead and power consumption are small enough and proportional to the degree of feedback polynomial.
(42) Software-Based Self-Repair for Heterogenous Multi-Core Systems
S. Müller, H.T. Vierhaus, M. Schölzel
Proc. Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'15), 67 (2015)
(DIAMANT)
This paper describes a software-based technique for building heterogeneous fault tolerant multi-core systems, which are able to handle temporary and permanent hardware faults autonomously in two system layers. The fault tolerance technique relies on a single concept for adapting the binary code of the user application to the current fault state of a single core. Thereby this scheme is used either for a local repair of each core or for a glob-al repair. By the global repair, the task assigned to a faulty core may be rescheduled to another core that provides enough re-sources for the execution of the task. Thereby the local repair scheme is reused for the adaptation of the rescheduled task. It is shown that the reliability of a multi-core system can be improved significantly, when using the global repair together with the local repair instead of using the local repair only.
(43) A Multi-Layer Software-Based Fault-Tolerance Approach for Heterogenous Multi-Core Systems
S. Müller, T. Koal, S. Scharoba, H.T. Vierhaus, M. Schölzel
Proc. IEEE Latin American Test Symposium (LATS 2015), (2015)
(DIAMANT)
(44) Polarity Reception for IR-UWB in Wireless Fading Channel
S. Olonbayar, D. Kreiser, R. Kraemer, G. Fischer, D. Martynenko, O. Klymenko
Proc. European Wireless (EW2015), 283 (2015)
(KUSZ)
A digital baseband was designed and implemented according to the standard IEEE802.15.4a both in FPGA and as well as ASIC. The baseband supports data rates 850 Kb/s, 6.81 Mb/s and 27.24 Mb/s running at the clock speed of 31.2 MHz. The transmitter and receiver were tested by introducing various distortions to the signal being received. The baseband was shown to be fully functional being able to receive even under heavy distortion. Both the synchronization and data detection performance are robust. The baseband tested with a FPGA was further made as an ASIC in the 250 nm BiCMOS technology from IHP, Germany.
(45) Autonomous Execution of Reliable Sensor Network Applications on Varying Node Hardware
St. Ortmann, P. Langendörfer
Handbook of Research on Innovations in Systems and Software Engineering, IGI Global, 602 (2015)
(StrokeBack)
(46) Assessing the Success of Stroke Rehabilitation with Wearable Sensors
St. Ortmann, D. Biswas, A. Cranny, K. Maharatna, J. Achner, J. Klemke
Proc. Technically Assisted Rehabilitation (TAR 2015), (2015)
(StrokeBack)
(47) A Power-Gated Sensor Node Microcontroller for Security Applications
G. Panic, T. Basmer, O. Schrape
Proc. International Symposium on Signals, Systems and Electronics (ISSSE 2015), ext. abstr. 1576 (2015)
(48) Low Power Design Techniques
G. Panic
Proc. Informatik 2015, 1379 (2015)
(Telediagnostics)
The demand for portable electronic devices that offer greater functionality and performance at lower costs and smaller sizes has increased rapidly. This market trend is driving the need for efficient System-on-Chip (SoC) designs, where the power arises as the one of the biggest problems. The microprocessor design has traditionally focused on dynamic power (active power) consumption as the limiting factor in system integration. As technology has shrunk to 90 nm and below, static power (leakage power) is posing new challenges to low power design.
Historically, CMOS technology has dissipated much less power than earlier technologies such as transistor-transistor and emitter-coupled logic. In fact, when not switching, CMOS transistors consumed negligible power. However, with the increase in device speed and chip density, the power of CMOS increased dramatically. According to technology trends, the dynamic power per device decreases over the time. However, if it is assumed that the number of on-chip devices doubles every two years, total dynamic power increases on per-chip basis. Additionally, the shrinking of feature sizes makes static power dissipation grow exponentially. Consequently, the packaging and cooling costs as well as the limited power capacity of batteries become unsustainable.
The reduction of power growth below the predicted numbers has become one of the most important tasks for designers. To cope with the power challenges, a number of advanced power saving techniques have been developed that can efficiently target both static and dynamic power loss. The existing and future trends in low power design show that efficient power management is greatly determined by design decisions made in early phase of system design. Thus, the selection of power saving strategy becomes one of the most important challenges for designers.
This presentation starts by covering basic sources of power consumption in CMOS, including both static and dynamic power loss. Furthermore, the presentation gives a detailed overview on existing low power techniques including standard techniques developed for mature technologies, process-level techniques, and advanced low power techniques used in deep-submicron CMOS. Also, some attention is given to the selection of power saving strategy for design and early power estimation. Finally, future trends in low power design are discussed as well.
(49) Activity Profiling and Power Estimation for Embedded Wireless Sensor Node Design
G. Panic, Z. Stamenkovic
Proc. 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 231 (2015)
(50) Highly Integrated Dual-Band Digital Beamforming Synthetic Aperture Radar
A. Patyuchenko, M. Younis, G. Krieger, Z. Wang, S. Gao, F. Qin, C. Mao, S. Glisic, W. Debski, L. Boccia, G. Amendola, E. Arnieri, M. Krstic, E. Celton, P. Penkala
Proc. European Radar Conference (EuRAD), 1 (2015)
(Different)
(51) Innovative Methodology to Define Stakeholders’ Requirements for Smart Systems
J. Peralta, N. Jimenez, A. Casaca, F. Melo, K. Piotrowski
Proc. of the 23rd International Conference and Exhibition on Electricity Distribution (CIRED 2015), (2015)
(e-balance)
The presented methodology aims at facilitating the definition of stakeholders’ requirements for new system architectures. It is composed of 4 steps which allow identifying the links between stakeholders and/or systems and writing the necessary information. A preliminary step is necessary and focused on the conceptual map and template design. The former is a block diagram that includes all the stakeholders, management units and energy systems and their relations. The latter is a self-questionnaire to describe the requirements. This approach has allowed defining 204 requirements for the 28 use cases of the e-balance project by 10 researchers of different expertise areas without ambiguities. The requirement details have also allowed prioritizing the most relevant requirements with a statistical approach, what has allowed optimising the project planning. Finally, both the methodology and the first outputs and conclusions obtained of the requirement implementation in e-balance are explained.
(52) Implementation of Coherent IEEE 802.15.4 Receiver on Software Defined Radio Platform
U. Pesovic, D. Gliech, P. Planinsic, Z. Stamenkovic, S. Randjic
Proc. 23rd Telecommunications Forum (TELFOR 2015), 224 (2015)
Coherent receivers have better demodulation characteristics then non-coherent receivers when demodulating signals with higher bit error probability. They require synchronization with received signal using preamble which is transmitted at beginning of IEEE 802.15.4 packet. Software defined radio doesn’t allow adjustment of local oscillator frequency using Costas Loop circuitry, so synchronization need to be performed by software synchronization in baseband. This paper represents implementation of coherent IEEE 802.15.4 receiver on software defined radio.
(53) A Fast Link Initialization Protocol for Beam Steering based Cellular Backhaul Systems
M. Petri, M. Ehrig, M. Günther
Network Protocols and Algorithms 7(2), 113 (2015)
To deal with the enormous increase of mobile data traffic, new cellular network topologies are necessary. The reduction of cell area and the usage of light-weighted base stations serving only a handful of users, commonly known as the small cell approach, seems to be a suitable solution addressing changes in user expectations and usage scenarios. This paper is an extended version of [1], where current challenges of small cell deployments were presented from a backhaul perspective. A mesh-type backhaul network topology based on beam-steering millimeter-wave systems was proposed as a future-proof solution. In this paper, we focus on a link initialization protocol for beam steering with highly directive antennas. Special requirements and problems for link setup are analysed. Based on them, a fast protocol for link initialization is presented and it is evaluated in terms of the resulting initialization speed-up compared to state-of-the-art solutions. Furthermore, a potential approach for extending the fast link initialization protocol to support point-to-multipoint connections is given.
(54) Verbesserter TMR-Strahlungsschutz für ASIC-Layouts
V. Petrovic, G. Schoof, M. Krstic
Proc. 27. GI/ITG - Workshop über Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2015), 82 (2015)
(Different)
(55) Designflow for Radhard TMR Flip-Flops
V. Petrovic, M. Krstic
Proc. 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 203 (2015)
(Different)
Protection against radiation effects in digital ASICs chip can be reached using different design approaches. One of the popular approaches for increasing the reliability is the hardware triplication. However, the triplication of hardware doesn’t mean that the problems with radiation effects are automatically solved. The automatic random placement of standard cells can bring the higher power consumption as well as more occupied silicon area, with marginal improvement of the linear energy transfer threshold (LET) value. Additionally, the TMR approach usually requires changes in the of standard design ASIC flow, even requesting significant modifications of RTL code. In this paper, we will investigate the issues of design flow for TMR flip-flops, addressing both issues of compliance to the standard ASIC design methodology, enabling the use of non-modified RTL code, as well as layout generation of radhard TMR flip-flops, based on standard non-hardened flip-flop components.
(56) Bezpieczenstwo w Systemach Smart Grid na Przykladzie Projektu E-Balance
K. Piotrowski, J.J. Peralta Escalante
Zdalne Odczyty: Kryptologigia a Biznes - Bezpieczenstwo Stosowane, Wydawnictwo BTC, 87 (2015)
(e-balance)
(57) Bezpieczenstwo w Systemach Smart Grid na Przykladzie Projektu E-Balance
K. Piotrowski, J.J. Peralta Escalante
Proc. Konferencja Naukowo-Przemyslowa: Kryptologia a Biznes, Bezpieczenstwo Stosowane (KBBS), I.42015 (2015)
(e-balance)
(58) Neue Standards für WIFI - Um die Ecke gefunkt
J. Rähm, M. Kloiber, E. Grass
Deutschlandfunk – Computer und Kommunikation, (2015)
(Prelocate)
(59) Customer Integration and Voice-of-Customer Methods in the German Automotive Industry
A. Rese, A. Sänn, F. Homfeldt
International Journal of Automotive Technology and Management (IJATM) 15, 1 (2015)
(ESCI)
(60) Configurable Software Defined Radio System for two Way Time of Flight Ranging
V. Sark, E. Grass
Proc. International Symposium on Signals, Systems and Electronics 2015 (ISSSE 2015), ext. abstr. 1402 (2015)
(PROWILAN)
(61) PHY-Layer Limitations of Distance Measurements Using Round Trip Time of Flight (RTToF)
V. Sark, E. Grass
Proc. XII. International Conference on Electronics, Telecommunications, Automation and Informatics (ETAI), 11.1 (2015)
(Prelocate)
Many popular applications require precise ranging and localization. This is
mainly needed in indoor scenarios and urban area scenarios, i.e. where
GPS precision is poor or not available at all. Another, also popular,
requirement is the use of the same radio interface for data communication and
ranging.
In this paper, a general overview of the physical layer limitations are presented.
The Round Trip Time of Flight (RTToF) method for distance measurement (ranging) is
used. The first limitation addressed is the noise. Some proposed solutions were
tested and confirmed. The second limitation is the finite channel bandwidth. It
will distort the signal, so precise estimation of the distance is difficult.
The ranging (localization) system also introduces limitations due to the hardware used.
The finite sample rate of the A/D converter is a common system limitation. Interpolation is one good and standard solution.
Different interpolation methods were tested and some results are presented here.
Also, a solution for minimization of the clock inaccuracy error is proposed.
At last, the NLOS problem is addressed. One solution for detection of LOS/NLOS
scenario is proposed and preliminary simulation results are presented.
(62) An FPGA Debugging Tool for High Speed Multi-Channel Data Converter Add-on Boards
V. Sark, J. Gutierrez Teran, E. Grass
Proc. XII International Conference on Electronics, Telecommunications, Automation and Informatics (ETAI), 5.1. (2015)
(Prelocate)
Future wireless communication systems are constantly under pressure
for supplying more and more bandwidth. The next generation wireless
systems are expected to offer data rates of 100 Gbps. Also, precise
localization is getting more and more interest from the research community.
High speed data communication
and precise RF ranging require high speed data converters (A/D and D/A).
Testing and configuring these converters can be a painstaking process,
even if reconfigurable hardware, e.g. Field Programmable Gate Array (FPGA)
are available. The debugging tools supplied by the FPGA vendors, usually
the initial choice for this purpose, offer very poor performance. Setting up
and testing of many parameters takes an enormous amount of time when using these
tools. In this paper, a debugging tool for testing high speed data converters
is presented. The tool was developed in order to test 1 Gsps A/D and D/A converters
on an FPGA platform. The tool allows easy programming of common repetitive operations.
Thus, the time needed for deploying high speed data converters on an FPGA system
is extremely reduced. On the other hand, the tool allows automatic
configuration of some parameters, which is also presented in this paper.
(63) Multi-Way Ranging With Clock Offset Compensation
V. Sark, E. Grass, J. Gutierrez Teran
Proc. International Scientific Conference on Advances in Wireless and Optical Communications (RTUWO 2015), (2015)
(Prelocate)
This paper presents a new approach for reducing the ranging error due to the crystal clock offset. This approach is applicable in cooperative ranging methods like N-Way or Multi-Way ranging, which are mainly used in Wireless Sensor Networks (WSN). Leaving the crystal clock offset error uncompensated leads to propagation of the ranging error through the WSN. In our approach, the crystal clock offset between the nodes is estimated and used to compensate the ranging error.
The main advantage of our approach is the smaller number of transmissions compared to other crystal clock offset mitigation techniques. This reduces the energy consumption and minimizes the wireless medium usage for ranging purposes. The simulation results show that, even when a coarse estimation of the clock offset is performed, it has a significant impact on the reduction of the ranging error.
(64) Reduction of the Clock-Offset Induced Error in Multi-Way Ranging Scenarios
V. Sark, E. Grass, J. Gutierrez Teran
Proc. 1st International Scientific Conference on Advances in Wireless and Optical Communications 2015, RTU Press Riga, 158 (2015)
(Prelocate)
This paper presents a new approach for reducing the ranging error due to the crystal clock offset. This approach is applicable in cooperative ranging methods like N-Way or Multi-Way ranging, which are mainly used in Wireless Sensor Networks (WSN). Leaving the crystal clock offset error uncompensated leads to propagation of the ranging error through the WSN. In our approach, the crystal clock offset between the nodes is estimated and used to compensate the ranging error.
The main advantage of our approach is the smaller number of transmissions compared to other crystal clock offset mitigation techniques. This reduces the energy consumption and minimizes the wireless medium usage for ranging purposes. The simulation results show that, even when a coarse estimation of the clock offset is performed, it has a significant impact on the reduction of the ranging error.
(65) On Implementation of TPMS receiver for Traffic Data Collection
N. Savic, M. Krstic
Proc. International Symposium on Signals, Systems and Electronics (ISSSE 2015), ext. abstr. 1363 (2015)
(66) On the Feasibility of Handling Manufacturing Faults in Embedded Memories by Software Means
M. Schölzel, P. Skoncej, F. Vater
Proc. IEEE International Workshop of Electronics, Control, Measurement, Signals and their application to Mechatronics, 161 (2015)
(MOTARO)
(67) On the Feasibility of Handling Manufacturing Faults in Embedded Memories by Software Means
M. Schölzel, P. Skoncej, F. Vater
Proc. IEEE International Workshop of Electronics, Control, Measurement, Signals and their application to Mechatronics, 161 (2015)
(DIAMANT)
(68) Software-based Repair for Memories in Tiny Embedded Systems
M. Schölzel, P. Skoncej, F. Vater
Proc. European Test Symposium (ETS), (2015)
(MOTARO)
This paper presents a software-based technique for handling permanent faults in low-cost memories for embedded systems. Basically the technique is based on an adaptation of the program code that avoids the usage of faulty memory words. With this technique it is possible to handle permanent manufacturing faults as well as permanent aging faults in simple and cheap memories without any kind of hardware-based fault management in the memory. This is of particular interest for long living low-cost embedded systems like sensor nodes that make use of such memories. Different methods for handling memory faults in data and program memory are discussed. The methods for program memories are evaluated with flash memory devices. Based on real test data for the flash memories it is shown that with the software-based technique a significant amount of hardware-overhead in the memory can be avoided without losing the capabilities of handling memory faults.
(69) Software-based Repair for Memories in Tiny Embedded Systems
M. Schölzel, P. Skoncej, F. Vater
Proc. European Test Symposium (ETS), (2015)
(DIAMANT)
This paper presents a software-based technique for handling permanent faults in low-cost memories for embedded systems. Basically the technique is based on an adaptation of the program code that avoids the usage of faulty memory words. With this technique it is possible to handle permanent manufacturing faults as well as permanent aging faults in simple and cheap memories without any kind of hardware-based fault management in the memory. This is of particular interest for long living low-cost embedded systems like sensor nodes that make use of such memories. Different methods for handling memory faults in data and program memory are discussed. The methods for program memories are evaluated with flash memory devices. Based on real test data for the flash memories it is shown that with the software-based technique a significant amount of hardware-overhead in the memory can be avoided without losing the capabilities of handling memory faults.
(70) Integrated Circuit Failure Mechanisms and the Impacts of Technology Downscaling
A. Simevski
Proc. International Conference on Electronics, Telecommunications, Automation and Informatics (ETAI 2015), 5.5 (2015)
Integrated circuit reliability is of primary impor-
tance for applications in space, aviation, car safety, medical
equipment, etc. This paper presents an overview of the reliability
failure mechanisms of integrated circuits that lead to transient
and permanent faults. If special care is not taken, these faults
may further introduce errors and system failures. A classification of faults and failure mechanisms is given, followed by a comprehensive description of the most significant failure mechanisms, i.e., aging (wear out) and single event effects. The impact of integrated circuit technology downscaling on these effects is also revisited. CMOS technology, as the most popular one, is in the main focus.
(71) Softwarebasierte Selbstreparatur von Flash-Speichern für fehlertolerante mikrocontroller-basierte Systeme
P. Skoncej, F. Mühlbauer, M. Schölzel
Proc. Workshop für Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen, Informatik, 1461 (2015)
(DIAMANT)
(72) Softwarebasierte Selbstreparatur von Flash-Speichern für fehlertolerante mikrocontroller-basierte Systeme
P. Skoncej, F. Mühlbauer, M. Schölzel
Proc. Workshop für Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen, Informatik, 1461 (2015)
(MOTARO)
(73) Projekt Smartie: Bezpieczenstwo, Prywatnosc i Poufnosc w Zarzadzaniu Danymi w Inteligentych Miastach
A. Sojka-Piotrowska
Zdalne Odczyty: Kryptologia a Biznes - Bezpieczentswo Stosowane, Wydawnictwo BTC, 99 (2015)
(SMARTIE)
The growing popularity of using the Internet of Things in large-scale, mission-critical environments, e.g. cities, causes the need for investigation of new techniques ensuring the security and trust for data exchange between Internet of Things devices and the data owners or consumers. The main objective of SMARTIE project is to create a distributed framework for smart city applications sharing large volumes of heterogeneous data. The purpose of this framework is the provision of end-to-end security and trust in information delivery for decision-making purposes taking the data owners’ privacy into consideration. The feasibility and utility of SMARTIE approach will be tested in real environments (Traffic, Transport and Energy) with real users of the city infrastructures. The cities involved are Novi Sad (Serbia), Murcia (Spain) and Frankfurt an der Oder (Germany). This paper presents the security approach developed within the SMARTIE project.
(74) Projekt Smartie: Bezpieczenstwo, Prywatnosc i Poufnosc w Zarzadzaniu Danymi w Inteligentych Miastach
A. Sojka-Piotrowska
Proc. II Konferencja Naukowo-Przemyslowa: Kryptologia a Biznes, Bezpiechenstwo Stosowane (KBBS 2015), (2015)
(SMARTIE)
The growing popularity of using the Internet of Things in large-scale, mission-critical environments, e.g. cities, causes the need for investigation of new techniques ensuring the security and trust for data exchange between Internet of Things devices and the data owners or consumers. The main objective of SMARTIE project is to create a distributed framework for smart city applications sharing large volumes of heterogeneous data. The purpose of this framework is the provision of end-to-end security and trust in information delivery for decision-making purposes taking the data owners’ privacy into consideration. The feasibility and utility of SMARTIE approach will be tested in real environments (Traffic, Transport and Energy) with real users of the city infrastructures. The cities involved are Novi Sad (Serbia), Murcia (Spain) and Frankfurt an der Oder (Germany). This paper presents the security approach developed within the SMARTIE project.
(75) A Secure Isolation of Software Activities in Tiny Scale Systems
O. Stecklina
Proc. Ph.D. Forum on Pervasive Computing and Communications (PerComm), 245 (2015)
(UNIKOPS)
All visions of pervasive computing share the idea of smart,
small, and cheap devices that improve our everyday life. But
devices like smart sensor or deeply embedded controllers as
fundamental part of cyber-physical systems (CPSs) are also
able to do many things that we do not want. In fact, they will
be always vulnerable to doing the bidding of attackers, to the
detriment of their owners. This work presents a concept for a
security architecture for tiny scale systems (TSSs) with their
limited resources. The concept is based on well-understood
technologies of desktop systems, which are tailor-made for
TSSs in a compile- and run-time co-design process.
(76) Intrinsic Code Attestation by Instruction Chaining for Embedded Devices
O. Stecklina, P. Langendörfer, F. Vater, T. Kranz, G. Leander
Proc. 11th EAI International Conference on Security and Privacy in Communication Networks, (2015)
(UNIKOPS)
In this paper we present a novel approach to ensure that
no malicious code can be executed on resource constraint devices such
as sensor nodes or embedded devices. The core idea is to encrypt the
code and to decrypt it after reading it from the memory. Thus, if the
code is not encrypted with the correct key it cannot be executed due
the incorrect result of the decryption operation. A side effect of this is
that the code is protected from being copied. In addition we propose to
bind instructions to their predecessors by cryptographic approaches. This
helps us to prevent attacks that reorder authorized code such as return-oriented programming attacks. We present a thorough security analysis
of our approach as well as simulation results that prove the feasibility
of our approach. The performance penalty as well as the area penalty
depend mainly on the cipher algorithm used. The former can be as small
as a single clock cycle if Prince a latency optimized block cipher is used,
while the area overhead is 45 per cent for a commodity micro controller
unit (MCU).
(77) A Novel Compact Dual-Band Bandpass Waveguide Filter
S. Stefanovski, M. Potrebic, D. Tosic, Z. Stamenkovic
Proc. 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 51 (2015)
A novel design of second-order dual-band H-plane bandpass waveguide filter is presented in this paper. Filter design is relatively simple and is based on the use of complementary split ring resonators, implemented as metal septa, with properly shaped slots, in the transverse planes of the standard (WR-90) rectangular waveguide. The positions of the resonators on the same septum are chosen in such a manner that there is no mutual coupling between them. This approach is used for the design of the waveguide resonator with two resonant frequencies (9 GHz and 11 GHz). Further, the second-order dual-band bandpass waveguide filter, with symmetrically positioned folded septa, is presented. The equivalent circuits of the considered resonators and filters are developed. The proposed dual-band bandpass filter design is verified by a good agreement of the filter responses obtained for three-dimensional electromagnetic models and equivalent microwave circuits. Finally, the method for filter miniaturization is introduced and applied to the second-order dual-band filter. The required filter response is preserved.
(78) Autonomous Sensor Capsule for Usage in Bioreactors
N. Todtenberg, S.-T. Schmitz-Hertzberg, J. Klatt, F. Jorde, B. Jüttner, K. Schmalz, R. Kraemer
IEEE Sensors Journal 15(7), 4093 (2015)
(Telediagnostics)
An autonomous biochemical sensor capsule for the remote monitoring of an algae culture cultivated in a photobioreactor is presented. The encapsulated system has a spherical shape with a diameter of 44 mm. Radio communication with a carrier frequency of 433 MHz is used to transfer the acquired sensor data in the bioreactor to a base station outside. Experiments with the first prototype inside the bioreactor filled with nutrient solution were performed to determine the reliability of the communication link. The Packet Error Rate (PER) converged to 26 % and the path loss on average was 96 dB. The functionality of the signal processing chain of acquired biochemical sensor values was evaluated using an experimental setup: Our second capsule prototype with potentiometric sensors demonstrates the pH-measurements of different buffer solutions trickled on the sensor electrodes with a pipette.
(79) Securing the Internet of Things - Security and Privacy in a Hyperconnected World
E.Z. Tragos, H.C. Pöhls, R. Staudemeyer, D. Slamanig, A. Kapovits, S. Suppan, A. Fragkiadakis, G. Baldini, R. Neisse, P. Langendörfer, Z. Dyka, Ch. Wittke
Building the Hyperconnected Society - Internet of Things Research and Innovation - Value Chains, Ecosystem and Markets
(80) Multiple Fault Testing in Systems-on-Chip with High-Level Decision Diagrams
R. Ubar, M. Schölzel, S.A. Oyeniran, H.T. Vierhaus
Proc. IEEE International Design & Test Symposium (IDT), 66 (2015)
(DIAMANT)
(81) Compiler-Centered Microprocessor Design (CoMet) - From C-Code to a VHDL MOdel of an ASIP
R. Urban, M. Schölzel, H.T. Vierhaus, E. Altmann, H. Selig
Proc. 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 17 (2015)
(82) Möglichkeiten der Nutzung von RRAM in Low-Power Microcontrollern
F. Vater, G. Panic, S. Schölzel
Proc. Workshop Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen (Informatik 2015), INFORMATIK 2015, Lecture Notes in Informatics (LNI), Gesellschaft für Informatik, 1475 (2015)
(DIAMANT)
Die Energieeffizienz aktueller Microcontroller wird durch die aggressive Nutzung von verschiedenen Ruhe- und Schlafmodi erreicht. Eine vollständige Abschaltung des Microcontrollers ist dabei aufwendig, da die Zustände in flüchtigen Speichern nicht beibehalten werden. Nichtflüchtige Speicher bieten die Möglichkeit auf einfach Weise die Daten zwischenzuspeichern. In diesem Paper werden die verschiedenen Speichertechnologien in Hinblick auf ihre Energieeffizenz unter Berücksichtigung von Schreib-/Lesegeschwindigkeit sowie Lebensdauer untersucht. Dabei findet eine sehr genaue und technologienahe Simulation auf Basis von Transistormodellen statt.
(83) Neue Methodik zur Implementierung fehlertoleranter pipeline-basierter Architekturen
S. Weidling, M. Krstic
Proc. 27. GI/ITG - Workshop über Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2015), 86 (2015)
(84) Influence of Electrical Circuits of ECC Designs on Shape of Electromagnetic Traces Measured on FPGA
Ch. Wittke, Z. Dyka, P. Langendörfer
über: http://eprint.iacr.org/
(MaSCH)
Side channel attacks take advantage from the fact that the behavior of crypto implementations can be observed and provides hints that simplify revealing keys. The energy consumption of the chip that performs a cryptographic operation depends on its inputs, on the used cryptographic key and on the circuit that realizes the cryptographic algorithm. An attacker can experiment with different inputs and key candidates: he studies the influence of these parameters on the shape of measured traces with the goal to extract the key. The main assumption is here that the circuit of the attacked devices is constant. In this paper we investigated the influence of variable circuits on the shape of electromagnetic traces. We changed only a part of the cryptographic designs i.e. the partial multiplier of our ECC designs. This part calculates always the same function in a single clock cycle. The rest of the design was kept unchanged. So, we obtained designs with significantly different circuits: in our experiments the number of used FPGAs LUTs differs up to 15%. These differences in the circuits caused a big difference in the shape of electromagnetic traces even when the same data and the same key are processed. Our experiments show that the influence of different circuits on the shape of traces is comparable with the influence of different inputs. We assume that this fact can be used as a protection means against side channel attacks, especially if the cryptographic circuit can be changed before the cryptographic operation is executed or dynamically, i.e. while the cryptographic operation is processed.
(85) A Survey about Testing Asynchronous Circuits
St. Zeidler, M. Krstic
Proc. 22nd European Conference on Circuit Theory and Design (ECCTD 2015), (2015)
(Design for Testability)
Even though the asynchronous design methodology is considered to be a promising solution to upcoming challenges of designing complex integrated circuits (ICs), it is not widely accepted by the industry. Besides the lack of mature design tools, a further key inhibitor of using this design style is the widespread assumption that asynchronous circuits are difficult to test due to problems with system timing during test, nondeterminism, and difficulties with applying standard test approaches such as scan. However, there is a huge variety of approaches to handle these testing issues. This paper summarizes the different available test methodologies for asynchronous and globally-asynchronous locally-synchronous (GALS) designs and addresses their strengths and weaknesses. Moreover, it gives an overview of a methodology for testing based on the use of specific test processor, developed by IHP.
(86) A Design Preconditioning Flow for Low-Noise Circuits
St. Zeidler, X. Fan, O. Schrape, M. Krstic
Proc. 18th IEEE International Symposium Design and Diagnostics of Electronic Circuits and Systems (DDECS 2015), 191 (2015)
(IC-NAO)
Mitigating switching noise in highly complex integrated circuits (ICs) is one of the challenging issues in current design flows. The common way to optimize the noise characteristics is to apply current shaping techniques, which introduce clock skew to distribute the switching activity of the circuit. However, this is typically done at late backend design stages, i.e., in layout after cell placement, which limits the maximum clock phase insertion between the domains. Therefore, we propose a novel preconditioning flow, which considers noise optimization up frontend design, \ie, design coding stage. By this, RTL-level techniques, such as clock inversion, can be applied to further optimize the noise characteristics, while common current shaping strategies can still be applied in the backend design.
