Script list Publications
(1) Discussing the Initialization of the Montgomery kP-Algorithm in the Light of SCA
E. Alpirez Bock, Z. Dyka, P. Langendörfer
Proc. 24th Crypto-Day, (2016)
(myAirCoach)
Side channel analysis (SCA) attacks have been a popular research topic in the last years. Parameters
like power consumption, electromagnetic radiation and execution time of a cryptographic imple-
mentation can be analysed for identifying implementation details and based on this, extracting the
private key. The Montgomery kP-algorithm using Lopez-Dahab projective coordinates [LD99] is
an efficient method for performing the scalar multiplication in elliptic curve crypto-systems (ECC).
This algorithm is a bitwise processing of the scalar k, which is the private key used for performing
decryption in ECC. It is considered resistant against simple power analysis (SPA) since each key
bit is processed by the same type, amount and sequence of operations, independently of the key
bit's value. Nevertheless, its initialization phase affects this algorithm's robustness against SCA.
We describe how the first iteration of the kP processing loop reveals information about the key bit being processed, i.e. bit kl-2. Using simulated power traces, we demonstrate that the power profile of the processing of kl-2 differs from the power profiles of the processing of all other key bits. Moreover, we demonstrate that this power profile differs significantly for the cases kl-2 = 1 and kl-2 = 0. This leads to an easy extraction of bit kl-2 using SPA and exposes details of the implementation of the algorithm. This can be useful for the preparation of further attacks. As a countermeasure against this vulnerability, we propose a modification of the algorithm's initialization phase and of the processing of bit kl-2. We show that with this modification, the power profiles of the processings of kl-2 = 1 and kl-2 = 0 look similar to each other and similar to the processing of all remaining bits of the key, i.e. the value of the key bit kl-2 cannot be extracted using SPA. Our proposed modifications increase the algorithm's robustness against SCA and even reduce the time needed for the initialization phase and for processing kl-2. Compared to the original design, our new implementation needs only 0.12% additional area, while its energy consumption is almost the same, remaining by 2.09 J. Thus, we achieved to increase the security of our implementation without any additional costs.
(2) Efficient and Power Analysis Resistant Implementation of the Montgomery kP-Algorithm
E. Alpirez Bock, Z. Dyka, P. Langendörfer
Proc. 23rd Crypto-Day, 17 (2016)
(MaSCH)
(3) Increasing the Robustness of the Montgomery kP-Algorithm against SCA by Modifying its Initialization
E. Alpirez Bock, Z. Dyka, P. Langendörfer
Proc. International Conference on Information Technology and Communications Security, (2016)
DOI: 10.1007/978-3-319-47238-6_12, (myAirCoach)
The Montgomery kP-algorithm using Lopez-Dahab projec-
tive coordinates is a well-known method for performing the scalar multi-
plication in elliptic curve crypto-systems (ECC). It is considered resistant
against simple power analysis (SPA) since each key bit is processed by the
same type, amount and sequence of operations, independently of the key
bit's value. Nevertheless, its initialization phase a ects this algorithm's
robustness against side channel analysis (SCA) attacks. We describe how
the rst iteration of the kP processing loop reveals information about the
key bit being processed, i.e. bit kl-2. We explain how the value of this bit
can be extracted with SPA and how the power pro le of its processing can
reveal details about the implementation of the algorithm. We propose a
modi cation of the algorithm's initialization phase and of the processing
of bit kl-2, in order to hinder the extraction of its value using SPA. Our
proposed modi cations increase the algorithm's robustness against SCA
and even reduce the time needed for the initialization phase and for pro-
cessing kl-2. Compared to the original design, our new implementation
needs only 0.12% additional area, while its energy consumption is almost
the same, i.e. we improved the security of the design at no cost.
(4) SET Response of a SEL Protection Switch for 130 nm and 250 nm CMOS Technologies
M. Andjelkovic, A. Ilic, V. Petrovic, M. Nenadovic, Z. Stamenkovic, G. Ristic
Proc. IEEE International On-Line Testing Symposium (IOLTS 2016), 185 (2016)
This paper analyzes the single event transient (SET) response of a single event latchup (SEL) protection switch (SPS cell) designed in the 130 and 250 nm bulk CMOS technologies. The analysis has been conducted through the SPICE simulations, using the standard double exponential current source as the SET model. It has been confirmed that the 130 nm SPS cell is more susceptible to SETs than the 250 nm version, i.e. the 130 nm SPS cell has exhibited significantly lower critical charge. Based on the simulation results, an analytical model for estimating the critical charge in terms of the transistor size, load capacitance, supply voltage and duration of the SET current pulse, has been derived. Using the proposed critical charge model simplifies the analysis of the SPS cell’s susceptibility to SETs for custom designs.
(5) Performance Investigation on BCH Codec Implementations
D. Azinovic, K. Tittelbach-Helmrich, Z. Stamenkovic
Proc. 16th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2016), (2016)
(ParSec)
This paper investigates the performance of the BCH encoder and decoder for different error-correcting capabilities. The focus is on BCH codes of length 255. The motivation for this research is a project where data symbols of this length are transmitted over an error-prone wireless channel. The paper presents a mathematical introduction into encoding for cyclic codes and decoding of the BCH code. The code was implemented in both software and hardware and the performance and cost of both implementations were measured for different code parameters.
(6) GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits
M. Babic, St. Zeidler, M. Krstic
Proc. 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 67 (2016)
(GASEBO)
This paper proposes a methodology for substrate noise reduction in mixed-signal integrated circuits (IC) by using a globally-asynchronous locally-synchronous (GALS) approach for digital system integration. For this purpose the harmonic balanced partitioning strategy has been proposed. It has been shown that by converting a synchronous design into a plesiochronous GALS design with M locally-synchronous modules (LSMs), a theoretical limit of spectral peak attenuation corresponds to 20logM. This model has been evaluated by numerical simulations in MATLAB. Based on the proposed partitioning scheme, a methodology for GALS partitioning for optimal substrate noise reduction has been developed. Finally the corresponding low-noise GALS design flow has been proposed, based on a custom noise optimization tool named EMIAS. The flow has been evaluated on a realistic design example.
(7) 5G-XHaul: Enabling Scalable Virtualization for Future 5G Transport Networks
D. Camps-Mur, P. Flegkas, D. Syrivelis, Q. Wei, J. Gutierrez Teran
Proc. 15th International Conference on Ubiquitous Computing and Communications (IUCC 2016), 137 (2016)
DOI: 10.1109/IUCC-CSS.2016.032, (5G-XHaul)
(8) Un Middleware Centrado en Datos para el Control en Tiempo Real de Redes de Energia Inteligentes
J. Chen, E. Canete, M. Diaz, D. Garrido, K. Piotrowski
Proc. V Congreso espanol de Informatica (CEDI 2016), 19 (2016)
(e-balance)
(9) User's Requirements and Privacy Concerns as Canvas of Business Models and Active Demand Management within e-Balance System
W. Ciemniewski, M. Geers, B.E. Matusiak, K. Piotrowski
Proc. 13th International Conference on the European Energy Market (EEM 2016), 1 (2016)
(e-balance)
This paper presents an in depth analysis of the research regarding users requirements and system functionalities, business models and privacy issues as well as data security aspects in the energy balancing system. It is crucial for the system, that it has to be reliable and respond to users’ expectations. The system/platform itself is a result of European (FP7) collaborative project e-balance: Balancing the energy production and consumption in energy efficient smart neighbourhoods.
(10) Radiation-Hardened SiGe BiCMOS Technologies for Analogue and Mixed-Signal ICs
M. Cirillo, F. Teply, G. Fischer, R. Sorge, J. Schmidt, M. Krstic, V. Petrovic
Proc. 6th International Workshop on Analogue and Mixed Signal Integrated Circuits for Space Applications (AMICSA 2016), 48 (2016)
Introduction :
IHP is actively involved since many years in developing and providing un-restricted access to their high-performance 250nm and 130nm SiGe BiCMOS Technologies and Services.
In response to the strategic European non-dependence process for critical Space Technologies like EEE components, aiming to ensuring European free, un-restricted acces to any required space technology supply chain, IHP has been involved in the development of RadHard SiGe Process Design Kits (PDKs) for their SiGe BiCMOS technologies. For the 250nm node, a RadHard PDK SGB25RH has been developed and evaluated in accordance to the ESCC 2269010 Basic Specification “Evaluation Test Programme for MMICs” and will be filing for EPPL Listing in 2016 while for the 130nm Technology node, PDK SG13RH is under development and sensitivity to radiation (TID, DD, SEEs) is being evaluated before going through the full ESCC 2269010 Evaluation Test Programme (2017-2019) and release the SG13RH technology for EPPL Listing within 2020.
Content :
The integration of Silicon-Germanium (SiGe) onto BiCMOS technology platforms have been proven an economically viable and valuable technology for the design and implementation of low power highly integrated microwave monolithic integrated circuits (MMICs) operating at very high frequencies together with complex CMOS functions unavailable in other technologies. SiGe HBTs exhibit intrinsic advantages – such as a very high tolerance to Total Ionizing Dose (TID) greater than 1 Mrad(Si) and improved performances down to cryogenic temperatures – which make them excellent candidates for space-based applications which any independent ASIC/MMIC Design House can use to develop electronic components for the space market.
The presentation will focus on presenting the 250nm and 130nm IHP SiGe BiCMOS Processes, the contents of the RadHard PDKs (devices and libraries), the definition of the Capability Domain, status and results of the Evaluation Tests in accordance with ESCC-2269010 on the various Test Vehicles (TCV, DECs and RIC) . More recent results concerning radiation tests and reliability evaluations on both CMOS and SiGe HBT devices will be presented focusing on the failure modes of such devices and the required derating factors necessary to achieve reliability and mission lifetimes.
Conclusion :
The presentation will conclude with the description of IHP's access policy to the Rad Hard Design Kits and supported services (i.e. Lot Acceptance Tests – LATs defined in Process Identification Document – PID) from IHP and partners like Arquimea GmBH as well as the currently on-going activities and technology (such as Rad Hard LDMOS and Junction Isolated Cascode –JIC- CMOS) and library IP developments and enhancements foreseen for inclusion in future updates of the PDKs.
In addition a short overview of the current on-going R&D technology developments undertaken by IHP on their available commercial processes and IHP’s vision to the “More-than-Moore” approach like integration of THz Devices, Embedded RF-MEMS, Heterogeneous Integration (Micro-Fluidics, Through Silicon Vias, III-V on Si BiCMOS), Resistive-RAMs and Silicon Photonics which could prove useful for future compact low weight electronic components and System-on-Chip solutions for future Space or Ground-segment applications.
(11) Next Generation mm-Wave Wireless Backhaul Based on LOS MIMO Links
D. Cvetkovski, T. Haelsig, B. Lankl, E. Grass
Proc. German Microwave Conference (GeMiC 2016), 69 (2016)
(maximumMIMO)
With the evolution of the mobile networks towards more dense and flexible configurations, novel wireless backhaul solutions that can match the high capacity and flexibility demands are required in addition to the fixed fiber optics solutions. In this work we analyze the core backhaul requirements and the related system design challenges for utilizing the mm-wave frequency
band due to the large available bandwidth.
We determine the key performance metrics in terms of achievable throughput and energy efficiency of several transmission schemes seeking for a viable solution for the small cell backhaul scenario. Finally, an insight to the structure of the baseband domain required for processing multiple transmitted streams at the full system bandwidth is presented for a proposed LOS SM-MIMO system concept.
(12) Successful Simple Power Analysis of GALS ECC Design
Z. Dyka, F. Vater, D. Kreiser, P. Langendörfer
Proc. 23rd Crypto-Day, 5 (2016)
(Achilles)
(13) Revisiting Random Permutation of Calculation Steps of a Field Multiplication as a DPA Countermeasure
Z. Dyka, E. Alpirez Bock, I. Kabin, P. Langendörfer
Proc. 25th Crypto-Day, (2016)
(ECC)
(14) Inherent Resistance of Efficient ECC Designs Against SCA Attacks
Z. Dyka, E. Alpirez Bock, I. Kabin, P. Langendörfer
Proc. IFIP International Conference on New Technologies, Mobility and Security (NTMS 2016), (2016)
(MaSCH)
(15) Project FAST - Fast Actuators Sensors & Transceivers
F. Ellinger, T. Meister, P. Grosa, K. Jamshidi, D. Ihle, N. Franchi, J. Wagner, A. Richter, G. Fettweis, F. Fitzek, M. Kreissig, H. Klessig, E. Jorswiek, R. Kraemer, St. Ortmann, M. Schölzel, F. Gerfers, K. Richter, N. Elkmann, A. Frotzscher, H. Eisenreich, R. Löhr, W. Winkler, D. Zoeke, D. John, U. Fischer-Hirchert, A. Carôt, A. Bluschke, A. Richter
Proc. IEEE MTT-S Latin America Microwave Conference (LAMC 2016), (2016)
(16) Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling
X. Fan, M. Stegmann, O. Schrape, St. Zeidler, I. Jensen, J. Thorsen, T. Bjerregaard, M. Krstic
IEEE Transactions on Circuits and Systems I 63(7), 982 (2016)
(IC-NAO)
The simultaneous switching activity in digital circuits
challenges the design of mixed-signal SoCs. Rather than focusing
on time-domain noise voltage minimization, this work optimizes
switching noise in the frequency domain. A two-tier solution based
on the on-chip clock scheduling is proposed. First, to cope with the
switching noise at the fundamental clock frequency, which usually
dominates in terms of noise power, a two-phase clocking scheme
is employed for system timing. Second, on-chip clock latencies are
manipulated to target harmonic peaks in specific frequency bands
for the spectral noise optimization. An automated design flow,
which allows for noise optimization in user-defined applicationspecific
frequency bands, is developed. The effectiveness of our design
solution is validated by measurements of substrate noise and
conductive EMI (electromagnetic interference) noise on a test chip,
which consists of four wireless sensor node baseband processors
each addressing a distinct clock-tree-synthesis strategy. Compared
to the reference synchronous design, the proposed clock scheduling
solution substantially reduces noise in the target GSM-850 band,
i.e., by 11.1 dB on the substrate noise and 12.9 dB on the EMI noise,
along with dramatic noise peak drops measured at the 50-MHz
clock frequency.
(17) Cross-Plattform zur Hardware- und Betriebssystemunabhängigen Implementierung von Anwendungen und Protokollen
M. Frohberg, P. Poppe, N. Vetter, S. Reinhold, M. Schölzel
Proc. GI/ITG KuVS Fachgespräch Sensornetze (FGSN 2016), 47 (2016)
(DIAMANT)
In diesem Beitrag wird eine Cross-Plattform be-schrieben, die eine hardware- und betriebssystemunabhängige Implementierung von Protokollen und Anwendungen für Sen-sorknoten erlaubt. Dadurch soll in Umgebungen in denen viele heterogene Hardwareplattformen eingesetzt werden, die Wiederverwendbarkeit von Code bei der Entwicklung von Software selbst dann gewährleistet sein, wenn unterschiedliche Betriebssysteme auf verschiedenen Hardwareplattformen unterstützt werden müssen. Durch eine Integration von Instrumentalisierungsfunktionen in die Cross-Plattform kann diese zusätzlich das Testen und Überwachen verschiedener Abläufe im realen System plattformunabhängig unterstützen, und somit zur Produktivitätssteigerung in heterogenen Umgebungen beitragen.
(18) The IoT Architectural Framework, Design Issues and Application Domains
G. Gardasevic, M. Veletic, N. Maletic, D. Vasiljevic, I. Radusinovic, S. Tomovic, M. Radonjic
Wireless Personal Communications 92(1), 127 (2016)
The challenge raised by the introduction of Internet of Things (IoT) concept will permanently shape the networking and communications landscape and will therefore have a significant social impact. The ongoing IoT research activities are directed towards the definition and design of open architectures and standards, but there are still many issues requiring a global consensus before the final deployment. The paper presents and discusses the IoT architectural frameworks proposed under the ongoing standardization efforts, design issues in terms of IoT hardware and software components, as well as the IoT application domain representatives, such as smart cities, healthcare, agriculture, and nano-scale applications (addressed within the concept of Internet of Nano-Things). In order to obtain the performances related to recently proposed protocols for emerging Industrial Internet of Things applications, the preliminary results for Message Queuing Telemetry Transport and Time-Slotted Channel Hopping protocols are provided. The testing was performed on OpenMote hardware platform and two IoT operating systems: Contiki and OpenWSN.
(19) 5G-XHaul: A Converged Optical and Wireless Solution for 5G Transport Networks
J. Gutierrez Teran, N. Maletic, D. Camps-Mur, E. Garcia, I. Berberana, M. Anastasopoulos, A. Tzanakaki, V. Kalokidou, P. Flegkas, D. Syrivelis, T. Korakis, P. Legg, D. Markovic, G. Lyberopoulos, J. Bartelt, J.K. Chaudhary, M. Grieger, N. Vucic, J. Zou, E. Grass
Transactions on Emerging Telecommunications Technologies 27(9), 1187 (2016)
DOI: 10.1002/ett.3063, (5G-XHaul)
(20) Cognitive Wireless Communications - A Paradigm Shift in Dealing with Radio Resources as a Prerequisite for the Wireless Network of the Future - An Overview on the Topic of Cognitive Wireless Technologies
T. Haustein, S. Stanczak, A. Wolisz, F. Jondral, J. Schotten, R. Kraemer, M. Mück, H. Mennenga, P. Bender
Frequenz: Journal of RF-Engineering and Telecommunications 70(7-8), 281 (2016)
Wireless radio communications systems form the basis for mobile network connections in the digital society. A limited amount of radio spectrum and a spatially densified use of wireless communications systems require a resource-efficient use of the spectrum. Mechanisms of cognitive radio may hold the key to a more efficient use of the available spectrum under consideration of quality of service requirements. These mechanisms take advantage of location-specific knowledge of the wireless channel occupation in the dimensions of frequency, time, location and direction in space and therefore enable co-existent and reliable wireless communication. The authors give an introduction to the status of cognitive wireless communication technology, which represents the starting point of a series of research projects promoted by BMBF during 2012–2014.
(21) High-Level Modeling and Testing of Multiple Control Faults in Digital Systems
A. Jasnetski, S.A. Oyeniran, A. Tsertov, M. Schölzel, R. Ubar
Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), (2016)
(DIAMANT)
(22) Secure Homomorphic Data Aggregation for Smart Energy Cconsumption Infrastructure
I. Kabin, K. Piotrowski, P. Langendörfer
Proc. 23rd Crypto-Day, 9 (2016)
(e-balance)
(23) On the Influence of Hardware Technologies on the Vulnerability of Protected ECC Implementations
I. Kabin, E. Alpirez Bock, Ch. Wittke, D. Kreiser, Z. Dyka, P. Langendörfer
Proc. Session on Work in Progress, 19th EUROMICRO Conference on Digital Systems Design (DSD 2016), (2016)
(24) Influence of Multiplier on the Security of Elliptic Curve Cryptography Design
I. Kabin, Z. Dyka, P. Langendörfer
Proc. 25rd Crypto-Day, (2016)
(MaSCH)
(25) 25-Gb/s/Channel VCSEL Driver and Transimpedance Amplifier Array ICs in 0.25-μm SiGe:C BiCMOS Technology for Space Applications
M. Ko, K. Tittelbach-Helmrich, V. Petrovic, D. Kissinger
Proc. 6th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications (AMICSA 2016), 102 (2016)
(MERLIN)
(26) ParSec: A PSSS Approach to Industrial Radio with Very Low and Very Flexible Cycle Timing
R. Kraemer, M. Methfessel, R. Kays, L. Underberg, A.C. Wolf
Proc. European Signal Processing Conference (EUSIPCO 2016), 1222 (2016)
(ParSec)
(27) Generation of Cryptographic Keys using Parameters of a Wireless Communication Channel in an Industrial Environment
D. Kreiser, Z. Dyka, P. Langendörfer, O. Stecklina
Proc. 25th Crypto-Day, (2016)
(ParSec)
(28) Enhanced Architectures for Soft Error Detection and Correction in Combinational and Sequential Circuits
M. Krstic, S. Weidling, V. Petrovic, E. Sogomonyan
Microelectronics Reliability 56, 212 (2016)
In this article a new method for the design of fault-tolerant pipelined sequential and
combinational circuits is described. The proposed methodology is based on error detection logic in the combinational circuit part combined with the sequential elements implemented using master-slave flip-flops. If a transient error due to a transient fault in the combinational circuit part is detected, the error signal controls the latching stage such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure is necessary. The target applications are dataflow processing blocks, where software based recovery methods cannot be easily applied. As a differentiator against the state-of-the-art, presented methodology addresses both single events as well as timing faults of arbitrarily long duration. A realistic implementation of this method is proposed and the timing conditions are carefully investigated and simulated. The improvement to the baseline methodology is demonstrated with respect to achieved fault tolerance for the example of a sum-bit duplicated adder.
(29) Asynchronous Design Methods for Dark Silicon Chips
M. Krstic
Festschrift on the Occasion of 60th Birthday of Prof. Alex Yakovlev, (2016)
(30) Prototyping and Business Potential
A. Krukowski, I. Lamprinos, D. Biswas, A. Cranny, E. Vogiatzaki, M. Schauer, St. Ortmann
Modern Stroke Rehabilitation through e-Health-based Entertainment, Springer, Chapter 9, 233 (2016)
(StrokeBack)
(31) Requirements and Conceptual Architecture
A. Krukowski, E. Vogiatzaki, St. Ortmann
Modern Stroke Rehabilitation through e-Health-based Entertainment, Springer, Chapter 2, 27 (2016)
(StrokeBack)
(32) Evaluations with Patients and Lessons Learned
A. Krukowski, I. Lamprinos, D. Biswas, A. Cranny, J. Achner, J. Klemke, M. Jöbges, St. Ortmann
Modern Stroke Rehabilitation through e-Health-based Entertainment, Springer, Chapter 10, 295 (2016)
(StrokeBack)
(33) 100 Gb/s Data Link Layer - from a Simulation to FPGA Implementation
L. Lopacinski, M. Brzozowski, R. Kraemer, S. Buechner, J. Nolte
Journal of Telecommunications and Information Technology (JTIT) 1, 90 (2016)
(DFG-SPP1655)
In the paper, simulation and hardware implementation of a data link layer for 100 Gbps Terahertz wireless communication is presented. The overhead of protocols and coding should be reduced to a minimum. This is especially important for high-speed networks, where a small degradation of efficiency will degrade the user data throughput by several Gbps. The following aspects are explained: an acknowledge frame compression, the optimal frame segmentation and aggregation, Reed-Solomon forward error correction, an algorithm to control the transmitted data redundancy (link adaptation), and FPGA (field programmable gate array) implementation of a demonstrator. The most important conclusion is that changing the segment size influences the uncoded transmissions mostly, and the FPGA memory footprint can be significantly reduced when the hybrid automatic repeat request type II is replaced by the type I with a link adaptation. Additionally, an algorithm for controlling the Reed-Solomon redundancy is presented. Hardware implementation is demonstrated, and the device achieves net data rate of 97 Gbps.
(34) Towards 100 Gbps Wireless Communication: Energy Efficiency of ARQ, FEC, and RF-Frontends
L. Lopacinski, M. Brzozowski, R. Kraemer, S. Buechner, J. Nolte
Proc. International Symposium on Wireless Communication Systems (ISWCS), 320 (2016)
(DFG-SPP1655)
This paper introduces recent results of 100 Gbps wireless transceiver design. Furthermore, energy for retransmissions and forward error correction is compared. The presented model estimates energy boundaries, when the fragment selective retransmissions are more energy efficient than forward error correction (FEC). In the targeted system, the FEC is relatively expensive and the FEC mode with the highest throughput is not optimal in terms of consumed energy per bit. Moreover, we compare energy efficiency of our data link layer processor to the energy required to transmit a single bit on the physical layer. In most cases, gain obtained by forward error correction consumes more energy than the gain obtained by power amplifiers in the terahertz band.
(35) Improved Turbo Product Coding dedicated for 100 Gbps Wireless Terahertz Communication
L. Lopacinski, M. Brzozowski, R. Kraemer, S. Buechner, J. Nolte
Proc. IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2016), 781 (2016)
(DFG-SPP1655)
in this article, an improved turbo product decoding scheme is proposed. The new method is almost as effective as hard decodable low-density parity check codes (HD-LDPC). Due to the modified codeword shape, no external interleavers are required to correct burst errors. If the decoder uses Reed-Solomon (RS) codes, then error correction performance against burst errors is significantly higher than the gain provided by HD-LDPC with an external interleaver. An additional advantage is a possibility to design a dedicated decoder for Virtex7 field programmable gate array (FPGA) serial transceivers. In our case, we use the method for 100 Gbps data link layer processor dedicated for wireless communication in the Terahertz band. The targeted platform is Virtex7 FPGA, but the solution can be easily scaled on other technologies.
(36) Automatic Clock: A Promising Approach Toward GALSification
M.J. Mamaghani, M. Krstic, J. Garside
Proc. 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 83 (2016)
(GAELS)
(37) Detecting Elementary Arm Movements by Tracking Upper Limb Joint Angles with MARG Sensors
E. Mazomenos, D. Biswas, A. Cranny, A. Rajan, K. Maharatna, J. Achner, J. Klemke, M. Jöbges, St. Ortmann, P. Langendörfer
IEEE Journal of Biomedical and Health Informatics 20(4), 1088 (2016)
(StrokeBack)
This paper reports an algorithm for the detection of three elementary upper limb movements, i.e., reach and retrieve, bend the arm at the elbow and rotation of the arm about the long
axis. We employ two MARG sensors, attached at the elbow and wrist, from which the kinematic properties (joint angles, position) of the upper arm and forearm are calculated through data fusion using a quaternion-based gradient-descent method and a two-link model of the upper limb. By studying the kinematic patterns of the three movements on a small dataset, we derive discriminative features that are indicative of each movement; these are then used to
formulate the proposed detection algorithm. Our novel approach of employing the joint angles and position to discriminate the three fundamental movements was evaluated in a series of experiments with 22 volunteers who participated in the study: 18 healthy subjects and four stroke survivors. In a controlled experiment, each volunteer was instructed to perform each movement a number of times. This was complimented by a seminaturalistic experiment
where the volunteers performed the same movements as subtasks of an activity that emulated the preparation of a cup of tea. In the stroke survivors group, the overall detection accuracy for all three movements was 93.75% and 83.00%, for the controlled and seminaturalistic
experiment, respectively. The performance was higher in the healthy group where 96.85% of the tasks in the controlled experiment and 89.69% in the seminaturalistic were detected correctly. Finally, the detection ratio remains close (±6%) to the average value, for different task durations further attesting to the algorithms robustness.
(38) Softwarebasierte Fehlertoleranz für Flash-Speicher von mikrocontroller-basierten Systemen
F. Mühlbauer, P. Skoncej, M. Schölzel
Proc. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2016), (2016)
(DIAMANT)
(39) Erkennung und Korrektur transienter Fehler durch Roll-back mit geringem Overhead
F. Mühlbauer, M. Schölzel
Proc. Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2016), 41 (2016)
(DIAMANT)
(40) Softwarebasierte Fehlertoleranz für Flash-Speicher von mikrocontroller-basierten Systemen
F. Mühlbauer, P. Skoncej, M. Schölzel
Proc. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2016), (2016)
(MOTARO)
(41) ASIC Implementation of Highly Reliable IR-UWB Transceiver for Industrial Automation
S. Olonbayar, G. Fischer, D. Kreiser, D. Martynenko, O. Klymenko, R. Kraemer, E. Grass
Frequenz: Journal of RF-Engineering and Telecommunications 70(7-8), 319 (2016)
(KUSZ)
An in-depth treatment of impulse an radio ultra-wideband (IR-UWB) wireless system is provided reviewing theoretical background, proceeding with detailed implementation procedure, and finally giving simulation and test results. This is the first research and prototyping work to be published in the field of IR-UWB that operates in the 6-8 GHz band. The aim of this work is to implement an IR-UWB wireless system for industrial automation that is robust and reliable. To achieve this, an analogue bandwidth of 250 MHz and digital baseband processing at the clock frequency 499.2 MHz were realized in a 250 nm BiCMOS process, integrating the complete system into a single chip. Simulation and measurement results confirm that the implemented IR-UWB transceiver is operational across four frequency channels in the band 6-8 GHz each supporting three data rates 850 kb/s, 6.81 Mb/s and 27.24 Mb/s.
(42) Data Flow Driven BAN: Architecture and Algorithms
St. Ortmann, P. Langendörfer
Modern Stroke Rehabilitation through e-Health-based Entertainment, Springer, Chapter 3, 51 (2016)
(StrokeBack)
(43) Telemedizinprojekt StrokeBack - Evidenzbasierte Tele-Rehabilitation für die obere Extremität
St. Ortmann
Physikalische Medizin Rehabilitationsmedizin Kurortmedizin 26, 201 (2016)
(StrokeBack)
Im Rahmen des EU-Projektes StrokeBack wurde untersucht, mit welchen Mitteln evidenzbasierte Therapien für die telemedizinische Rehabilitation nach dem Schlaganfall in der heimischen Umgebung umsetzbar sind.
Zielsetzung des StrokeBack Konzeptes ist es, erprobte Therapieansätze so zu digitalisieren, dass diese durch den Patienten selbstbestimmt und ohne Anwesenheit des Therapeuten zu Hause ausgeführt werden können. Dabei bekommt der Patient über ein Online-System einen individuellen Übungsplan erstellt, welcher automatisch auf ein Computer-Trainingssystem zuhause überspielt wird. Dieses Trainingssystem bietet dem Patienten verschiedene Übungen gemäß Plan an und überwacht deren Ausführung mit Hilfe optischer und digitaler Sensoren. Die therapeutische Intervention obliegt dabei ebenfalls dem Computersystem, d.h. der Patient bekommt direktes Feedback über die korrekte Ausführung der Übungen.
Im Projekt ist ein mobiles, kompaktes Computersystem in Koffergröße entstanden, über das dem Patient drei verschiedene Therapieformen angeboten werden, die mit kleinen Computerspielen kombiniert sind. Als erstes ermöglicht es repetitives Training mit Fokus auf die Handgelenksextension und das Öffnen/Schließen der Hand. Als zweite Variante kann Training mit einem haptischen Therapiegerät in der Form eines Würfels angeboten werden. Der Würfel ist drahtlos mit der Station verbunden und liefert Bewegungsdaten zur Ausführungskontrolle der Übung in Echtzeit. Als dritte Therapieform ist die musikunterstützte Therapie implementiert, bei der Patienten auf einem echten Keyboard vorgegebene Übungen kontrolliert ausführen können.
Das System wurde mit einzelnen Patienten während der Entwicklung fortlaufend erprobt und evaluiert. Am besten angenommen wurde das Training mit haptischem Feedback, wobei die Überwachung der Übungen mit optischen Sensoren zahlreiche Fallstricke offenbarte. Derzeit wird eine Studie zur Erprobung des Gerätes an der Berlin-Brandenburg-Klinik in Wandlitz durchgeführt.
(44) Wearable Sensors for Mobile Health Monitoring in Daily Life
St. Ortmann
Journal of Nursing & Care 5(4), 150 (2016)
DOI: 10.4172/2167-1168.C1.019, (myAirCoach)
Wearable sensing devices have become very popular for consumer health and fitness monitoring in the private sector. It is quite obvious that a mass of people in need of daily care, rehabilitation interventions, or patients with chronic diseases can also benefit from being monitored by smart wearables. We have developed a wearable sensor platform that was and is successfully applied for two different e-health applications, i.e. home rehabilitation after stroke and control of asthma patients respectively asthma control. In the stroke rehabilitation setting, we have been able to assess the effectiveness of ambulant therapy by analyzing motor skills during daily life activities. The progress of rehabilitation state can be documented by statistics about usage of upper limbs yet up to the point of comparing affected versus not-affected limbs.
For smart asthma control we develop prototypes of novel devices that collect insights of inhaler usages/medication in correlation to medication intakes, personal activities as well as environmental effects of the actual surroundings. Given that about 50 % of asthma patients are not well controlled, we expect boosting patient’s self-management capabilities by automated feedback and guiding features for disease control on 24/7 basis. Likewise we assume a monitoring of inhaler use allows physicians for much better dosing medications to prevent from risky over- or underspending of medication intake. Promising measurement results of laboratory settings are currently transferred into real-world prototypes.
The research leading to these results has received funding from the European Commission’s Horizon 2020 under grant agreement from project myAirCoach – No. 643607.
(45) Low Power Techniques in State-of-the-Art System on Chip Design
G. Panic
Proc. Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2016), 9 (2016)
(46) IHP Node Platform as a Base for Precision Farming and Remote Diagnosis in Agriculture
K. Piotrowski, A. Sojka-Piotrowska, Z. Stamenkovic, R. Kraemer
Proc. 24th Telecommunications Forum (TELFOR 2016), (2016)
(e-balance)
This paper presents the IHPNode platform in the context of precision farming (or Agriculture 4.0). This platform is an experimental platform for wireless sensor network (WSN) applications and can be used in precision farming as one of the most promising WSN application areas. The paper presents the requirements of the applications, the features of the IHPNode platform, as well as, the planned future improvements.
(47) IHP Node – The Experimental Platform for Wireless Sensor Networks and Internet of Things
K. Piotrowski, A. Sojka-Piotrowska
Proc. 11th Scientific Conference on Measurement Systems in Research and in Industry, 121 (2016)
(SMARTIE)
The article presents the hardware platform that was realized as the response to the demand for an experimental platform for applications in the area of wireless sensor networks and the Internet of Things. Together with the software support it enables an accelerated start for R&D projects as well as in product development in these areas. This article presents the defined modules of the platform and the experiences of the authors with these while implementing R&D projects.
(48) IHP Node – The Experimental Platform for Wireless Sensor Networks and Internet of Things
K. Piotrowski, A. Sojka-Piotrowska
Proc. 11th Scientific Conference on Measurement Systems in Research and in Industry, 121 (2016)
(e-balance)
The article presents the hardware platform that was realized as the response to the demand for an experimental platform for applications in the area of wireless sensor networks and the Internet of Things. Together with the software support it enables an accelerated start for R&D projects as well as in product development in these areas. This article presents the defined modules of the platform and the experiences of the authors with these while implementing R&D projects.
(49) IHP Node Platform as a Base for Precision Farming and Remote Diagnosis in Agriculture
K. Piotrowski, A. Sojka-Piotrowska, Z. Stamenkovic, R. Kraemer
Proc. 24th Telecommunications Forum (TELFOR 2016), (2016)
(SMARTIE)
This paper presents the IHPNode platform in the context of precision farming (or Agriculture 4.0). This platform is an experimental platform for wireless sensor network (WSN) applications and can be used in precision farming as one of the most promising WSN application areas. The paper presents the requirements of the applications, the features of the IHPNode platform, as well as, the planned future improvements.
(50) A Hierachical Architecture for an Energy Management System
K. Piotrowski, A. Casaca, M.E.T. Gerards, M. Jongerden, F. Melo, D. Garrido, M. Geers, J.J. Peralta
Proc. 10th Mediterranean Conference on Power Generation, Transmission, Distribution and Energy Conversion, (2016)
(e-balance)
(51) A Comprehensive Software-Based Self-Test and Self-Repair Method for Statically Scheduled Superscalar Processors
M. Schölzel, T. Koal, S. Müller, S. Scharoba, S. Röder, H.T. Vierhaus
Proc. IEEE Latin American Test Symposium (LATS 2016), 33 (2016)
(DIAMANT)
(52) Implementation of DBFN Processor for Synthetic Aperture Radar Application
O. Schrape, A. Koczor, P. Penkala, V. Petrovic, M. Krstic
Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), 175 (2016)
(Different)
One of the main reasons why Synthetic Aperture
Radar (SAR) is an attractive solution for earth surface screening
applications is its reliability independent on the wheather condi-
tions. This paper presents the implementation details of digital
beamforming baseband core processor for such a SAR system.
The processor chip is part of a distributed beamforming network
(DBFN) of 16 baseband processors where each one processes data
obtained from four 210MSPS ADC cores. Due to requirements
related to space environment, the baseband is implemented in
radiation-tolerant manner in order to temper single event effects
(SEE). Instead of full-chip protection, the baseband processor
uses only partially radhard flip-flops. This trade-off saves 25.87%
of silicon area based on gate-level synthesis results. A prototype
is produced in an low-cost variant of a 0.25µm BiCMOS process.
First measurement results show an average operating current of
445.49mA at a clock speed of 210MHz and a 2.5V power supply.
(53) Implementation of a Real Time Unit for Satellite Applications
A. Simevski, K. Schleisiek, V. Petrovic, N. Beller, P. Skoncej, G. Schoof, M. Krstic
Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), 180 (2016)
(RTU ASIC)
The significance of low cost small satellites used for scientific research and practical applications continuously grows. Current satellite OBC (On-Board Computer) microcontrollers have integrated various digital peripherals and interfaces. However, a common Real Time Unit (RTU) requires interfacing to simple analogue sensors and actuators. Here we present a novel RTU microcontroller which includes a 13-bit Analog-to-Digital Converter (ADC) and two 12-bit Digital-to-Analog Converters (DAC). Furthermore, it includes a 32KB internal SRAM memory and a 32KB internal flash memory. This enables an easy construction of a software-controlled embedded system which is easily interfaced to existing hardware sensors and actuators. The chip is produced in IHP 250nm technology using radiation hardening by design. The operating frequency is 80 MHz. A 3-bit clock divider, as well as clock- and power-gating are used for reducing power consumption which is measured to be 0,8W in operation.
(54) Feasibility of Software-based Repair for Program Memories
P. Skoncej, F. Mühlbauer, F. Kubicek, L. Schröder, M. Schölzel
Proc. 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2016), 199 (2016)
(MOTARO)
(55) Protecting Flash Memory Areas Against Memory Faults in Tiny Embedded Systems
P. Skoncej
Proc. 15th Biennial Baltic Electronics Conference (BEC 2016), 91 (2016)
(MOTARO)
(56) Feasibility of Software-based Repair for Program Memories
P. Skoncej, F. Mühlbauer, F. Kubicek, L. Schröder, M. Schölzel
Proc. 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2016), 199 (2016)
(DIAMANT)
(57) A Comprehensive Approach to Fault Tolerance: Device, Circuit, and System Techniques
Z. Stamenkovic, V. Petrovic
Proc. 17th IEEE Latin American Test Symposium (LATS 2016), (2016)
(SEPHY)
In spite of the huge research efforts and respectable scientific achievements, there are still challenges regarding the use of commercial ASIC technologies in space and safety-critical applications. This work presents a design methodology for fault-tolerant ASIC that is based on radiation-hard technology, redundant circuits with latchup protection, additional implementation steps during logic synthesis and layout generation, and power gating. Enhancements have been made within the standard ASIC design flow in order to incorporate redundancy and power-switch cells and, consequently, enable protection against single-event upset (SEU), single-event transient (SET), and single-event latchup (SEL). In order to validate the proposed fault-tolerant circuits, a fault-injection environment including fault models has been developed. The fault occurrence and its duration are modeled according to the real effects in actual hardware. Some of these techniques are being exploited and implemented in the SEPHY project (http://www.sephy.eu), which aims to increase the European competitiveness in the field of fault-tolerant ASIC by developing a radiation-hard PHY layer of the 10/100-Base-T Ethernet transceiver. The radiation-hard PHY layer ASIC will be fabricated in Atmel’s 150 nm technology. This device will enable the use of Ethernet in space systems and also provide the base to implement a radiation-hard Gigabit Ethernet PHY layer for space applications. Additionally, the developed techniques and devices can be of interest in other critical applications like automotive or industrial systems.
In order to automate a design flow of the fault-tolerant circuits, it is essential to design specific cells which are not present in the standard or radiation-hard design kits. A SEL protection switch (SPS) is described first. It consists of a current sensor/driver, feedback block, control block, and communication interface for a power network controller. Afterwards, the details of triple-modular redundant (TMR) and double-modular redundant (DMR) circuits with latchup protection and separated power domains are presented.
Fault-injection models for TMR and DMR circuits are developed in order to simulate and verify the fault-tolerant designs. Functional simulation of a digital design at the gate level suffices in case of the single-event transient and upset effects. However, in order to provide the information about design behavior during latchup effect, it is required to functionally simulate the design at the transistor level. We present TMR and DMR circuit simulation results with the implemented fault-injection models for all three types of the mentioned single-event effects.
Fault-tolerant ASICs can be implemented using the standard design automation tools and introducing a few additional steps in the standard design flow. An extra step is necessary to generate a modified design netlist including redundant cells, voters and required protection for memory blocks. The other two additional steps (definition of the power domains and placement of the SPS cells) have to be undertaken in the layout phase. The SPS cells are placed under the crossover points of the power stripes and cell rows. A SPS cell protects just one power domain and corresponding redundant logic.
(58) SOC Design for Wireless Communications (a three-hour tutorial)
Z. Stamenkovic
Proc. 29th International Conference on VLSI Design (VLSID 2016), 25 (2016)
(DEAL)
A common denominator of system-on-chip (SOC) design is research of how to integrate a whole system on one silicon chip. The tutorial emphasizes design methods, architectures and circuits towards system level integration. It gives the basic knowledge and skills for designing small, low-power, embedded devices. Besides tackling issues of functionality, an important goal is to understand the balancing of production cost, development time, and performance of such devices. The complexity of these devices increases exponentially, and so does the effort of designing such systems. Only by using an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The tutorial bundles these topics in order to provide a good understanding of all problems involved. Finally, it teaches how to design large systems and shows how to go from description and simulation to implementation and testing. A good SOC design flow assumes getting a design from the architectural level or RTL level to the chip layout. It should provide the designer with a working starting point for each stage of the design process. The tutorial describes such a methodology that relies on a library of configurable IP cores and custom hardware accelerators and satisfies the unique needs of wireless applications. The SOC design flow will be thoroughly examined with examples drawn from wireless communications.
This three-hour tutorial is aimed at engineers and scientists (familiar with basics of digital and analogue design) involved with system design who need to understand how to develop complex SOCs under severe time and cost constraints. The tutorial intends to provide training to engineers already familiar with hardware and software design.
(59) Advanced Wireless Sensor Nodes and Networks for Agricultural Applications
Z. Stamenkovic, S. Randjic, I. Santamaria, U. Pesovic, G. Panic, S. Tanaskovic
Proc. 24th Telecommunications Forum (TELFOR 2016), (2016)
(DFG-Serbien)
Wireless sensors and their networks can be effectively employed in the agricultural sector. They help to gather and cross-correlate critical data to make meaningful and timely operating decisions that enhance the production yield and profitability. A review of advanced wireless sensor nodes, networks, and applications in precision agriculture has been presented. Some machine learning techniques in this field have also been discussed.
(60) Compact Dual-Band Bandpass Waveguide Filter with H-Plane Inserts
S. Stefanovski, M. Potrebic, D. Tosic, Z. Stamenkovic
Journal of Circuits, Systems, and Computers (JCSC) 25(3), 1640015 (2016)
A novel compact dual-band bandpass waveguide filter is presented in this paper. H-plane metal inserts with complementary split-ring resonators are implemented as resonating elements in the standard (WR-90) rectangular waveguide. Design starts from the models of the waveguide resonators with two resonant frequencies (9 GHz and 11 GHz), using a single flat or folded metal insert. Further, folded inserts are used for the second-order dual-band filter design. The equivalent circuits are proposed for the considered waveguide resonators and filter. A good agreement of the amplitude responses obtained for three-dimensional electromagnetic models and microwave circuits is achieved. Finally, compact dual-band bandpass waveguide filter is proposed as a novel solution using miniaturized inverters for both central frequencies. Compact filter model is further modified in order to obtain solution customized for easier fabrication. For the compact filter model, amplitude response is experimentally verified. The required filter response is preserved, as verified by a good agreement of the results obtained for the original dual-band filter and for the compact filter solutions.
(61) Hardware Implementation of a Medium Access Control Layer for Industrial Wireless LAN
K. Tittelbach-Helmrich, Z. Stamenkovic
Proc. 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), 62 (2016)
(DEAL)
The paper describes a hardware solution for a custom WLAN Medium Access Control (MAC) layer, designed for Industry Automation applications. Architecture and implementation details of the MAC processor including system simulation and test procedures are presented.
(62) Implementing a Medium Access Control Protocol in Pure Hardware using SystemC
K. Tittelbach-Helmrich, Z. Stamenkovic
Proc. Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2016), 69 (2016)
(DEAL)
The paper describes design considerations and design flow for a MAC (Medium Access Control) layer of a communication system that is completely implemented in hardware. In order to work on a higher level of abstraction, we have done the design using the ‘SystemC’ language. System simulations can be carried out using standard digital design tools. Also, a tool ‘CtoS’ for converting SystemC to RTL-level Verilog or VHDL is available. The automatically generated RTL code serves as basis f or standard digital hardware design flow: synthesis, layout, and sign-off. This design flow turned out to be easy-to-use and delivering high quality results.
(63) 5G Infrastructures Supporting End-User and Operational Services: The 5G-XHaul Architectural Perspective
A. Tzanakaki, M. Anastasopoulos, D. Simeonidou, I. Berberana, D. Syrivelis, T. Korakis, P. Flegkas, D. Camps Mur, I. Demirkol, J. Gutierrez Teran, E. Grass, Q. Wei, E. Pateromichelakis, A. Fehske, M. Grieger, M. Eiselt, J. Bartelt, G. Lyberopoulos, E. Theodoropoulou
Proc. IEEE International Conference on Communications (ICC 2016), (2016)
DOI: 10.1109/ICCW.2016.7503764, (5G-XHaul)
(64) PSSS - Innovatives System zur Funkkommunikation für Industrie 4.0
L. Underberg, R. Kays, R. Kraemer, A.C. Wolf
Proc. VDE-Kongress 2016, (2016)
(65) Non-Cyclic Design Space Exploration for ASIPs — Compiler-Centered Microprocessor Design (CoMet)
R. Urban, H.T. Vierhaus, M. Schölzel, E. Altmann, H. Seelig
Journal of Circuits, Systems, and Computers (JCSC) 25(3), 1640012 (2016)
(DIAMANT)
The CoMet approach on designing application specific instruction set processors (ASIPs) is
targeting a non-cyclic design space exploration (DSE). The design process is driven by a step by step refinement of intermediate codes, known from compiler backends. In every step, the intermediate
code can be simulated and profiled. Based on that profiling information, it can be
further transformed to an optimized or refined intermediate code. The whole transformation
process is implemented in a GUI-based design tool, whose main component is a configurable
simulator for intermediate codes. It will be shown how the configurable intermediate code
simulator is used and how the intermediate code transformation and the VHDL generation of
the ASIP model will work in the CoMet tool.
(66) Application Study: RRAM for Low-Power Microcontrollers
F. Vater, M. Schölzel
Proc. 1st International Workshop on Emerging Memory Solutions (2016)
(DIAMANT)
The energy efficiency of today’s microcontrollers
is supported by the extensive usage of low-power mechanisms.
A full power-down requires in many cases a complex, and
maybe error prone, administration scheme, because data from
the volatile memory have to be stored in a flash based backup
memory. New types of non-volatile memory, e.g. in RRAM
technology, are faster and consumes a fraction of the energy
compared to flash technology. This paper evaluates power gating
for WSN with RRAM as back-up memory.
(67) A New Telerehabilitation System Based on Internet of Things
S. Vukicevic, Z. Stamenkovic, S. Murugesan, Z. Bogdanovic, B. Radenkovic
Facta Universitatis, Series: Electronics and Energetics 29(3), 395 (2016)
Internet of Things (IoT) applied in healthcare system has huge potential to improve patients' quality of life. Representing network of devices embedded with electronics and sensors, IoT enables constant monitoring of vital body functions, tracking of physical activities of a person and aides rehab physical therapy. Such an IoT-based system would allow standalone recovery process, minimizing need of dedicated medical personnel and could be used in both hospital and home conditions. In this paper, we present a telerehabilitation system that uses wearable muscle sensor and Microsoft Kinect to create interactive personalized physical therapy that can be carried out at home. Early experiments and results of pilot implementation validate the feasibility and effectiveness of the proposed IoT-enabled telerehabilitation system.
(68) Architektur mit reduzierter Komplexität zur Erkennung und Korrektur von transienten Fehlern in kombinatorischer und sequentieller Logik
S. Weidling, M. Krstic, V. Petrovic, E. Sogomonyan
Proc. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2016), (2016)
(69) Preparation of SCA Attacks: Successfully Decapsulating BGA Packages
Ch. Wittke, Z. Dyka, O. Skibitzki, P. Langendörfer
Proc. 9th International Conference on Security for Information Technology and Communications, (2016)
(70) Successfully Decapsulating BGA Packages: How To
Ch. Wittke, Z. Dyka, O. Skibitzki, P. Langendörfer
Proc. 24th Crypto-Day, 1 (2016)
(71) Sophisticated Placement of Flip-flops to Protect Cryptographic ASICs against Laser FI and Localized EMA
Ch. Wittke, Z. Dyka, P. Langendörfer
Proc. 25th Crypto-Day, (2016)
(72) Comparison of EM Probes using SEMA of an ECC Design
Ch. Wittke, Z. Dyka, P. Langendörfer
Proc. 8th IFIP International Conference on New Technologies, Mobility and Security (NTMS 2016), (2016)
(73) Probe Comparison for EM-Measurement in Terms of Side Channel Analysis
Ch. Wittke, Z. Dyka, P. Langendörfer
Proc. 23rd Crypto-Day, 8 (2016)
(74) An Early Stage Design Flow for Switching Noise Attenuation
St. Zeidler, X. Fan, O. Schrape, M. Krstic
Journal of Circuits, Systems, and Computers (JCSC) 25(3), 1640022 (2016)
(IC-NAO)
In the design of highly complex integrated circuits (ICs), switching noise is a raising problem. To handle this, current shaping techniques are applied to reduce current peaks causing ground bounce and voltage drops. Such techniques distribute the switching activity by adding phases and/or jitter to the clock of different domains. However, they are usually performed at later phases of the design process, i.e., in the chip layout. In this phase, the timing margins of the logic paths are typically fixed, which limits the clock phases that can be introduced between the domains. In this paper, we present a novel design preconditioning flow, which addresses the optimization of power noise characteristics of a design already at the frontend level. This allows early RTL-level design modifications, e.g., clock inversion or pipeline stage insertion, which potentially facilitate noise mitigation or enhance clock skewing in later design stages.
E. Alpirez Bock, Z. Dyka, P. Langendörfer
Proc. 24th Crypto-Day, (2016)
(myAirCoach)
Side channel analysis (SCA) attacks have been a popular research topic in the last years. Parameters
like power consumption, electromagnetic radiation and execution time of a cryptographic imple-
mentation can be analysed for identifying implementation details and based on this, extracting the
private key. The Montgomery kP-algorithm using Lopez-Dahab projective coordinates [LD99] is
an efficient method for performing the scalar multiplication in elliptic curve crypto-systems (ECC).
This algorithm is a bitwise processing of the scalar k, which is the private key used for performing
decryption in ECC. It is considered resistant against simple power analysis (SPA) since each key
bit is processed by the same type, amount and sequence of operations, independently of the key
bit's value. Nevertheless, its initialization phase affects this algorithm's robustness against SCA.
We describe how the first iteration of the kP processing loop reveals information about the key bit being processed, i.e. bit kl-2. Using simulated power traces, we demonstrate that the power profile of the processing of kl-2 differs from the power profiles of the processing of all other key bits. Moreover, we demonstrate that this power profile differs significantly for the cases kl-2 = 1 and kl-2 = 0. This leads to an easy extraction of bit kl-2 using SPA and exposes details of the implementation of the algorithm. This can be useful for the preparation of further attacks. As a countermeasure against this vulnerability, we propose a modification of the algorithm's initialization phase and of the processing of bit kl-2. We show that with this modification, the power profiles of the processings of kl-2 = 1 and kl-2 = 0 look similar to each other and similar to the processing of all remaining bits of the key, i.e. the value of the key bit kl-2 cannot be extracted using SPA. Our proposed modifications increase the algorithm's robustness against SCA and even reduce the time needed for the initialization phase and for processing kl-2. Compared to the original design, our new implementation needs only 0.12% additional area, while its energy consumption is almost the same, remaining by 2.09 J. Thus, we achieved to increase the security of our implementation without any additional costs.
(2) Efficient and Power Analysis Resistant Implementation of the Montgomery kP-Algorithm
E. Alpirez Bock, Z. Dyka, P. Langendörfer
Proc. 23rd Crypto-Day, 17 (2016)
(MaSCH)
(3) Increasing the Robustness of the Montgomery kP-Algorithm against SCA by Modifying its Initialization
E. Alpirez Bock, Z. Dyka, P. Langendörfer
Proc. International Conference on Information Technology and Communications Security, (2016)
DOI: 10.1007/978-3-319-47238-6_12, (myAirCoach)
The Montgomery kP-algorithm using Lopez-Dahab projec-
tive coordinates is a well-known method for performing the scalar multi-
plication in elliptic curve crypto-systems (ECC). It is considered resistant
against simple power analysis (SPA) since each key bit is processed by the
same type, amount and sequence of operations, independently of the key
bit's value. Nevertheless, its initialization phase a ects this algorithm's
robustness against side channel analysis (SCA) attacks. We describe how
the rst iteration of the kP processing loop reveals information about the
key bit being processed, i.e. bit kl-2. We explain how the value of this bit
can be extracted with SPA and how the power pro le of its processing can
reveal details about the implementation of the algorithm. We propose a
modi cation of the algorithm's initialization phase and of the processing
of bit kl-2, in order to hinder the extraction of its value using SPA. Our
proposed modi cations increase the algorithm's robustness against SCA
and even reduce the time needed for the initialization phase and for pro-
cessing kl-2. Compared to the original design, our new implementation
needs only 0.12% additional area, while its energy consumption is almost
the same, i.e. we improved the security of the design at no cost.
(4) SET Response of a SEL Protection Switch for 130 nm and 250 nm CMOS Technologies
M. Andjelkovic, A. Ilic, V. Petrovic, M. Nenadovic, Z. Stamenkovic, G. Ristic
Proc. IEEE International On-Line Testing Symposium (IOLTS 2016), 185 (2016)
This paper analyzes the single event transient (SET) response of a single event latchup (SEL) protection switch (SPS cell) designed in the 130 and 250 nm bulk CMOS technologies. The analysis has been conducted through the SPICE simulations, using the standard double exponential current source as the SET model. It has been confirmed that the 130 nm SPS cell is more susceptible to SETs than the 250 nm version, i.e. the 130 nm SPS cell has exhibited significantly lower critical charge. Based on the simulation results, an analytical model for estimating the critical charge in terms of the transistor size, load capacitance, supply voltage and duration of the SET current pulse, has been derived. Using the proposed critical charge model simplifies the analysis of the SPS cell’s susceptibility to SETs for custom designs.
(5) Performance Investigation on BCH Codec Implementations
D. Azinovic, K. Tittelbach-Helmrich, Z. Stamenkovic
Proc. 16th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2016), (2016)
(ParSec)
This paper investigates the performance of the BCH encoder and decoder for different error-correcting capabilities. The focus is on BCH codes of length 255. The motivation for this research is a project where data symbols of this length are transmitted over an error-prone wireless channel. The paper presents a mathematical introduction into encoding for cyclic codes and decoding of the BCH code. The code was implemented in both software and hardware and the performance and cost of both implementations were measured for different code parameters.
(6) GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits
M. Babic, St. Zeidler, M. Krstic
Proc. 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 67 (2016)
(GASEBO)
This paper proposes a methodology for substrate noise reduction in mixed-signal integrated circuits (IC) by using a globally-asynchronous locally-synchronous (GALS) approach for digital system integration. For this purpose the harmonic balanced partitioning strategy has been proposed. It has been shown that by converting a synchronous design into a plesiochronous GALS design with M locally-synchronous modules (LSMs), a theoretical limit of spectral peak attenuation corresponds to 20logM. This model has been evaluated by numerical simulations in MATLAB. Based on the proposed partitioning scheme, a methodology for GALS partitioning for optimal substrate noise reduction has been developed. Finally the corresponding low-noise GALS design flow has been proposed, based on a custom noise optimization tool named EMIAS. The flow has been evaluated on a realistic design example.
(7) 5G-XHaul: Enabling Scalable Virtualization for Future 5G Transport Networks
D. Camps-Mur, P. Flegkas, D. Syrivelis, Q. Wei, J. Gutierrez Teran
Proc. 15th International Conference on Ubiquitous Computing and Communications (IUCC 2016), 137 (2016)
DOI: 10.1109/IUCC-CSS.2016.032, (5G-XHaul)
(8) Un Middleware Centrado en Datos para el Control en Tiempo Real de Redes de Energia Inteligentes
J. Chen, E. Canete, M. Diaz, D. Garrido, K. Piotrowski
Proc. V Congreso espanol de Informatica (CEDI 2016), 19 (2016)
(e-balance)
(9) User's Requirements and Privacy Concerns as Canvas of Business Models and Active Demand Management within e-Balance System
W. Ciemniewski, M. Geers, B.E. Matusiak, K. Piotrowski
Proc. 13th International Conference on the European Energy Market (EEM 2016), 1 (2016)
(e-balance)
This paper presents an in depth analysis of the research regarding users requirements and system functionalities, business models and privacy issues as well as data security aspects in the energy balancing system. It is crucial for the system, that it has to be reliable and respond to users’ expectations. The system/platform itself is a result of European (FP7) collaborative project e-balance: Balancing the energy production and consumption in energy efficient smart neighbourhoods.
(10) Radiation-Hardened SiGe BiCMOS Technologies for Analogue and Mixed-Signal ICs
M. Cirillo, F. Teply, G. Fischer, R. Sorge, J. Schmidt, M. Krstic, V. Petrovic
Proc. 6th International Workshop on Analogue and Mixed Signal Integrated Circuits for Space Applications (AMICSA 2016), 48 (2016)
Introduction :
IHP is actively involved since many years in developing and providing un-restricted access to their high-performance 250nm and 130nm SiGe BiCMOS Technologies and Services.
In response to the strategic European non-dependence process for critical Space Technologies like EEE components, aiming to ensuring European free, un-restricted acces to any required space technology supply chain, IHP has been involved in the development of RadHard SiGe Process Design Kits (PDKs) for their SiGe BiCMOS technologies. For the 250nm node, a RadHard PDK SGB25RH has been developed and evaluated in accordance to the ESCC 2269010 Basic Specification “Evaluation Test Programme for MMICs” and will be filing for EPPL Listing in 2016 while for the 130nm Technology node, PDK SG13RH is under development and sensitivity to radiation (TID, DD, SEEs) is being evaluated before going through the full ESCC 2269010 Evaluation Test Programme (2017-2019) and release the SG13RH technology for EPPL Listing within 2020.
Content :
The integration of Silicon-Germanium (SiGe) onto BiCMOS technology platforms have been proven an economically viable and valuable technology for the design and implementation of low power highly integrated microwave monolithic integrated circuits (MMICs) operating at very high frequencies together with complex CMOS functions unavailable in other technologies. SiGe HBTs exhibit intrinsic advantages – such as a very high tolerance to Total Ionizing Dose (TID) greater than 1 Mrad(Si) and improved performances down to cryogenic temperatures – which make them excellent candidates for space-based applications which any independent ASIC/MMIC Design House can use to develop electronic components for the space market.
The presentation will focus on presenting the 250nm and 130nm IHP SiGe BiCMOS Processes, the contents of the RadHard PDKs (devices and libraries), the definition of the Capability Domain, status and results of the Evaluation Tests in accordance with ESCC-2269010 on the various Test Vehicles (TCV, DECs and RIC) . More recent results concerning radiation tests and reliability evaluations on both CMOS and SiGe HBT devices will be presented focusing on the failure modes of such devices and the required derating factors necessary to achieve reliability and mission lifetimes.
Conclusion :
The presentation will conclude with the description of IHP's access policy to the Rad Hard Design Kits and supported services (i.e. Lot Acceptance Tests – LATs defined in Process Identification Document – PID) from IHP and partners like Arquimea GmBH as well as the currently on-going activities and technology (such as Rad Hard LDMOS and Junction Isolated Cascode –JIC- CMOS) and library IP developments and enhancements foreseen for inclusion in future updates of the PDKs.
In addition a short overview of the current on-going R&D technology developments undertaken by IHP on their available commercial processes and IHP’s vision to the “More-than-Moore” approach like integration of THz Devices, Embedded RF-MEMS, Heterogeneous Integration (Micro-Fluidics, Through Silicon Vias, III-V on Si BiCMOS), Resistive-RAMs and Silicon Photonics which could prove useful for future compact low weight electronic components and System-on-Chip solutions for future Space or Ground-segment applications.
(11) Next Generation mm-Wave Wireless Backhaul Based on LOS MIMO Links
D. Cvetkovski, T. Haelsig, B. Lankl, E. Grass
Proc. German Microwave Conference (GeMiC 2016), 69 (2016)
(maximumMIMO)
With the evolution of the mobile networks towards more dense and flexible configurations, novel wireless backhaul solutions that can match the high capacity and flexibility demands are required in addition to the fixed fiber optics solutions. In this work we analyze the core backhaul requirements and the related system design challenges for utilizing the mm-wave frequency
band due to the large available bandwidth.
We determine the key performance metrics in terms of achievable throughput and energy efficiency of several transmission schemes seeking for a viable solution for the small cell backhaul scenario. Finally, an insight to the structure of the baseband domain required for processing multiple transmitted streams at the full system bandwidth is presented for a proposed LOS SM-MIMO system concept.
(12) Successful Simple Power Analysis of GALS ECC Design
Z. Dyka, F. Vater, D. Kreiser, P. Langendörfer
Proc. 23rd Crypto-Day, 5 (2016)
(Achilles)
(13) Revisiting Random Permutation of Calculation Steps of a Field Multiplication as a DPA Countermeasure
Z. Dyka, E. Alpirez Bock, I. Kabin, P. Langendörfer
Proc. 25th Crypto-Day, (2016)
(ECC)
(14) Inherent Resistance of Efficient ECC Designs Against SCA Attacks
Z. Dyka, E. Alpirez Bock, I. Kabin, P. Langendörfer
Proc. IFIP International Conference on New Technologies, Mobility and Security (NTMS 2016), (2016)
(MaSCH)
(15) Project FAST - Fast Actuators Sensors & Transceivers
F. Ellinger, T. Meister, P. Grosa, K. Jamshidi, D. Ihle, N. Franchi, J. Wagner, A. Richter, G. Fettweis, F. Fitzek, M. Kreissig, H. Klessig, E. Jorswiek, R. Kraemer, St. Ortmann, M. Schölzel, F. Gerfers, K. Richter, N. Elkmann, A. Frotzscher, H. Eisenreich, R. Löhr, W. Winkler, D. Zoeke, D. John, U. Fischer-Hirchert, A. Carôt, A. Bluschke, A. Richter
Proc. IEEE MTT-S Latin America Microwave Conference (LAMC 2016), (2016)
(16) Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling
X. Fan, M. Stegmann, O. Schrape, St. Zeidler, I. Jensen, J. Thorsen, T. Bjerregaard, M. Krstic
IEEE Transactions on Circuits and Systems I 63(7), 982 (2016)
(IC-NAO)
The simultaneous switching activity in digital circuits
challenges the design of mixed-signal SoCs. Rather than focusing
on time-domain noise voltage minimization, this work optimizes
switching noise in the frequency domain. A two-tier solution based
on the on-chip clock scheduling is proposed. First, to cope with the
switching noise at the fundamental clock frequency, which usually
dominates in terms of noise power, a two-phase clocking scheme
is employed for system timing. Second, on-chip clock latencies are
manipulated to target harmonic peaks in specific frequency bands
for the spectral noise optimization. An automated design flow,
which allows for noise optimization in user-defined applicationspecific
frequency bands, is developed. The effectiveness of our design
solution is validated by measurements of substrate noise and
conductive EMI (electromagnetic interference) noise on a test chip,
which consists of four wireless sensor node baseband processors
each addressing a distinct clock-tree-synthesis strategy. Compared
to the reference synchronous design, the proposed clock scheduling
solution substantially reduces noise in the target GSM-850 band,
i.e., by 11.1 dB on the substrate noise and 12.9 dB on the EMI noise,
along with dramatic noise peak drops measured at the 50-MHz
clock frequency.
(17) Cross-Plattform zur Hardware- und Betriebssystemunabhängigen Implementierung von Anwendungen und Protokollen
M. Frohberg, P. Poppe, N. Vetter, S. Reinhold, M. Schölzel
Proc. GI/ITG KuVS Fachgespräch Sensornetze (FGSN 2016), 47 (2016)
(DIAMANT)
In diesem Beitrag wird eine Cross-Plattform be-schrieben, die eine hardware- und betriebssystemunabhängige Implementierung von Protokollen und Anwendungen für Sen-sorknoten erlaubt. Dadurch soll in Umgebungen in denen viele heterogene Hardwareplattformen eingesetzt werden, die Wiederverwendbarkeit von Code bei der Entwicklung von Software selbst dann gewährleistet sein, wenn unterschiedliche Betriebssysteme auf verschiedenen Hardwareplattformen unterstützt werden müssen. Durch eine Integration von Instrumentalisierungsfunktionen in die Cross-Plattform kann diese zusätzlich das Testen und Überwachen verschiedener Abläufe im realen System plattformunabhängig unterstützen, und somit zur Produktivitätssteigerung in heterogenen Umgebungen beitragen.
(18) The IoT Architectural Framework, Design Issues and Application Domains
G. Gardasevic, M. Veletic, N. Maletic, D. Vasiljevic, I. Radusinovic, S. Tomovic, M. Radonjic
Wireless Personal Communications 92(1), 127 (2016)
The challenge raised by the introduction of Internet of Things (IoT) concept will permanently shape the networking and communications landscape and will therefore have a significant social impact. The ongoing IoT research activities are directed towards the definition and design of open architectures and standards, but there are still many issues requiring a global consensus before the final deployment. The paper presents and discusses the IoT architectural frameworks proposed under the ongoing standardization efforts, design issues in terms of IoT hardware and software components, as well as the IoT application domain representatives, such as smart cities, healthcare, agriculture, and nano-scale applications (addressed within the concept of Internet of Nano-Things). In order to obtain the performances related to recently proposed protocols for emerging Industrial Internet of Things applications, the preliminary results for Message Queuing Telemetry Transport and Time-Slotted Channel Hopping protocols are provided. The testing was performed on OpenMote hardware platform and two IoT operating systems: Contiki and OpenWSN.
(19) 5G-XHaul: A Converged Optical and Wireless Solution for 5G Transport Networks
J. Gutierrez Teran, N. Maletic, D. Camps-Mur, E. Garcia, I. Berberana, M. Anastasopoulos, A. Tzanakaki, V. Kalokidou, P. Flegkas, D. Syrivelis, T. Korakis, P. Legg, D. Markovic, G. Lyberopoulos, J. Bartelt, J.K. Chaudhary, M. Grieger, N. Vucic, J. Zou, E. Grass
Transactions on Emerging Telecommunications Technologies 27(9), 1187 (2016)
DOI: 10.1002/ett.3063, (5G-XHaul)
(20) Cognitive Wireless Communications - A Paradigm Shift in Dealing with Radio Resources as a Prerequisite for the Wireless Network of the Future - An Overview on the Topic of Cognitive Wireless Technologies
T. Haustein, S. Stanczak, A. Wolisz, F. Jondral, J. Schotten, R. Kraemer, M. Mück, H. Mennenga, P. Bender
Frequenz: Journal of RF-Engineering and Telecommunications 70(7-8), 281 (2016)
Wireless radio communications systems form the basis for mobile network connections in the digital society. A limited amount of radio spectrum and a spatially densified use of wireless communications systems require a resource-efficient use of the spectrum. Mechanisms of cognitive radio may hold the key to a more efficient use of the available spectrum under consideration of quality of service requirements. These mechanisms take advantage of location-specific knowledge of the wireless channel occupation in the dimensions of frequency, time, location and direction in space and therefore enable co-existent and reliable wireless communication. The authors give an introduction to the status of cognitive wireless communication technology, which represents the starting point of a series of research projects promoted by BMBF during 2012–2014.
(21) High-Level Modeling and Testing of Multiple Control Faults in Digital Systems
A. Jasnetski, S.A. Oyeniran, A. Tsertov, M. Schölzel, R. Ubar
Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), (2016)
(DIAMANT)
(22) Secure Homomorphic Data Aggregation for Smart Energy Cconsumption Infrastructure
I. Kabin, K. Piotrowski, P. Langendörfer
Proc. 23rd Crypto-Day, 9 (2016)
(e-balance)
(23) On the Influence of Hardware Technologies on the Vulnerability of Protected ECC Implementations
I. Kabin, E. Alpirez Bock, Ch. Wittke, D. Kreiser, Z. Dyka, P. Langendörfer
Proc. Session on Work in Progress, 19th EUROMICRO Conference on Digital Systems Design (DSD 2016), (2016)
(24) Influence of Multiplier on the Security of Elliptic Curve Cryptography Design
I. Kabin, Z. Dyka, P. Langendörfer
Proc. 25rd Crypto-Day, (2016)
(MaSCH)
(25) 25-Gb/s/Channel VCSEL Driver and Transimpedance Amplifier Array ICs in 0.25-μm SiGe:C BiCMOS Technology for Space Applications
M. Ko, K. Tittelbach-Helmrich, V. Petrovic, D. Kissinger
Proc. 6th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications (AMICSA 2016), 102 (2016)
(MERLIN)
(26) ParSec: A PSSS Approach to Industrial Radio with Very Low and Very Flexible Cycle Timing
R. Kraemer, M. Methfessel, R. Kays, L. Underberg, A.C. Wolf
Proc. European Signal Processing Conference (EUSIPCO 2016), 1222 (2016)
(ParSec)
(27) Generation of Cryptographic Keys using Parameters of a Wireless Communication Channel in an Industrial Environment
D. Kreiser, Z. Dyka, P. Langendörfer, O. Stecklina
Proc. 25th Crypto-Day, (2016)
(ParSec)
(28) Enhanced Architectures for Soft Error Detection and Correction in Combinational and Sequential Circuits
M. Krstic, S. Weidling, V. Petrovic, E. Sogomonyan
Microelectronics Reliability 56, 212 (2016)
In this article a new method for the design of fault-tolerant pipelined sequential and
combinational circuits is described. The proposed methodology is based on error detection logic in the combinational circuit part combined with the sequential elements implemented using master-slave flip-flops. If a transient error due to a transient fault in the combinational circuit part is detected, the error signal controls the latching stage such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure is necessary. The target applications are dataflow processing blocks, where software based recovery methods cannot be easily applied. As a differentiator against the state-of-the-art, presented methodology addresses both single events as well as timing faults of arbitrarily long duration. A realistic implementation of this method is proposed and the timing conditions are carefully investigated and simulated. The improvement to the baseline methodology is demonstrated with respect to achieved fault tolerance for the example of a sum-bit duplicated adder.
(29) Asynchronous Design Methods for Dark Silicon Chips
M. Krstic
Festschrift on the Occasion of 60th Birthday of Prof. Alex Yakovlev, (2016)
(30) Prototyping and Business Potential
A. Krukowski, I. Lamprinos, D. Biswas, A. Cranny, E. Vogiatzaki, M. Schauer, St. Ortmann
Modern Stroke Rehabilitation through e-Health-based Entertainment, Springer, Chapter 9, 233 (2016)
(StrokeBack)
(31) Requirements and Conceptual Architecture
A. Krukowski, E. Vogiatzaki, St. Ortmann
Modern Stroke Rehabilitation through e-Health-based Entertainment, Springer, Chapter 2, 27 (2016)
(StrokeBack)
(32) Evaluations with Patients and Lessons Learned
A. Krukowski, I. Lamprinos, D. Biswas, A. Cranny, J. Achner, J. Klemke, M. Jöbges, St. Ortmann
Modern Stroke Rehabilitation through e-Health-based Entertainment, Springer, Chapter 10, 295 (2016)
(StrokeBack)
(33) 100 Gb/s Data Link Layer - from a Simulation to FPGA Implementation
L. Lopacinski, M. Brzozowski, R. Kraemer, S. Buechner, J. Nolte
Journal of Telecommunications and Information Technology (JTIT) 1, 90 (2016)
(DFG-SPP1655)
In the paper, simulation and hardware implementation of a data link layer for 100 Gbps Terahertz wireless communication is presented. The overhead of protocols and coding should be reduced to a minimum. This is especially important for high-speed networks, where a small degradation of efficiency will degrade the user data throughput by several Gbps. The following aspects are explained: an acknowledge frame compression, the optimal frame segmentation and aggregation, Reed-Solomon forward error correction, an algorithm to control the transmitted data redundancy (link adaptation), and FPGA (field programmable gate array) implementation of a demonstrator. The most important conclusion is that changing the segment size influences the uncoded transmissions mostly, and the FPGA memory footprint can be significantly reduced when the hybrid automatic repeat request type II is replaced by the type I with a link adaptation. Additionally, an algorithm for controlling the Reed-Solomon redundancy is presented. Hardware implementation is demonstrated, and the device achieves net data rate of 97 Gbps.
(34) Towards 100 Gbps Wireless Communication: Energy Efficiency of ARQ, FEC, and RF-Frontends
L. Lopacinski, M. Brzozowski, R. Kraemer, S. Buechner, J. Nolte
Proc. International Symposium on Wireless Communication Systems (ISWCS), 320 (2016)
(DFG-SPP1655)
This paper introduces recent results of 100 Gbps wireless transceiver design. Furthermore, energy for retransmissions and forward error correction is compared. The presented model estimates energy boundaries, when the fragment selective retransmissions are more energy efficient than forward error correction (FEC). In the targeted system, the FEC is relatively expensive and the FEC mode with the highest throughput is not optimal in terms of consumed energy per bit. Moreover, we compare energy efficiency of our data link layer processor to the energy required to transmit a single bit on the physical layer. In most cases, gain obtained by forward error correction consumes more energy than the gain obtained by power amplifiers in the terahertz band.
(35) Improved Turbo Product Coding dedicated for 100 Gbps Wireless Terahertz Communication
L. Lopacinski, M. Brzozowski, R. Kraemer, S. Buechner, J. Nolte
Proc. IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2016), 781 (2016)
(DFG-SPP1655)
in this article, an improved turbo product decoding scheme is proposed. The new method is almost as effective as hard decodable low-density parity check codes (HD-LDPC). Due to the modified codeword shape, no external interleavers are required to correct burst errors. If the decoder uses Reed-Solomon (RS) codes, then error correction performance against burst errors is significantly higher than the gain provided by HD-LDPC with an external interleaver. An additional advantage is a possibility to design a dedicated decoder for Virtex7 field programmable gate array (FPGA) serial transceivers. In our case, we use the method for 100 Gbps data link layer processor dedicated for wireless communication in the Terahertz band. The targeted platform is Virtex7 FPGA, but the solution can be easily scaled on other technologies.
(36) Automatic Clock: A Promising Approach Toward GALSification
M.J. Mamaghani, M. Krstic, J. Garside
Proc. 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 83 (2016)
(GAELS)
(37) Detecting Elementary Arm Movements by Tracking Upper Limb Joint Angles with MARG Sensors
E. Mazomenos, D. Biswas, A. Cranny, A. Rajan, K. Maharatna, J. Achner, J. Klemke, M. Jöbges, St. Ortmann, P. Langendörfer
IEEE Journal of Biomedical and Health Informatics 20(4), 1088 (2016)
(StrokeBack)
This paper reports an algorithm for the detection of three elementary upper limb movements, i.e., reach and retrieve, bend the arm at the elbow and rotation of the arm about the long
axis. We employ two MARG sensors, attached at the elbow and wrist, from which the kinematic properties (joint angles, position) of the upper arm and forearm are calculated through data fusion using a quaternion-based gradient-descent method and a two-link model of the upper limb. By studying the kinematic patterns of the three movements on a small dataset, we derive discriminative features that are indicative of each movement; these are then used to
formulate the proposed detection algorithm. Our novel approach of employing the joint angles and position to discriminate the three fundamental movements was evaluated in a series of experiments with 22 volunteers who participated in the study: 18 healthy subjects and four stroke survivors. In a controlled experiment, each volunteer was instructed to perform each movement a number of times. This was complimented by a seminaturalistic experiment
where the volunteers performed the same movements as subtasks of an activity that emulated the preparation of a cup of tea. In the stroke survivors group, the overall detection accuracy for all three movements was 93.75% and 83.00%, for the controlled and seminaturalistic
experiment, respectively. The performance was higher in the healthy group where 96.85% of the tasks in the controlled experiment and 89.69% in the seminaturalistic were detected correctly. Finally, the detection ratio remains close (±6%) to the average value, for different task durations further attesting to the algorithms robustness.
(38) Softwarebasierte Fehlertoleranz für Flash-Speicher von mikrocontroller-basierten Systemen
F. Mühlbauer, P. Skoncej, M. Schölzel
Proc. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2016), (2016)
(DIAMANT)
(39) Erkennung und Korrektur transienter Fehler durch Roll-back mit geringem Overhead
F. Mühlbauer, M. Schölzel
Proc. Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2016), 41 (2016)
(DIAMANT)
(40) Softwarebasierte Fehlertoleranz für Flash-Speicher von mikrocontroller-basierten Systemen
F. Mühlbauer, P. Skoncej, M. Schölzel
Proc. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2016), (2016)
(MOTARO)
(41) ASIC Implementation of Highly Reliable IR-UWB Transceiver for Industrial Automation
S. Olonbayar, G. Fischer, D. Kreiser, D. Martynenko, O. Klymenko, R. Kraemer, E. Grass
Frequenz: Journal of RF-Engineering and Telecommunications 70(7-8), 319 (2016)
(KUSZ)
An in-depth treatment of impulse an radio ultra-wideband (IR-UWB) wireless system is provided reviewing theoretical background, proceeding with detailed implementation procedure, and finally giving simulation and test results. This is the first research and prototyping work to be published in the field of IR-UWB that operates in the 6-8 GHz band. The aim of this work is to implement an IR-UWB wireless system for industrial automation that is robust and reliable. To achieve this, an analogue bandwidth of 250 MHz and digital baseband processing at the clock frequency 499.2 MHz were realized in a 250 nm BiCMOS process, integrating the complete system into a single chip. Simulation and measurement results confirm that the implemented IR-UWB transceiver is operational across four frequency channels in the band 6-8 GHz each supporting three data rates 850 kb/s, 6.81 Mb/s and 27.24 Mb/s.
(42) Data Flow Driven BAN: Architecture and Algorithms
St. Ortmann, P. Langendörfer
Modern Stroke Rehabilitation through e-Health-based Entertainment, Springer, Chapter 3, 51 (2016)
(StrokeBack)
(43) Telemedizinprojekt StrokeBack - Evidenzbasierte Tele-Rehabilitation für die obere Extremität
St. Ortmann
Physikalische Medizin Rehabilitationsmedizin Kurortmedizin 26, 201 (2016)
(StrokeBack)
Im Rahmen des EU-Projektes StrokeBack wurde untersucht, mit welchen Mitteln evidenzbasierte Therapien für die telemedizinische Rehabilitation nach dem Schlaganfall in der heimischen Umgebung umsetzbar sind.
Zielsetzung des StrokeBack Konzeptes ist es, erprobte Therapieansätze so zu digitalisieren, dass diese durch den Patienten selbstbestimmt und ohne Anwesenheit des Therapeuten zu Hause ausgeführt werden können. Dabei bekommt der Patient über ein Online-System einen individuellen Übungsplan erstellt, welcher automatisch auf ein Computer-Trainingssystem zuhause überspielt wird. Dieses Trainingssystem bietet dem Patienten verschiedene Übungen gemäß Plan an und überwacht deren Ausführung mit Hilfe optischer und digitaler Sensoren. Die therapeutische Intervention obliegt dabei ebenfalls dem Computersystem, d.h. der Patient bekommt direktes Feedback über die korrekte Ausführung der Übungen.
Im Projekt ist ein mobiles, kompaktes Computersystem in Koffergröße entstanden, über das dem Patient drei verschiedene Therapieformen angeboten werden, die mit kleinen Computerspielen kombiniert sind. Als erstes ermöglicht es repetitives Training mit Fokus auf die Handgelenksextension und das Öffnen/Schließen der Hand. Als zweite Variante kann Training mit einem haptischen Therapiegerät in der Form eines Würfels angeboten werden. Der Würfel ist drahtlos mit der Station verbunden und liefert Bewegungsdaten zur Ausführungskontrolle der Übung in Echtzeit. Als dritte Therapieform ist die musikunterstützte Therapie implementiert, bei der Patienten auf einem echten Keyboard vorgegebene Übungen kontrolliert ausführen können.
Das System wurde mit einzelnen Patienten während der Entwicklung fortlaufend erprobt und evaluiert. Am besten angenommen wurde das Training mit haptischem Feedback, wobei die Überwachung der Übungen mit optischen Sensoren zahlreiche Fallstricke offenbarte. Derzeit wird eine Studie zur Erprobung des Gerätes an der Berlin-Brandenburg-Klinik in Wandlitz durchgeführt.
(44) Wearable Sensors for Mobile Health Monitoring in Daily Life
St. Ortmann
Journal of Nursing & Care 5(4), 150 (2016)
DOI: 10.4172/2167-1168.C1.019, (myAirCoach)
Wearable sensing devices have become very popular for consumer health and fitness monitoring in the private sector. It is quite obvious that a mass of people in need of daily care, rehabilitation interventions, or patients with chronic diseases can also benefit from being monitored by smart wearables. We have developed a wearable sensor platform that was and is successfully applied for two different e-health applications, i.e. home rehabilitation after stroke and control of asthma patients respectively asthma control. In the stroke rehabilitation setting, we have been able to assess the effectiveness of ambulant therapy by analyzing motor skills during daily life activities. The progress of rehabilitation state can be documented by statistics about usage of upper limbs yet up to the point of comparing affected versus not-affected limbs.
For smart asthma control we develop prototypes of novel devices that collect insights of inhaler usages/medication in correlation to medication intakes, personal activities as well as environmental effects of the actual surroundings. Given that about 50 % of asthma patients are not well controlled, we expect boosting patient’s self-management capabilities by automated feedback and guiding features for disease control on 24/7 basis. Likewise we assume a monitoring of inhaler use allows physicians for much better dosing medications to prevent from risky over- or underspending of medication intake. Promising measurement results of laboratory settings are currently transferred into real-world prototypes.
The research leading to these results has received funding from the European Commission’s Horizon 2020 under grant agreement from project myAirCoach – No. 643607.
(45) Low Power Techniques in State-of-the-Art System on Chip Design
G. Panic
Proc. Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2016), 9 (2016)
(46) IHP Node Platform as a Base for Precision Farming and Remote Diagnosis in Agriculture
K. Piotrowski, A. Sojka-Piotrowska, Z. Stamenkovic, R. Kraemer
Proc. 24th Telecommunications Forum (TELFOR 2016), (2016)
(e-balance)
This paper presents the IHPNode platform in the context of precision farming (or Agriculture 4.0). This platform is an experimental platform for wireless sensor network (WSN) applications and can be used in precision farming as one of the most promising WSN application areas. The paper presents the requirements of the applications, the features of the IHPNode platform, as well as, the planned future improvements.
(47) IHP Node – The Experimental Platform for Wireless Sensor Networks and Internet of Things
K. Piotrowski, A. Sojka-Piotrowska
Proc. 11th Scientific Conference on Measurement Systems in Research and in Industry, 121 (2016)
(SMARTIE)
The article presents the hardware platform that was realized as the response to the demand for an experimental platform for applications in the area of wireless sensor networks and the Internet of Things. Together with the software support it enables an accelerated start for R&D projects as well as in product development in these areas. This article presents the defined modules of the platform and the experiences of the authors with these while implementing R&D projects.
(48) IHP Node – The Experimental Platform for Wireless Sensor Networks and Internet of Things
K. Piotrowski, A. Sojka-Piotrowska
Proc. 11th Scientific Conference on Measurement Systems in Research and in Industry, 121 (2016)
(e-balance)
The article presents the hardware platform that was realized as the response to the demand for an experimental platform for applications in the area of wireless sensor networks and the Internet of Things. Together with the software support it enables an accelerated start for R&D projects as well as in product development in these areas. This article presents the defined modules of the platform and the experiences of the authors with these while implementing R&D projects.
(49) IHP Node Platform as a Base for Precision Farming and Remote Diagnosis in Agriculture
K. Piotrowski, A. Sojka-Piotrowska, Z. Stamenkovic, R. Kraemer
Proc. 24th Telecommunications Forum (TELFOR 2016), (2016)
(SMARTIE)
This paper presents the IHPNode platform in the context of precision farming (or Agriculture 4.0). This platform is an experimental platform for wireless sensor network (WSN) applications and can be used in precision farming as one of the most promising WSN application areas. The paper presents the requirements of the applications, the features of the IHPNode platform, as well as, the planned future improvements.
(50) A Hierachical Architecture for an Energy Management System
K. Piotrowski, A. Casaca, M.E.T. Gerards, M. Jongerden, F. Melo, D. Garrido, M. Geers, J.J. Peralta
Proc. 10th Mediterranean Conference on Power Generation, Transmission, Distribution and Energy Conversion, (2016)
(e-balance)
(51) A Comprehensive Software-Based Self-Test and Self-Repair Method for Statically Scheduled Superscalar Processors
M. Schölzel, T. Koal, S. Müller, S. Scharoba, S. Röder, H.T. Vierhaus
Proc. IEEE Latin American Test Symposium (LATS 2016), 33 (2016)
(DIAMANT)
(52) Implementation of DBFN Processor for Synthetic Aperture Radar Application
O. Schrape, A. Koczor, P. Penkala, V. Petrovic, M. Krstic
Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), 175 (2016)
(Different)
One of the main reasons why Synthetic Aperture
Radar (SAR) is an attractive solution for earth surface screening
applications is its reliability independent on the wheather condi-
tions. This paper presents the implementation details of digital
beamforming baseband core processor for such a SAR system.
The processor chip is part of a distributed beamforming network
(DBFN) of 16 baseband processors where each one processes data
obtained from four 210MSPS ADC cores. Due to requirements
related to space environment, the baseband is implemented in
radiation-tolerant manner in order to temper single event effects
(SEE). Instead of full-chip protection, the baseband processor
uses only partially radhard flip-flops. This trade-off saves 25.87%
of silicon area based on gate-level synthesis results. A prototype
is produced in an low-cost variant of a 0.25µm BiCMOS process.
First measurement results show an average operating current of
445.49mA at a clock speed of 210MHz and a 2.5V power supply.
(53) Implementation of a Real Time Unit for Satellite Applications
A. Simevski, K. Schleisiek, V. Petrovic, N. Beller, P. Skoncej, G. Schoof, M. Krstic
Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), 180 (2016)
(RTU ASIC)
The significance of low cost small satellites used for scientific research and practical applications continuously grows. Current satellite OBC (On-Board Computer) microcontrollers have integrated various digital peripherals and interfaces. However, a common Real Time Unit (RTU) requires interfacing to simple analogue sensors and actuators. Here we present a novel RTU microcontroller which includes a 13-bit Analog-to-Digital Converter (ADC) and two 12-bit Digital-to-Analog Converters (DAC). Furthermore, it includes a 32KB internal SRAM memory and a 32KB internal flash memory. This enables an easy construction of a software-controlled embedded system which is easily interfaced to existing hardware sensors and actuators. The chip is produced in IHP 250nm technology using radiation hardening by design. The operating frequency is 80 MHz. A 3-bit clock divider, as well as clock- and power-gating are used for reducing power consumption which is measured to be 0,8W in operation.
(54) Feasibility of Software-based Repair for Program Memories
P. Skoncej, F. Mühlbauer, F. Kubicek, L. Schröder, M. Schölzel
Proc. 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2016), 199 (2016)
(MOTARO)
(55) Protecting Flash Memory Areas Against Memory Faults in Tiny Embedded Systems
P. Skoncej
Proc. 15th Biennial Baltic Electronics Conference (BEC 2016), 91 (2016)
(MOTARO)
(56) Feasibility of Software-based Repair for Program Memories
P. Skoncej, F. Mühlbauer, F. Kubicek, L. Schröder, M. Schölzel
Proc. 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2016), 199 (2016)
(DIAMANT)
(57) A Comprehensive Approach to Fault Tolerance: Device, Circuit, and System Techniques
Z. Stamenkovic, V. Petrovic
Proc. 17th IEEE Latin American Test Symposium (LATS 2016), (2016)
(SEPHY)
In spite of the huge research efforts and respectable scientific achievements, there are still challenges regarding the use of commercial ASIC technologies in space and safety-critical applications. This work presents a design methodology for fault-tolerant ASIC that is based on radiation-hard technology, redundant circuits with latchup protection, additional implementation steps during logic synthesis and layout generation, and power gating. Enhancements have been made within the standard ASIC design flow in order to incorporate redundancy and power-switch cells and, consequently, enable protection against single-event upset (SEU), single-event transient (SET), and single-event latchup (SEL). In order to validate the proposed fault-tolerant circuits, a fault-injection environment including fault models has been developed. The fault occurrence and its duration are modeled according to the real effects in actual hardware. Some of these techniques are being exploited and implemented in the SEPHY project (http://www.sephy.eu), which aims to increase the European competitiveness in the field of fault-tolerant ASIC by developing a radiation-hard PHY layer of the 10/100-Base-T Ethernet transceiver. The radiation-hard PHY layer ASIC will be fabricated in Atmel’s 150 nm technology. This device will enable the use of Ethernet in space systems and also provide the base to implement a radiation-hard Gigabit Ethernet PHY layer for space applications. Additionally, the developed techniques and devices can be of interest in other critical applications like automotive or industrial systems.
In order to automate a design flow of the fault-tolerant circuits, it is essential to design specific cells which are not present in the standard or radiation-hard design kits. A SEL protection switch (SPS) is described first. It consists of a current sensor/driver, feedback block, control block, and communication interface for a power network controller. Afterwards, the details of triple-modular redundant (TMR) and double-modular redundant (DMR) circuits with latchup protection and separated power domains are presented.
Fault-injection models for TMR and DMR circuits are developed in order to simulate and verify the fault-tolerant designs. Functional simulation of a digital design at the gate level suffices in case of the single-event transient and upset effects. However, in order to provide the information about design behavior during latchup effect, it is required to functionally simulate the design at the transistor level. We present TMR and DMR circuit simulation results with the implemented fault-injection models for all three types of the mentioned single-event effects.
Fault-tolerant ASICs can be implemented using the standard design automation tools and introducing a few additional steps in the standard design flow. An extra step is necessary to generate a modified design netlist including redundant cells, voters and required protection for memory blocks. The other two additional steps (definition of the power domains and placement of the SPS cells) have to be undertaken in the layout phase. The SPS cells are placed under the crossover points of the power stripes and cell rows. A SPS cell protects just one power domain and corresponding redundant logic.
(58) SOC Design for Wireless Communications (a three-hour tutorial)
Z. Stamenkovic
Proc. 29th International Conference on VLSI Design (VLSID 2016), 25 (2016)
(DEAL)
A common denominator of system-on-chip (SOC) design is research of how to integrate a whole system on one silicon chip. The tutorial emphasizes design methods, architectures and circuits towards system level integration. It gives the basic knowledge and skills for designing small, low-power, embedded devices. Besides tackling issues of functionality, an important goal is to understand the balancing of production cost, development time, and performance of such devices. The complexity of these devices increases exponentially, and so does the effort of designing such systems. Only by using an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The tutorial bundles these topics in order to provide a good understanding of all problems involved. Finally, it teaches how to design large systems and shows how to go from description and simulation to implementation and testing. A good SOC design flow assumes getting a design from the architectural level or RTL level to the chip layout. It should provide the designer with a working starting point for each stage of the design process. The tutorial describes such a methodology that relies on a library of configurable IP cores and custom hardware accelerators and satisfies the unique needs of wireless applications. The SOC design flow will be thoroughly examined with examples drawn from wireless communications.
This three-hour tutorial is aimed at engineers and scientists (familiar with basics of digital and analogue design) involved with system design who need to understand how to develop complex SOCs under severe time and cost constraints. The tutorial intends to provide training to engineers already familiar with hardware and software design.
(59) Advanced Wireless Sensor Nodes and Networks for Agricultural Applications
Z. Stamenkovic, S. Randjic, I. Santamaria, U. Pesovic, G. Panic, S. Tanaskovic
Proc. 24th Telecommunications Forum (TELFOR 2016), (2016)
(DFG-Serbien)
Wireless sensors and their networks can be effectively employed in the agricultural sector. They help to gather and cross-correlate critical data to make meaningful and timely operating decisions that enhance the production yield and profitability. A review of advanced wireless sensor nodes, networks, and applications in precision agriculture has been presented. Some machine learning techniques in this field have also been discussed.
(60) Compact Dual-Band Bandpass Waveguide Filter with H-Plane Inserts
S. Stefanovski, M. Potrebic, D. Tosic, Z. Stamenkovic
Journal of Circuits, Systems, and Computers (JCSC) 25(3), 1640015 (2016)
A novel compact dual-band bandpass waveguide filter is presented in this paper. H-plane metal inserts with complementary split-ring resonators are implemented as resonating elements in the standard (WR-90) rectangular waveguide. Design starts from the models of the waveguide resonators with two resonant frequencies (9 GHz and 11 GHz), using a single flat or folded metal insert. Further, folded inserts are used for the second-order dual-band filter design. The equivalent circuits are proposed for the considered waveguide resonators and filter. A good agreement of the amplitude responses obtained for three-dimensional electromagnetic models and microwave circuits is achieved. Finally, compact dual-band bandpass waveguide filter is proposed as a novel solution using miniaturized inverters for both central frequencies. Compact filter model is further modified in order to obtain solution customized for easier fabrication. For the compact filter model, amplitude response is experimentally verified. The required filter response is preserved, as verified by a good agreement of the results obtained for the original dual-band filter and for the compact filter solutions.
(61) Hardware Implementation of a Medium Access Control Layer for Industrial Wireless LAN
K. Tittelbach-Helmrich, Z. Stamenkovic
Proc. 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2016), 62 (2016)
(DEAL)
The paper describes a hardware solution for a custom WLAN Medium Access Control (MAC) layer, designed for Industry Automation applications. Architecture and implementation details of the MAC processor including system simulation and test procedures are presented.
(62) Implementing a Medium Access Control Protocol in Pure Hardware using SystemC
K. Tittelbach-Helmrich, Z. Stamenkovic
Proc. Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2016), 69 (2016)
(DEAL)
The paper describes design considerations and design flow for a MAC (Medium Access Control) layer of a communication system that is completely implemented in hardware. In order to work on a higher level of abstraction, we have done the design using the ‘SystemC’ language. System simulations can be carried out using standard digital design tools. Also, a tool ‘CtoS’ for converting SystemC to RTL-level Verilog or VHDL is available. The automatically generated RTL code serves as basis f or standard digital hardware design flow: synthesis, layout, and sign-off. This design flow turned out to be easy-to-use and delivering high quality results.
(63) 5G Infrastructures Supporting End-User and Operational Services: The 5G-XHaul Architectural Perspective
A. Tzanakaki, M. Anastasopoulos, D. Simeonidou, I. Berberana, D. Syrivelis, T. Korakis, P. Flegkas, D. Camps Mur, I. Demirkol, J. Gutierrez Teran, E. Grass, Q. Wei, E. Pateromichelakis, A. Fehske, M. Grieger, M. Eiselt, J. Bartelt, G. Lyberopoulos, E. Theodoropoulou
Proc. IEEE International Conference on Communications (ICC 2016), (2016)
DOI: 10.1109/ICCW.2016.7503764, (5G-XHaul)
(64) PSSS - Innovatives System zur Funkkommunikation für Industrie 4.0
L. Underberg, R. Kays, R. Kraemer, A.C. Wolf
Proc. VDE-Kongress 2016, (2016)
(65) Non-Cyclic Design Space Exploration for ASIPs — Compiler-Centered Microprocessor Design (CoMet)
R. Urban, H.T. Vierhaus, M. Schölzel, E. Altmann, H. Seelig
Journal of Circuits, Systems, and Computers (JCSC) 25(3), 1640012 (2016)
(DIAMANT)
The CoMet approach on designing application specific instruction set processors (ASIPs) is
targeting a non-cyclic design space exploration (DSE). The design process is driven by a step by step refinement of intermediate codes, known from compiler backends. In every step, the intermediate
code can be simulated and profiled. Based on that profiling information, it can be
further transformed to an optimized or refined intermediate code. The whole transformation
process is implemented in a GUI-based design tool, whose main component is a configurable
simulator for intermediate codes. It will be shown how the configurable intermediate code
simulator is used and how the intermediate code transformation and the VHDL generation of
the ASIP model will work in the CoMet tool.
(66) Application Study: RRAM for Low-Power Microcontrollers
F. Vater, M. Schölzel
Proc. 1st International Workshop on Emerging Memory Solutions (2016)
(DIAMANT)
The energy efficiency of today’s microcontrollers
is supported by the extensive usage of low-power mechanisms.
A full power-down requires in many cases a complex, and
maybe error prone, administration scheme, because data from
the volatile memory have to be stored in a flash based backup
memory. New types of non-volatile memory, e.g. in RRAM
technology, are faster and consumes a fraction of the energy
compared to flash technology. This paper evaluates power gating
for WSN with RRAM as back-up memory.
(67) A New Telerehabilitation System Based on Internet of Things
S. Vukicevic, Z. Stamenkovic, S. Murugesan, Z. Bogdanovic, B. Radenkovic
Facta Universitatis, Series: Electronics and Energetics 29(3), 395 (2016)
Internet of Things (IoT) applied in healthcare system has huge potential to improve patients' quality of life. Representing network of devices embedded with electronics and sensors, IoT enables constant monitoring of vital body functions, tracking of physical activities of a person and aides rehab physical therapy. Such an IoT-based system would allow standalone recovery process, minimizing need of dedicated medical personnel and could be used in both hospital and home conditions. In this paper, we present a telerehabilitation system that uses wearable muscle sensor and Microsoft Kinect to create interactive personalized physical therapy that can be carried out at home. Early experiments and results of pilot implementation validate the feasibility and effectiveness of the proposed IoT-enabled telerehabilitation system.
(68) Architektur mit reduzierter Komplexität zur Erkennung und Korrektur von transienten Fehlern in kombinatorischer und sequentieller Logik
S. Weidling, M. Krstic, V. Petrovic, E. Sogomonyan
Proc. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2016), (2016)
(69) Preparation of SCA Attacks: Successfully Decapsulating BGA Packages
Ch. Wittke, Z. Dyka, O. Skibitzki, P. Langendörfer
Proc. 9th International Conference on Security for Information Technology and Communications, (2016)
(70) Successfully Decapsulating BGA Packages: How To
Ch. Wittke, Z. Dyka, O. Skibitzki, P. Langendörfer
Proc. 24th Crypto-Day, 1 (2016)
(71) Sophisticated Placement of Flip-flops to Protect Cryptographic ASICs against Laser FI and Localized EMA
Ch. Wittke, Z. Dyka, P. Langendörfer
Proc. 25th Crypto-Day, (2016)
(72) Comparison of EM Probes using SEMA of an ECC Design
Ch. Wittke, Z. Dyka, P. Langendörfer
Proc. 8th IFIP International Conference on New Technologies, Mobility and Security (NTMS 2016), (2016)
(73) Probe Comparison for EM-Measurement in Terms of Side Channel Analysis
Ch. Wittke, Z. Dyka, P. Langendörfer
Proc. 23rd Crypto-Day, 8 (2016)
(74) An Early Stage Design Flow for Switching Noise Attenuation
St. Zeidler, X. Fan, O. Schrape, M. Krstic
Journal of Circuits, Systems, and Computers (JCSC) 25(3), 1640022 (2016)
(IC-NAO)
In the design of highly complex integrated circuits (ICs), switching noise is a raising problem. To handle this, current shaping techniques are applied to reduce current peaks causing ground bounce and voltage drops. Such techniques distribute the switching activity by adding phases and/or jitter to the clock of different domains. However, they are usually performed at later phases of the design process, i.e., in the chip layout. In this phase, the timing margins of the logic paths are typically fixed, which limits the clock phases that can be introduced between the domains. In this paper, we present a novel design preconditioning flow, which addresses the optimization of power noise characteristics of a design already at the frontend level. This allows early RTL-level design modifications, e.g., clock inversion or pipeline stage insertion, which potentially facilitate noise mitigation or enhance clock skewing in later design stages.
