Publikationen 2022

Script list Publications

(1) BiCMOS IQ Transceiver with Array-on-Chip for D-Band Joint Radar-Communication Applications
W. Ahmad, M. Kucharski, H.J. Ng, D. Kissinger
Proc. 22nd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2022), 78 (2022)
(Benchmarking Circuits/Radar Systems)

(2) Miniaturized and Process-Tolerant Ku-Band Power Dividers using GaN on SiC
V. Ertürk, B. Sütbas, E. Ozbay, A. Atalar
Proc. 51st European Microwave Conference (EuMC 2021), 370 (2022)

(3) 55% Fractional-Bandwidth Doherty Power Amplifier in 130-nm SiGe for 5G mm-Wave Applications
A. Franzese, N. Maletic, M.H. Eissa, M.-D. Wei, R. Negra, A. Malignaggi
Proc. European Microwave Integrated Circuits Conference (EuMIC 2021), 273 (2022)

(4) An N-Way Single-Inductor High-Pass Power Divider for 5G Applications
A. Franzese, R. Negra, A. Malignaggi
IEEE Solid-State Circuits Letters 5, 5 (2022)

(5) Performance Comparison of V-Band T/R Amplifier Module in SiGe Technology using Aluminium and Copper Back-End of Line
A. Gadallah, M.H. Eissa, D. Kissinger, A. Malignaggi
Proc. IEEE Radio and Wireless Week (RWW 2022), (2022)

(6) Wideband, Compact and Efficient Frequency Quadrupler in 130 nm SiGe BiCMOS Technology for D-Band Applications
R. Hasan, H.J. Ng, M.H. Eissa, D. Kissinger
Proc. IEEE Radio and Wireless Week (RWW 2022), (2022)
(T-KOS)

(7) A Novel Architecture for Low-Jitter Multi-GHz Frequency Synthesis
F. Herzel, T. Mausolf, G. Fischer
Frequenz: Journal of RF-Engineering and Telecommunications (2022)
A phase-locked loop (PLL) cascade driven by a crystal oscillator and a free running dielectric resonator oscillator (DRO) is proposed. For minimizing phase noise, spurious tones and jitter, a programmable PLL1 in the lower GHz range is used to drive a millimeter-wave (mmW) PLL2 with a fixed frequency multiplication factor. The phase noise analysis results in two optimum bandwidths of the two PLLs for the lowest output jitter of the cascade. Phase noise and spurious tones (spurs) in PLL1 are further reduced by dividing the output frequency of PLL1 and up-converting it by means of a single-sideband (SSB) mixer driven by the DRO. By including the SSB mixer in the feedback loop of PLL1 manual tuning of the DRO is avoided, and a low-noise free running DRO can be employed. An exemplary design in SiGe BiCMOS technology is presented.
 

(8) A Robust Programmable Static Frequency Divider in Low-Voltage Emitter-Coupled Logic
F. Herzel, T. Mausolf, G. Fischer
Proc. 14th German Microwave Conference (GEMIC 2022), 57 (2022)

(9) Low-Power Ka- and V-Band Miller Compensated Amplifiers in 130-nm SiGe BiCMOS Technology
B. Sütbas, H.J. Ng, J. Wessel, A. Koelpin, G. Kahmen
Proc. 16th European Microwave Integrated Circuits Conference (EuMIC 2021), 71 (2022)
(iCampus)

(10) A V-band Low-Power and Compact Down-Conversion Mixer with Low LO Power in 130-nm SiGe BiCMOS Technology
B. Sütbas, H.J. Ng, J. Wessel, A. Koelpin, G. Kahmen
Proc. 16th European Microwave Integrated Circuits Conference (EuMIC 2021), 96 (2022)
(iCampus)

Die Website ist für moderne Browser konzipiert. Bitte verwenden Sie einen aktuellen Browser.