Publications 2018

(1) A Test Platform for the Noise Characterization of SiGe Microbolometer ROICs
S. Abbasi, A. Shafique, O. Ceylan, C. Baristiran Kaynak, M. Kaynak, Y. Gurbuz
IEEE Sensors Journal 18(15), 6217 (2018)
(IHP-Sabanci Joint Lab)
This paper introduces an in-circuit performance evaluation system for SiGe microbolometer readout integrated circuits (ROICs) that can characterize the overall system noise performance by emulating microbolometers with MOSFETs biased in the triode region. Specifically, the proposed test platform is designed for the testing of imagers with high resistance SiGe microbolometers. The architecture of the ROIC is based on a bridge with active and reference bolometer pixels with a capacitive transimpedance amplifier input stage and column parallel integration with serial readout. Noise measurements along with simulated resistance curves of the dummy detectors are reported. The prototype with 17-μm pixel pitch has been designed and fabricated in a 0.25-μm SiGe BiCMOS process.

(2) 0.3-THz SiGe-Based High-Efficiency Push–Push VCOs with >1-mW Peak Output Power Employing Common-Mode Impedance Enhancement
F. Ahmed, M. Furqan, B. Heinemann, A. Stelzer
IEEE Transactions on Microwave Theory and Techniques 66(3), 1384 (2018)
(Dotseven)

(3) A Linear Differential Transimpedance Amplifier for 100 Gb/s Integrated Coherent Optical Fiber Receivers
A. Awny, R. Nagulapalli, M. Kroh, J. Hoffmann, P. Runge, D. Micusik, G. Fischer, A.C. Ulusoy, M. Ko, D. Kissinger
IEEE Transactions on Microwave Theory and Techniques 66(2), 973 (2018)
This paper presents the design and measurements of a 32-Gb/s differential-input differential-output transimpedance amplifier (TIA) employed in dual polarization integrated coherent receivers for 100-Gb Ethernet. A circuit technique is shown that uses a replica TIA to tabilize the operating point of the two shunt-feedback input stages as well as to cancel the dc part of the two complementary input currents and balances their offset. The TIA can be operated in two modes, an automatic gain control mode to retain a good total harmonic distortion (THD) over a wide dynamic range and a manual gain control mode. Electrical as well as optical-electrical characterization of the TIA are presented. It achieves a maximum differential transimpedance of 74 dB, 33 GHz of 3-dB bandwidth, 12.2 pA/√Hz of average input-referred noise current density with the photodiode, 900 mVpp of maximum differential output swing, less than 1% of THD for 600 mVpp differential output swing, and 500 μApp differential input current. The linearity of the TIA is furthermore demonstrated with PAM4 measurements at 25 Gbaud. The dual TIA chip is fabricated in a 0.13-μm SiGe:C BiCMOS technology, dissipates 436 mW of power and occupies 2 mm2 of area.

(4) Scaling Optical Interconnects Beyond 400 Gb/s
P. Bakopoulos, P. Ma, D. Tsiokos, H. Hettrich, F. Eltes, C. Uhl, St. Lischke, D. Petousi, S. Abel, R. Schmid, G. Dabos, D. Kalavrouziotis, A. Manolis, A. Rubinstein, D. Moor, L. Zimmermann, N. Pleros, M. Möller, J. Fompeyrine, J. Leuthold, E. Mentovich
Proc. European Conference on Optical Communication (ECOC 2018), (2018)
DOI: 10.1109/ECOC.2018.8535463

(5) Aspects of Library Characterization of Digital Standard Cells with Complex Circuit Topology
A. Balashov, O. Schrape
Proc. CDNLive Cadence User Conference 2018, (2018)

(6) High Performance Thermistor Based on Si_(1-x)Ge_x/Si Multi Quantum Wells
C. Baristiran Kaynak, Y. Yamamoto, A. Göritz, F. Korndörfer, P. Zaumseil, P. Kulse, K. Schulz, M. Wietstruck, A. Shafique, Y. Gurbuz, M. Kaynak
IEEE Electron Device Letters 39(5), 753 (2018)
(IHP-Sabanci Joint Lab)
This letter represents a prototype of an intrinsic thermistor based on silicon-germanium/silicon (Si_1−xGe_x/Si) multi quantum wells with varying Ge concentration in SiGe wells. Experimental results of the thermistor prototype are provided in terms of temperature coefficient of resistance (TCR) and noise constant (K1/f). The prototype with 50% Ge in SiGe wells exhibited an outstanding TCR of −5.5 %/K accompanied by a K_1/f of 5.8 × 10⁻¹³ for 25 μm × 25 μm and 3.4 × 10⁻¹⁵ for 200 μm × 200 μm pixel size, showing the concurrent achievement of a very high TCR and a low 1/f noise performance.

(7) Si_(1-x)Ge_x/Si MQW Based Uncooled Microbolometer Development and Integration into 130 nm BiCMOS Technology
C. Baristiran Kaynak, Y. Yamamoto, A. Göritz, F. Korndörfer, P. Zaumseil, P. Kulse, K. Schulz, M. Fraschke, St. Marschmeyer, T. Wolansky, M. Wietstruck, A. Shafique, Y. Gurbuz, M. Kaynak
ECS Transactions 86(7), 373 (2018)
(IHP-Sabanci Joint Lab)

(8) Pixel Resistance Optimization of a Si_0.5Ge_0.5/Si MQWs Thermistor Based on In-Situ B Doping for Microbolometer Applications
C. Baristiran Kaynak, Y. Yamamoto, A. Göritz, F. Korndörfer, P. Zaumseil, P. Kulse, K. Schulz, M. Wietstruck, I. Costina, A. Shafique, Y. Gurbuz, M. Kaynak
Proc. SPIE Defense+Commercial Sensing 10624, 10624E1 (2018)
(IHP-Sabanci Joint Lab)

(9) Effect of the Number of Quantum Wells on SiGe/Si Based Thermistor Performance
C. Baristiran Kaynak, Y. Yamamoto, A. Göritz, F. Korndörfer, M. Wietstruck, A. Shafique, Y. Gurbuz, M. Kaynak
Proc. 50^th International Conference on Solid State Devices and Materials (SSDM 2018), 1225 (2018)
(IHP-Sabanci Joint Lab)

(10) Single Crystalline SiGe/Si MQW Thermistor for Uncooled Microbolometers
C. Baristiran Kaynak, Y. Yamamoto, A. Göritz, P. Zaumseil, P. Kulse, K. Schulz, M. Wietstruck, A. Shafique, Y. Gurbuz, M. Kaynak
Proc. 1^st Joint Conference International SiGe Technology and Device Meeting and International Conference on Silicon Epitaxy and Heterostructures (ISTDM/ICSI 2018), 73 (2018)
(IHP-Sabanci Joint Lab)

(11) SiGe Graded HBT Analysis by DSIMS, Spectroscopic Ellipsometry and X-Ray Diffractometry
F. Bärwolf, O. Fursenko, P. Zaumseil, Y. Yamamoto
Proc. 1^st Joint Conference International SiGe Technology and Device Meeting and International Conference on Silicon Epitaxy and Heterostructures (ISTDM/ICSI 2018), 287 (2018)

(12) Dynamic SIMS, Spectroscopic Ellipsometry and X-Ray Diffractometry Analysis of SiGe HBTs with Ge Grading
F. Bärwolf, O. Fursenko, P. Zaumseil, Y. Yamamoto
Semiconductor Science and Technology 34(1), 014005 (2018)
In this paper, SiGe heterojunction bipolar transistors (HBTs) with Ge concentrations up to 40 atomic percent (at%) and different slopes of Ge gradients are characterized by comparing dynamic secondary ion mass spectrometry (D-SIMS) and multi-angle spectroscopic ellipsometry (SE). X-ray diffractometry (XRD) was used as reference. D-SIMS results show that sputter rate and Ge content calibration have major impact on depth profile measurements of HBTs with graded SiGe. Strained and relaxed SiGe show differences in Ge content calibration and no difference in sputter rate calibration. Jiang’s protocol was used for Ge content calibration and proven to be valid up to ∼50 at% Ge. SE with a combination of 3 angles of incidence (AOIs) (59, 65, 71°) in comparison with the single AOI (71°) realized in industrial setup for semiconductor manufacturing environment was analyzed to find a more stable solution for revealing the thickness of plateau and gradient parts of SiGe base. SE with 71° AOI and rotating compensator is the best choice for in-line HBT with Ge grading characterization. The determination of gradient shape continues to be a challenging task for SE, due to high parameter correlations and the need to use some fixed parameters within the fitting procedure. D-SIMS remains the favorite for graded profile determination. Results of D-SIMS and SE with fixed parameters are in good agreement with XRD for HBTs with Ge grading.

(13) Substrate Integrated Waveguides for mm-wave Functionalized Silicon Interposer
M. Bertrand, E. Pistono, G. Acri, D. Kaddour, F. Podevin, V. Puyal, S. Tolunay Wipf, Ch. Wipf, M. Wietstruck, M. Kaynak, P. Ferrari
Proc. IEEE MTT-S International Microwave Symposium (IMS 2018), 875 (2018)
This paper presents D-band mm-wave SIWs, which are embedded in a high-resistivity silicon interposer. Thanks to the interposer thickness equal to 70 μm, high-performance SIW were obtained, with measured attenuation constant between 0.4 and 0.6 dB/mm from 110 GHz to 170 GHz. These first results pave the way for the realization of high performance passive circuits and antennas embedded in the interposer. Also, by using a fully shielded waveguide highly insensitive to adjacent wave-guiding and radiating structures, this topology provides signifi-cant advantages for packaging solutions at mm-wave frequencies. Such a functionalized interposer could offer lower cost, higher electrical performance as compared to standard CMOS technol-ogies.

(14) Characterization of Bandgap Engineering on Operative Transistor Devices by Spectral Photon Emission
A. Beyreuther, I. Vogt, T. Nakamura, G.G. Fischer, B. Motamedi, C. Boit
Proc. IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2018), (2018)

(15) A D-band SPDT Switch Utilizing Reverse-Saturated SiGe HBTs for Dicke-Radiometers
B. Cetindogan, B. Ustundag, E. Turkmen, M. Wietstruck, M. Kaynak, Y. Gurbuz
Proc. 11^th German Microwave Conference (GeMiC 2018), 47 (2018)
(IHP-Sabanci Joint Lab)
This paper presents a low insertion loss and high isolation D-band (110-170 GHz) single-pole double-throw (SPDT) switch utilizing reverse-saturated SiGe HBTs for Dicke-radiometers. The SPDT switch design is based on the quarter-wave shunt switch topology and implemented in a commercial 0.13-um SiGe BiCMOS technology which features SiGe HBTs with ft/fmax of 300/500 GHz. Measurement results of the implemented SPDT switch show a minimum inserion loss of 2.6 dB at 125 GHz and a maximum isolation of 30 dB at 151 GHz while the measured input ant output return loss of is greater than 10 dB across 110-170 GHz. Total power consumption of the SPDT switch is 5.3 mW while draining 5.6 mA from 0.95 V DC supply. Overall chip size is only 0.5x0.32=0.16 mm2, excluding the RF and DC pads.

(16) A Modular Phased Array Transceiver with RF-MEMS SPDT Switches in a 0.25 um SiGe BiCMOS Technology
T. Chaloun, F. Tabarani, S. Tolunay Wipf, M. Kaynak, H. Schumacher, W. Menzel
Proc. 12^th European Conference on Antennas and Propagation (EuCAP 2018), (2018)
(Flexwin)
An highly-integrated active reflectarray transceiver
enhanced with fully monolithically integrated RF-MEMS SPDT
switches is presented. The system operates at Ka band and
follows a 3-D manifold concept incorporating wide angle scanning
antenna elements, RF interconnects, mixed-signal MMICs in
a flexible and scalable manner. Apart from this, the thermal
management of the system, as well as the robustness and
reliability of RF-MEMS SPDT switches are discussed. To verify
the technological methodology, a phased array demonstrator with
144 elements has been realized demonstrating excellent scanning
performance up to 60degree from boresight.

(17) SiGe BiCMOS Current Status and Future Trends in Europe
P. Chevalier, W. Liebl, H. Rücker, A. Gauthier, D. Manger, B. Heinemann, G. Avenier, J. Böck
Proc. IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS 2018), 64 (2018)
(Taranto)

(18) Si Electronic-Photonic Integrated Circuits for Realization of Single-Chip Optical Single-Sideband Modulators
W.-Y. Choi, B.-M. Yu, J.-M. Lee, Ch. Mai, St. Lischke, L. Zimmermann
Proc. 40^th Progress In Electromagnetics Research Symposium (PIERS 2018), 721 (2018)

(19) Modeling Depletion-Type Si Ring Modulators
W.-Y. Choi, M. Kim, M. Shin, B. Yu, Ch. Mai, St. Lischke, L. Zimmermann
Proc. 23^rd OptoElectronics and Communications Conference (OECC 2018), 3D2-1 (2018)

(20) Electrical Characterization of N-Doped SiGeSn Diodes with High Sn Content
C.J. Clausen, I.A. Fischer, D. Weißhaupt, M. Oehme, F. Bärwolf, B. Tillack, G. Colston, M. Myronov, J. Schulze
Semiconductor Science and Technology 33, 124017 (2018)
Diodes incorporating undoped and Sb-doped SixGe1-x-ySny layers grown by molecular beam epitaxy with different alloy compositions and lattice-matched to Ge were fabricated and characterized experimentally. We discuss material as well as electrical device characterization and investigate different contact metallizations (Ni and Al). In particular, we investigate the formation of Ni(SixGe1-x-ySny) on the doped Sb-doped SixGe1-x-ySny layers via annealing based on material characterization and measurements of specific contact resistivities. Our results can serve as a starting point for the investigation of SixGe1-x-ySny layers with high Si and Sn content as cladding material in optoelectronic devices such as lasers and light emitting diodes.

(21) Dual-Polarization Wavelength Conversion of 16-QAM Signals in a Single Silicon Waveguide with Lateral p-i-n Diode
F. Da Ros, E. Liebig, A. Gajda, E.P. da Silva, A. Peczek, P.D. Girouard, A. Mai, K. Petermann, L. Zimmermann, M. Galili, L.K. Oxenløwe
Photonics Research 6(5), B23 (2018)
(SOPA ZI 1283/3-1)
A polarization-diversity loop with a silicon waveguide with lateral p-i-n diode as nonlinear medium is used to realize polarization insensitive four-wave mixing (FWM). Wavelength conversion of seven dual-polarization16-quadrature amplitude modulation (QAM) signals at 16 GBd is demonstrated with an optical signal-to-noise ratio (OSNR) penalty below 0.7 dB. High-quality converted signals are generated thanks to the low polarization dependence (less then 0.5 dB) and the high conversion efficiency (CE) achievable. The strong Kerr nonlinearity in silicon and the decrease of detrimental free-carrier absorption due to the reverse-biased p-i-n diode are key in ensuring the high CE levels.

(22) Nonlinearity Compensation for Dual-Polarization Signals using Optical Phase Conjugation in a Silicon Waveguide
F. Da Ros, E.P. da Silva, A. Gajda, P.M. Kaminski, V. Cristofori, A. Peczek, A. Mai, K. Petermann, L. Zimmermann, L.K. Oxenløwe, M. Galili
Proc. Conference on Lasers and Electro-Optics® (CLEO 2018), STu4C.1 (2018)
(SOPA ZI 1283/3-1)
Improvements in signal performance (1.2 dB in SNR) and transmission reach (16 %) are demonstrated for dual-polarization WDM 16-QAM signals through nonlinearity compensation by optical phase conjugation in silicon waveguide with a lateral p-i-n diode.

(23) Modeling of Materials for Silicon-Compatible Microelectronics
J. Dabrowski, G. Kissinger, G. Lippert, G. Lupina, M. Lukosius, P. Sana, T. Schroeder
Proc. NIC Symposium (NiC Series) 49, 239 (2018)
(Graphen)
Ab initio density functional theory (DFT) is an established method to model the behavior of materials at the atomic scale. At the IHP, we use it to investigate materials systems that are of interest to the most popular and cost-efficient technology, by which electronics is made today: the silicon technology. Here we report on the results obtained for various materials: (a) for strictly 2D atomic sheets (graphene), (b) for heteroepitaxial layers (oxides and nitrides), their surfaces, and the interfaces between these films, and (c) for bulk crystals (defects in silicon). The graphene sheets are intended as components of chemical sensors, optical modulators, and high-speed and high-power transistors. The chemical reactions and diffusion processes governing the nucleation and growth of graphene on perfect (flat and stepped) and defected surfaces of germanium films were simulated, and the mechanisms responsible for the observed growth modes were elucidated. The Sc oxide and nitride films constitute the topmost part of a heterostructure on which GaN diodes, lasers, and high-power transistors can be assembled. The simulations provided insight into the intermixing of oxygen and nitrogen. The substrate on which all these films and other device structures are grown, is crystalline silicon. For numerous application it is critical that the substrate getters (collects and binds) the impurities that are unintentionally introduced by the technological process. The formation of oxygen precipitates used as the gettering centers is associated with the presence of missing atoms (vacancies) in the Si bulk. We studied the process of vacancy clustering and oxidation, we extrapolated the clustering results to infinite separation between the defects, and we discussed the implications also for the interpretation of deep level transient spectroscopy (DLTS) or for the strategy to perform numerically expensive defect calculations (as done with hybrid potentials), among others.

(24) Modeling of Materials for Silicon-Compatible Microelectronics
J. Dabrowski, G. Kissinger, G. Lippert, G. Lupina, M. Lukosius, P. Sana, T. Schroeder
Proc. NIC Symposium (NiC Series) 49, 239 (2018)
(Siltronic Project)
Ab initio density functional theory (DFT) is an established method to model the behavior of materials at the atomic scale. At the IHP, we use it to investigate materials systems that are of interest to the most popular and cost-efficient technology, by which electronics is made today: the silicon technology. Here we report on the results obtained for various materials: (a) for strictly 2D atomic sheets (graphene), (b) for heteroepitaxial layers (oxides and nitrides), their surfaces, and the interfaces between these films, and (c) for bulk crystals (defects in silicon). The graphene sheets are intended as components of chemical sensors, optical modulators, and high-speed and high-power transistors. The chemical reactions and diffusion processes governing the nucleation and growth of graphene on perfect (flat and stepped) and defected surfaces of germanium films were simulated, and the mechanisms responsible for the observed growth modes were elucidated. The Sc oxide and nitride films constitute the topmost part of a heterostructure on which GaN diodes, lasers, and high-power transistors can be assembled. The simulations provided insight into the intermixing of oxygen and nitrogen. The substrate on which all these films and other device structures are grown, is crystalline silicon. For numerous application it is critical that the substrate getters (collects and binds) the impurities that are unintentionally introduced by the technological process. The formation of oxygen precipitates used as the gettering centers is associated with the presence of missing atoms (vacancies) in the Si bulk. We studied the process of vacancy clustering and oxidation, we extrapolated the clustering results to infinite separation between the defects, and we discussed the implications also for the interpretation of deep level transient spectroscopy (DLTS) or for the strategy to perform numerically expensive defect calculations (as done with hybrid potentials), among others.

(25) Modeling of Materials for Silicon-Compatible Microelectronics
J. Dabrowski, G. Kissinger, G. Lippert, G. Lupina, M. Lukosius, P. Sana, T. Schroeder
Proc. NIC Symposium (NiC Series) 49, 239 (2018)
(Future Silicon Wafers)
Ab initio density functional theory (DFT) is an established method to model the behavior of materials at the atomic scale. At the IHP, we use it to investigate materials systems that are of interest to the most popular and cost-efficient technology, by which electronics is made today: the silicon technology. Here we report on the results obtained for various materials: (a) for strictly 2D atomic sheets (graphene), (b) for heteroepitaxial layers (oxides and nitrides), their surfaces, and the interfaces between these films, and (c) for bulk crystals (defects in silicon). The graphene sheets are intended as components of chemical sensors, optical modulators, and high-speed and high-power transistors. The chemical reactions and diffusion processes governing the nucleation and growth of graphene on perfect (flat and stepped) and defected surfaces of germanium films were simulated, and the mechanisms responsible for the observed growth modes were elucidated. The Sc oxide and nitride films constitute the topmost part of a heterostructure on which GaN diodes, lasers, and high-power transistors can be assembled. The simulations provided insight into the intermixing of oxygen and nitrogen. The substrate on which all these films and other device structures are grown, is crystalline silicon. For numerous application it is critical that the substrate getters (collects and binds) the impurities that are unintentionally introduced by the technological process. The formation of oxygen precipitates used as the gettering centers is associated with the presence of missing atoms (vacancies) in the Si bulk. We studied the process of vacancy clustering and oxidation, we extrapolated the clustering results to infinite separation between the defects, and we discussed the implications also for the interpretation of deep level transient spectroscopy (DLTS) or for the strategy to perform numerically expensive defect calculations (as done with hybrid potentials), among others.

(26) Automation of Electro-Thermal Simulations Based on Thermal Conductivity Optimization
A. Datsuk, M. Kaynak, T. Krupkina
Proc. 19^th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2018), (2018)
(Design Kit)
Abstract — In this paper, an automated extraction method to optimize the thermal conductivity of silicon is proposed. The approach is based on the electrical and thermal co-simulation of SiGe HBTs. The bisection method is used to optimize silicon conductivity values. The optimized material stack is embedded in the process design kit and allows designers to perform computing of the full-chip temperature profile and get accurate simulation results. The overall investigation is confirmed by measurements performed on bulk-silicon HBTs. Comparison between the simulations and the measurements shows that the maximum mismatch of %5 is achieved for the RTH values.

(27) Electro-Thermal Simulation of a Bandgap
A. Datsuk, A. Balashov, V. Timoshenkov, T. Krupkina
Proc. 8^th All-Russia Science & Technology Conference "Problems of Advanced Micro- and Nanoelectronic Systems Development" (MES 2018), 189 (2018)
(Design Kit)
Abstract – In this paper we researched an influence of device thermal coupling on bandgap characteristics. The straightforward RFIC / MMIC circuits, the foundry provided design-kits (DKs) together with the device models HICUM, MEXTRAM and VIBC are used. The provided device models mostly include the self-heating parameters. However, self-heating parameters are modeled only for the intrinsic device but not for the surrounding devices. Furthermore, layout and packaging issues, which have a strong influence on the thermal performance of the ICs are not considered by the foundry provided device models. This causes inaccurate simulation results of aforementioned bandgap circuit in highly integrated designs with several power devices in a close proximity. The proposed approach is based on the electrical and thermal co-simulation and optimized material stack. Co-simulation utilizes power dissipation data from the circuit simulator and passes the value to the thermal solver. The solver extracts device information and connectivity from layout and calculates device temperature based on the current power dissipation value. The temperature value is transferred back to circuit simulator to calculate new power dissipation. This way, the thermal solver iterates with the circuit until a converged solution is reached. The process layer stack and all the required information are embedded into the foundry provided process design kit (PDK); hence allow the designer performing the electro-thermal simulations under the same design environment. The electro-thermal simulation shows significant output voltage change of the bandgap at high temperatures. Using the proposed flow, the circuit designers are capable to simulate the temperature affects and be aware of them before the tape out thus they reduce the malfunctioning risk of ICs due to unexpected thermal issues.

(28) Graphene/Silicon Schottky Diodes for Photodetection
A. Di Bartolomeo, G. Luongo, L. Iemmo, F. Giubileo, G. Niu, G. Lupina, T. Schroeder
Proc. 12^th IEEE Nanotechnology Materials and Devices Conference (NMDC 2017), 45 (2018)

(29) Record High Pockels Coefficient in PIC-Compatible BaTiO3/Si Photonic Devices
F. Eltes, J.E. Ortmann, D. Urbonas, D. Caimi, L. Czornomaz, Ch. Mai, L. Zimmermann, J. Fompeyrine, S. Abel
Proc. European Conference on Optical Communication (ECOC 2018), (2018)
(SITOGA)

(30) Record High Pockels Coefficient in PIC-Compatible BaTiO3/Si Photonic Devices
F. Eltes, J.E. Ortmann, D. Urbonas, D. Caimi, L. Czornomaz, Ch. Mai, L. Zimmermann, J. Fompeyrine, S. Abel
Proc. European Conference on Optical Communication (ECOC 2018), (2018)
(PHRESCO)

(31) Silicon Waveguide with Lateral p-i-n Diode for Nonlinearity Compensation by On-Chip Optical Phase Conjugation
A. Gajda, F. Da Ros, A. Peczek, E. Liebig, M. Galili, L. Zimmermann, K. Petermann
Proc. Optical Fiber Communications Conference and Exposition (OFC 2018), W3E.4 (2018)
(SOPA ZI 1283/3-1)
A 1-dB Q-factor improvement through optical phase conjugation in a silicon waveguide with a lateral p-i-n diode enables BER

(32) Monolithically Integrated Si Photonics Transmitters in 0.25 µm BiCMOS Platform for High-Speed Optical Communications
I. Garcia Lopez, R. Pedro, D. Petousi, St. Lischke, D. Knoll, M. Kroh, L. Zimmermann, M. Ko, A.C. Ulusoy, D. Kissinger
Proc. IEEE MTT-S International Microwave Symposium (IMS 2018), 1312 (2018)

(33) Comparison of Segmented and Traveling-Wave Electro-Optical Transmitters Based on Silicon Photonics Mach-Zehnder Modulators
A. Giuglea, G. Belfiore, M. Khafaji, R. Henker, D. Petousi, G. Winzer, L. Zimmermann, F. Ellinger
Proc. International Conference on Photonics in Switching and Computing (PSC 2018), (2018)
DOI: 10.1109/PS.2018.8751239

(34) Prolonged Corrosion Stability of a Microchip Sensor Implant during In Vivo Exposure
P. Glogener, M. Krause, J. Katzer, M.A. Schubert, M. Birkholz, O. Bellmann, C. Kröger-Koch, H.M. Hammon, C. Metges, C. Welsch, R. Ruff, K.P. Hoffmann
Biosensors (MDPI) 8(1), 13 (2018)
(Bioelectronics)
A microelectronic biosensor was subjected to in vivo exposure by implanting it in the vicinity of m. trapezii (Trapezius muscle) from cattle. The implant is intended for the continuous monitoring of glucose levels, and the study aimed at evaluating the biostability of exposed semiconductor surfaces. The sensor chip was a microelectromechanical system (MEMS) prepared using 0.25 µm complementary metal–oxide–semiconductor CMOS/BiCMOS technology. Sensing is based on the principle of affinity viscometry with a sensoric assay, which is separated by a semipermeable membrane from the tissue. Outer dimensions of the otherwise hermetically sealed biosensor system were 39 × 49 × 16 mm. The test system was implanted into cattle in a subcutaneous position without running it. After 17 months, the device was explanted and analyzed by comparing it with unexposed chips and systems. Investigations focused on the MEMS chip using SEM, TEM, and elemental analysis by EDX mapping. The sensor chip turned out to be uncorroded and no diminishing of the topmost passivation layer could be determined, which contrasts remarkably with previous results on CMOS biosensors. The negligible corrosive attack is understood to be a side effect of the semipermeable membrane separating the assay from the tissue. It is concluded that the separation has enabled a prolonged biostability of the chip, which will be of relevance for biosensor implants in general.

(35) Impact of the Precursor Chemistry and Process Conditions on the Cell-to-Cell Variability in 1T-1R based HfO₂ RRAM Devices
A. Grossi, E. Perez, C. Zambelli, P. Olivo, E. Miranda, R. Roelofs, J. Woodruff, P. Raisanen, W. Li, M. Givens, I. Costina, M.A. Schubert, Ch. Wenger
Scientific Reports 8, 11160 (2018)
(Panache)
The Resistive RAM (RRAM) technology is currently in a level of maturity that calls for its integration into CMOS compatible memory arrays. This CMOS integration requires a perfect understanding of the cells performance and reliability in relation to the deposition processes used for their manufacturing. In this paper, the impact of the precursor chemistries and process conditions on the performance of HfO₂ based memristive cells is studied. An extensive characterization of HfO₂ based 1T1R cells, a comparison of the cell-to-cell variability, and reliability study is performed. The cells’ behaviors during forming, set, and reset operations are monitored in order to relate their features to conductive filament properties and process-induced variability of the switching parameters. The modeling of the high resistance state (HRS) is performed by applying the Quantum-Point Contact model to assess the link between thedeposition condition and the precursor chemistry with the resulting physical cells characteristics.

(36) A High-Speed QPSK/16-QAM 1-m Wireless Link with a Tunable 220–260 GHz LO Carrier in SiGe HBT Technology
J. Grzyb, P.R. Vazquez, B. Heinemann, U.R. Pfeiffer
Proc. 43^rd International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz 2018), (2018)
DOI: 10.1109/IRMMW-THz.2018.8510465

(37) Performance Evaluation of a 220-260 GHz LO Tunable BPSK/QPSK Wireless Link in SiGe HBT Technology
J. Grzyb, P. Rodriquez Vazquez, N. Sarmah, B. Heinemann, U.R. Pfeiffer
Proc. 48^th European Microwave Conference (EuMC 2018), 1397 (2018)
(Dotseven)

(38) 0.13μm SiGe BiCMOS W-Band Low-Noise Amplifier for Passive Imaging Systems
B. Gungor, E. Turkmen, M. Yazici, M. Kaynak, Y. Gurbuz
18^th Mediterranean Microwave Symposium (MMS 2018), 206 (2018)
DOI: 10.1109/MMS.2018.8612121

(39) A 128-Pixel System-on-a-Chip for Real-Time Super-Resolution Terahertz Near-Field Imaging
P. Hillger, R. Jain, J. Grzyb, W. Förster, B. Heinemann, G. MacGrogan, P. Mounaix, T. Zimmer, U.R. Pfeiffer
IEEE Journal of Solid-State Circuits 53(12), 3599 (2018)
DOI: 10.1109/JSSC.2018.2878817
This paper presents a fully integrated system-on-achip for real-time terahertz super-resolution near-field imaging. The chip consists of 128 sensing pixels with individual crossbridged double 3-D split-ring resonators arranged in a 3.2 mm long 2 × 64 1-D array. It is implemented in 0.13-μm SiGe bipolar complementary metal-oxide-semiconductor technology and operated at around 550 GHz. All the functions, including sensor illumination, near-field sensing, and detection, are co-integrated with a readout integrated circuit for real-time image acquisition. The pixels exhibit a permittivity-based imaging contrast with a worst case estimated relative permittivity uncertainty of 0.33 and 10-12-μm spatial resolution. The sensor illumination is provided with on-chip oscillators feeding four-way equal power divider networks to enable an effective pixel pitch of 25 μm and a dense fill factor of 48% for the 1-D sensing area. The oscillators are equipped with electronic chopping to avoid 1/f-noise-related desensitization for the SiGe-heterojunction bipolar transistor power detectors integrated at each pixel. The chip features both an analog readout mode and a lock-in-amplifier-based digital readout mode. In the analog readout mode, the measured dynamic range (DR) is 63.8 dB for a 1-ms integration time at an external lock-in amplifier. The digital readout mode achieves a DR of 38.5 dB at 28 f/s. The chip consumes 37-104 mW of power and is packaged into a compact imaging module. This paper further demonstrates real-time acquisition of 2-D terahertz super-resolution images of a nickel mesh with 50-μm feature size, as well as a biometric human fingerprint.

(40) A 128-Pixel 0.56THz Sensing Array for Real-Time Near-Field Imaging in 0.13μm SiGe BiCMOS
P. Hillger, R. Jain, J. Grzyb, L. Mavarani, B. Heinemann, G. Mac Grogan, P. Mounaix, T. Zimmer, U. Pfeiffer
Proc. IEEE International Solid-State Circuits Conference (ISSCC 2018), 418 (2018)
(Dotseven)

(41) A Hetero-Integrated W-Band Transmitter Module in InP-on-BiCMOS Technology
M. Hossain, M.H. Eissa, M. Hrobak, D. Stoppel, N. Weimann, A. Malignaggi, A. Mai, D. Kissinger, W. Heinrich, V. Krozer
Proc. 48^th European Microwave Week (EuMW 2018), 97 (2018)
(SciFab)
This paper presents a W-band hetero-integrated transmitter module using InP-on-BiCMOS technology. It consists of a Phase Locked Loop (PLL) in 0.25 μm BiCMOS technology and a frequency multiplier followed by a double-balanced Gilbert mixer cell in 0.8 μm InP-HBT technology, which is integrated on top of the BiCMOS MMIC in a wafer-level BCB bonding process. The PLL operates from 45 GHz to 47 GHz and the module achieves a measured single sideband (SSB) power conversion loss of 20 dB and 22 dB at 88 GHz and 95 GHz, respectively, limited by the output power from the PLL source. The entire circuit consumes 434 mW DC power. The chip area of the module is 2.5x1.3 mm². To the knowledge of the authors, this is the first complex hetero-integrated module reported so far.

(42) High-Power Radiation at 1 THz in Silicon: A Fully Scalable Array Using a Multi-Functional Radiating Mesh Structure
Z. Hu, M. Kaynak, R. Han
IEEE Journal of Solid-State Circuits 53(5), 1313 (2018)
We introduce a highly scalable architecture of coherent harmonic oscillator array for high-power and narrow-beamwidth radiation in the mid-terahertz (THz) band. The array consists of horizontal and vertical slotlines (i.e., slot mesh) located at the boundaries between oscillator elements. Through such a structure, the following operations are achieved simultaneously: 1) maximum oscillation power at fundamental frequency f₀; 2) precise synchronization of the oscillation phase among elements; 3) cancellation of the radiation at f₀, 2 f₀, and 3 f₀; and 4) efficient radiation and power combining at λ4f₀. The resultant compact design fits into the optimal radiator pitch of 4 f₀ /2 (half wavelength) for the suppression of sidelobes, hence enabling implementation of high-density THz arrays. In particular, an array prototype of 42 coherent radiators (with 91 resonant antennas) at 1 THz is presented using the IHP S13G2 130-nm SiGe process. The chip occupies only 1-mm² area and consumes 1.1 W of dc power. The measured total radiated power and the effective isotropically radiated power are 80 μW and 13 dBm, respectively.

(43) The Effect of Surface Optimization on Post-Grinding Yield of 200 mm Wafer Level Packaging Applications
M. Inac, M. Wietstruck, A. Göritz, B. Cetindogan, C. Baristiran Kaynak, M. Lisker, A. Krüger, U. Saarow, P. Heinrich, T. Voss, K. Altin, M. Kaynak
Proc. Electronics System-Integration Technology Conference (ESTC 2018), 53 (2018)

(44) Scanning Microwave Microscopy of Buried CMOS Interconnect Lines with Nanometer Resolution
X. Jin, K. Xiong, R. Marstell, N.C. Strandwitz, J.C.M. Hwang, M. Farina, A. Göritz, M. Wietstruck, M. Kaynak
International Journal of Microwave and Wireless Technologies (IJMWT) 10, 556 (2018)
This paper reports scanning microwave microscopy of CMOS interconnect aluminum lines both bare and buried under oxide. In both cases, a spatial resolution of 190 ± 70 nm was achieved, which was comparable or better than what had been reported in the literature. With the lines immersed in water to simulate high-k dielectric, the signal-to-noise ratio degraded significantly, but the image remained as sharp as before, especially after averaging across a few adjacent scans. These results imply that scanning microwave microscopy can be a promising technique for non-destructive nano-characterization of both CMOS interconnects buried under oxide and live biological samples immersed in water.

(45) Demonstrating Horizontal Attacks using IHP’s Side Channel Analysis Tool
I. Kabin, D. Klann, Z. Dyka, A. Datsuk, P. Langendörfer
Proc. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2018), (2018)
(Total Resilience)

(46) Atomic Layer Deposited Solid Sources for Doping of High Aspect Ratio Semiconductor Structures
B. Kalkofen, M. Šilinskas, M. Lisker, E.P. Burte
Proc. 18^th International Workshop on Junction Technology (IWJT 2018), (2018)

(47) Atomic Layer Deposition of Oxide Films as Solid Sources for Doping of High Aspect Ratio Semiconductor Structures
B. Kalkofen, M. Silinskas, M. Lisker, E.P. Burte
Proc. 20^th Workshop on Dielectrics in Microelectronics (WODIM 2018), 93 (2018)
(DFG-DoGeALD)

(48) Atomic Layer Deposition of Phosphorus Oxide Films as Solid Sources for Doping of Semiconductor Structures
B. Kalkofen, B. Ahmed, S. Beljakowa, M. Lisker, Y.S. Kim, E.P. Burte
Proc. IEEE International Conference on Nanotechnology (IEEE NANO 2018), (2018)

(49) A Wideband (3–13 GHz) 7-Bit SiGe BiCMOS Step Attenuator with Improved Flatness
H. Kandis, M. Yazici, Y. Gurbuz, M. Kaynak
18^th Mediterranean Microwave Symposium (MMS 2018), 139 (2018)
DOI: 10.1109/MMS.2018.8612017

(50) Three-Dimensional Terahertz Tomography With Transistor-Based Signal Source and Detector Circuits Operating Near 300 GHz
J. Kim, D. Yoon, J. Yun, K. Song, M. Kaynak, B. Tillack, J.S. Rhie
IEEE Transactions on Terahertz Science and Technology 8(5), 482 (2018)
In this paper, three-dimensional (3-D) terahertz (THz) tomography was demonstrated with a signal source and imagers based on transistor circuits fabricatedwith standard semiconductor technologies. For the signal source, a 300-GHz oscillator based on InP HBT technology was employed. For detection, two types of imagers operating near 300GHz were employed, one direct and the other heterodyne, both realized with SiGe HBT technology. With a set of 2-D images taken from different angles, sinograms and tomograms were obtained, which led to a successful reconstruction of 3-D images of the target object based on the filtered back-projection algorithm. A systematic comparison was made for the direct imager and the heterodyne imager, for which the signal input power and the video bandwidth were varied for both imagers. The results revealed that the heterodyne imager shows a better sensitivity than the direct imager. However, a similar dynamic range of around 30 dB was achieved for both imagers because of a saturation observed for the heterodyne imager when the input power exceeds the threshold. The video bandwidth did not affect the image quality significantly for the bandwidth variation over four orders of magnitude for both imagers.

(51) A Large-Signal Equivalent Circuit for Depletion-Type Silicon Ring Modulators
M. Kim, M. Shin, M.-H. Kim, B.-M. Yu, Ch. Mai, St. Lischke, L. Zimmermann, W.-Y. Choi
Proc. Optical Fiber Communications Conference and Exposition (OFC 2018), Th2A.13 (2018)

(52) A Wavelength Stabilization Integrated Circuit for 25-Gb/s Si Micro-Ring Modulator
M.-H. Kim, L. Zimmermann, W.-Y. Choi
23^rd Opto-Electronics and Communications Conference (OECC 2018), (2018)
DOI: 10.1109/OECC.2018.8729989

(53) Oxygen in Silicon: End of the Story?
G. Kissinger, D. Kot, M.A. Schubert, J. Dabrowski, A. Sattler, T. Müller
ECS Transactions 86(10), 61 (2018)
(Future Silicon Wafers)
Oxygen in silicon is investigated since decades. Although, the goals of research and development in this field changed over the years it is and it will remain an ongoing topic which is mainly driven by defect and impurity control in crystal growth and device processing. Examples from our own published results about ab initio calculation for understanding of the initial stages of oxygen precipitation, investigation of the stoichiometry of oxygen precipitates, elucidation of the gettering mechanism of Cu at oxygen precipitates, and N-doping for the homogeneous oxygen precipitation during high temperature annealing in wafers optimized with respect to voids will be presented.

(54) On the Impact of Deposited Nitride Layers on Oxide Precipitation in Czochralski Silicon
G. Kissinger, D. Kot, T. Grabolla, T. Müller, A. Sattler
Proc. 8^th Forum on the Science and Technology of Silicon Materials 2018, 27 (2018)
(Future Silicon Wafers)
We investigated the influence of stress and in-diffused nitrogen on oxide precipitation after rapid thermal annealing (RTA). For this purpose, we used deposited nitride layers in order to focus more on the stress effects than on interface reactions during nitride formation. One-sided and double-sided nitride layers accompanied by simulation models helped to understand the behavior of intrinsic point defects, nitrogen, and strain. It was found that the presence of a nitride layer of any thickness, within the range, which we investigated, in direct contact with the silicon surface is sufficient to markedly change the precipitation behavior of interstitial oxygen after RTA at 1175 °C and 1250 °C. However, a 10 nm oxide between silicon substrate and nitride layer prevents any change of the BMD depth profile. Peaks of in-diffused nitrogen below the silicon surface lead to an enhanced oxygen precipitation only for RTA at 1250 °C but not for RTA at 1175 °C. RTA treatment of silicon wafers with one-sided nitride layers at 1250 °C leads to very sharp and small defect denuded zones in subsequent annealing and would be suitable for proximity gettering with their depths being nearly independent of the thickness of the nitride layer.
 

(55) Comparison of Time-Gated Surface-Enhanced Raman Spectroscopy (TG-SERS) and Classical SERS Based Monitoring of Escherichia Coli Cultivation Samples
M. Kögler, A. Paul, E. Anane, M. Birkholz, A. Bunker, T. Viitala, M. Maiwald, S. Junne, P. Neubauer
Biotechnology Progress 34(6), 1533 (2018)
(Bioelectronics)
The application of Raman spectroscopy as a monitoring technique for bioprocesses is severely limited by a large background signal originating from fluorescing compounds in the culture media. Here, we compare time-gated Raman (TG-Raman)-, continuous wave NIRprocess Raman (NIR-Raman), and continuous wave micro-Raman (micro-Raman approaches in combination with surface enhanced Raman spectroscopy (SERS) for their potential to overcome this limit. For that purpose, we monitored metabolite concentrations of Escherichia coli bioreactor cultivations in cell-free supernatant samples. We investigated concentration transients of glucose, acetate, AMP, and cAMP at alternating substrate availability, from deficiency to excess. Raman and SERS signals were compared to off-line metabolite analysis of carbohydrates, carboxylic acids, and nucleotides. Results demonstrate that SERS, in almost all cases, led to a higher number of identifiable signals and better resolved spectra. Spectra derived from the TG-Raman were comparable to those of micro-Raman resulting in well-discernable Raman peaks, which allowed for the identification of a higher number of compounds. In contrast, NIR-Raman provided a superior performance for the quantitative evaluation of analytes, both with and without SERS nanoparticles when using.

(56) Layout Based Electro-Thermal Simulation Setup
F. Korndörfer, A. Datsuk, M. Kaynak
Proc. 19^th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2018), 68 (2018)
In this work we demonstrate the use of an electro-thermal simulation software to simulate the thermal resistance of SiGe HBTs. The method uses a co-simulation of a circuit simulator and a thermal simulator. The thermal model is automatically extracted from the chip layout and the provided material stack. After adaption of the thermal properties of silicon we achieve an agreement between measurement and simulation of better than 5%. The complete simulation flow is integrated in a design kit.

(57) 64 GBd Monolithically Integrated Coherent QPSK Single Polarization Receiver in 0.25 μm SiGe-Photonic Technology
Ch. Kress, S. Gudyriev, H. Zwickel, J.N. Kemal, St. Lischke, L. Zimmermann, Ch. Koos, J.Ch. Scheytt
Proc. Optical Fiber Communications Conference and Exposition (OFC 2018), Th4A.6 (2018)
(SPEED)

(58) Investigation of Cleaning Processes after Tungsten-CMP
A. Krüger, A. Trusch, M. Lisker
Proc. IEEE International Conference on Planarization/CMP Technology (ICPT 2018), (2018)
(MPW)

(59) Comparison of Silica- and Ceria-Slurry for Direct STI-CMP
A. Krüger, A. Trusch, M. Lisker
Proc. IEEE International Conference on Planarization/CMP Technology (ICPT 2018), (2018)
(MPW)

(60) I-Line Stepper Based Overlay Evaluation Method for Wafer Bonding Applications
P. Kulse, K. Sasai, K. Schulz, M. Wietstruck
Proc. SPIE, 10585, 105852J-1 (2018)

(61) Wafer-Scale Fabrication of Recessed-Channel PtSe₂ MOSFETs with Low Contact Resistance and Improved Gate Control
L. Li, K. Xiong, R.J. Marstell, A. Madjar, N.C. Strandwitz, J.C.M. Hwang, N. McEvoy, J.B. McManus, G.S. Duesberg, A. Göritz, M. Wietstruck, M. Kaynak
IEEE Transactions on Electron Devices 65(10), 4102 (2018)
Abstract—For the first time, wafer-scale fabrication of PtSe₂ MOSFETs was demonstrated by photolithography on Pt thermally converted under Se₂ vapor at 400 °C. Taking advantage of the unique property of PtSe₂ to transition from semiconductor to semimetal as its thickness increased beyond a few monolayers, channel recess was adapted for improving gate control while keeping the contact resistance as low as 0.008 Ω∙cm. The wafer-scale fabrication resulted in uniform device characteristics so that average vs. best results were reported, as well as RF vs. DC characteristics. For example, the drain current at VGS = −10, VDS = −1 V were 25 ± 5, 57 ± 8, and 618 ± 17 μA/μm for 4-, 8-, and 12-nm-thick PtSe₂, respectively. The corresponding peak transconductances were 0.20 ± 0.1, 0.60 ± 0.05, and 1.4 ± 0.1 μS/μm. The forward-current cut-off frequency of 12-nm-thick PtSe₂ MOSFETs was 42 ± 5 MHz, whereas the corresponding frequency of maximum oscillation was 180 ± 30 MHz. These results confirmed the application potential of PtSe₂ for future generation thin-film transistors.

(62) High-Performance Waveguide-Coupled Ge Photo Detectors for a Photonic BiCMOS Technology
St. Lischke, D. Knoll, Ch. Mai, L. Zimmermann
Proc. 23^rd OptoElectronics and Communications Conference (OECC 2018), Workshop 2-1-5 (2018)
DOI: 10.1109/oecc.2018.8729865, (DIMENSION)

(63) High-Performance Waveguide-Coupled Ge Photo Detectors for a Photonic BiCMOS Technology
St. Lischke, D. Knoll, Ch. Mai, L. Zimmermann
Proc. 23^rd OptoElectronics and Communications Conference (OECC 2018), Workshop 2-1-5 (2018)
DOI: 10.1109/oecc.2018.8729865, (SPEED)

(64) Contacting Graphene in a 200 mm Wafer Silicon Technology Environment
M. Lisker, M. Lukosius, J. Kitzmann, M. Fraschke, D. Wolansky, S. Schulze, G. Lupina, A. Mai
Solid State Electronics 144, 17 (2018)
Two different approaches for contacting graphene in a 200mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this “stacked via” approach is Ni/TiN/W. We demonstrate that the second “stacked Via” is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

(65) Synthese und Technologieentwicklung für graphenbasierte Bauelemente
M. Lisker, M. Lukosius, G. Lupina, J. Kitzmann, A. Wolff, A. Mai
Proc. EFDS-Workshop: Graphen und andere 2D Materialien (2018), (2018)
(Graphen)

(66) Single-Event Upset Mitigation in a Complementary SiGe HBT BiCMOS Technology
N.E. Lourenco, A. Ildefonso, G.N. Tzintzarov, Z.E. Fleetwood, J.D. Cressler, K. Motoki, P. Paki, M. Kaynak
IEEE Transactions on Nuclear Science 65(1), 231 (2018)
The single-event upset response of SiGe-based digital circuits designed in a third-generation, bulk C-SiGe (npn + pnp) BiCMOS platform is investigated. Heavy-ion, broadbeam experiments across data rate, incidence angle, and bit stream pattern show that the pnp-based shift registers exhibit significant reductions in error cross section when compared with npn-only designs. Ion-strike simulations using 3-D TCAD models agree with the experimental findings, where the pnp SiGe heterojunction bipolar transistor (HBT) exhibits reduced sensitive area and transient duration, leading to large reductions in collected charge at the collector (output) terminal. The circuitlevel, heavy-ion measurements are in agreement with previous device-level, pulsed-laser studies, where the single-event effect (SEE) improvement of pnp SiGe HBTs was attributed to the n-well isolation layer present in the vertical material stack of the pnp SiGe HBT structure. These results provide confirmation that precision analog, RF/mm-wave, and high-speed digital applications utilizing unhardened, high-performance bulk pnp SiGe HBTs should benefit from an inherently improved SEE response.

(67) Growth of High-Quality Graphene for Photonics
M. Lukosius, M. Lisker, G. Dziallas, J. Dabrowski, M. Fraschke, G. Lippert, A. Wolff, A. Mai, Ch. Wenger
Proc. 8^th Graphene 2018, (2018)
(Graphen)

(68) Discrimination of Glioblastoma Cancer Stem Cells by Measuring their UHF-Dielectrophoresis Crossover Frequency
R. Manczak, S. Saada, C. Dalmay, B. Bessette, G. Begaud, S. Battu, P. Blondy, M.O. Jauberteau, F. Lalloue, M. Inac, C. Baristiran Kaynak, M. Kaynak, C. Palego, A. Pothier
Proc. IEEE MTT-S International Microwave Bio Conference (IMBioC 2018), 130 (2018)
(SUMCASTEC)

(69) Tracking Cancer Cells with Microfluidic High Frequency DEP Cytometer Implemented on BiCMOS Lab-on-Chip Platform
R. Manczak, F. Hjeij, T. Provent, S. Saada, C. Dalmay, B. Bessette, G. Begaud, S. Battu, P. Blondy, M.O. Jauberteau, F. Lalloue, M. Inac, C. Baristiran Kaynak, M. Kaynak, C. Palego, A. Pothier
Proc. IEEE MTT-S International Microwave Symposium (IMS 2018), 104 (2018)
(SUMCASTEC)

(70) High-Frequency Dielectrophoresis Characterization of Differentiated vs Undifferentiated Medulloblastoma Cells
R. Manczak, S. Saada, M. Tanori, A. Casciati, C. Dalmay, B. Bessette, G. Begaud, S. Battu, P. Blondy, M.O. Jauberteau, C. Baristiran Kaynak, M. Kaynak, C. Palego, C. Merla, B. Tanno, M. Mancuso, F. Lalloue, A. Pothier
Proc. 1^st EMF-Med World Conference on Biomedical Applications of Electromagnetic Fields (EMF-Med 2018), (2018)
(SUMCASTEC)

(71) Modelling and Performance Study of Monolithically Integrated Depletion Type Silicon IQ Modulators
G.R. Mehrpoor, B. Wohlfeil, M. Eiselt, L. Zimmermann, P. Rito, J.-P. Elbers, B. Schmauss
Proc. ITG-Fachtagung - Photonische Netze (2018), 103 (2018)
(SPEED)

We report on an analytical model for monitoring the bias condition of Silicon IQ modulators. Based on measured phase modulator behavior, ohmic heaters and modulator transfer functions, transmitter performance investigation is attained versus applied bias voltages. We underline error vector magnitude and quadrature error as appropriate metrics for quality measurements of Silicon coherent transmitters.

(72) Experiments on MEMS Integration in 0.25 µm CMOS Process
P. Michalik, D. Fernandez, M. Wietstruck, M. Kaynak, J. Madrenas
Sensors (MDPI) 18(7), 2111 (2018)

(73) Photoluminescence Study of Inter-Band Transitions in Few, Pseudomorphic and Strain-Unbalanced Ge-Rich Ge/GeSi Multiple Quantum Wells
M. Montanari, M. Virgilio, C.L. Manganelli, P. Zaumseil, M.H. Zoellner, Y. Hou, M.A. Schubert, L. Persichetti, L. Di Gaspare, M. De Seta, E. Vitiello, F. Pezzoli, G. Capellini
Physical Review B 98(19), 195310 (2018)
(FLASH)
In this paper we investigate the structural and optical properties of few strain-unbalanced multiple Ge/GeSi quantum wells pseudomorphically grown on GeSi reverse-graded substrates. The obtained high epitaxial quality demonstrates that strain symmetrization is not a mandatory requirement for few quantum-well repetitions. Photoluminescence data, supported by a thorough theoretical modeling, allow us to unambiguously disentangle the spectral features of the quantum wells from those originating in the virtual substrate and to evaluate the impact on the optical properties of key parameters, such as quantum confinement, layer compositions, excess carrier density, and lattice strain. This detailed understanding of the radiative recombination processes is of paramount importance for the development of Ge/GeSi-based optical devices.

(74) TDM-Controlled Ring Resonator Arrays for Fast, Fixed-Wavelength Optical Biosensing
P. Moock, L. Kasper, M. Jäger, D. Stolarek, H.H. Richter, J. Bruns, K. Petermann
Optics Express 26(17), 22356 (2018)
(MINIMUM)
A novel control concept for serial ring resonator arrays based on a time-division multiplex (TDM) approach is presented. It allows fast sampling rates in terms of biological kinetics. The novelty consists of using both thermal tuning of the effective refractive index and thermo-optical multiplexing for the silicon-on-insulator (SOI) ring resonator arrays, without the need for a tunable laser source. Using a fixed wavelength, fast read-out rates of 100 Hz are demonstrated for each ring.

(75) Atomically Controlled Processing for Dopant Segregation in CVD Si and Ge Epitaxial Growth
J. Murota, Y. Yamamoto, I. Costina, B. Tillack, V. Le Thanh, R. Loo, M. Caymax
ECS Journal of Solid State Science and Technology 7(6), P305 (2018)
High performance Si-based devices require atomically ordered interface of heterostructures and doping profiles as well as strain engineering due to the introduction of Ge into Si. In this work, dopant (P and B) segregation for in-situ doping in CVD Si and Ge epitaxial growth is investigated. The epitaxial growth of in-situ doped Si and Ge films either on Si (100) or on a few nm-thick Si_0.5Ge_0.5/Si (100) was performed at 550–555^◦C and 350^◦C, respectively. In the case of P doping, the P atoms segregate to the Si and the Ge surfaces and a part of them are incorporated into the grown Si and Ge cap layers. The P segregation during Si growth is larger than that during Ge growth. In the case of B doping, the B atoms scarcely segregate to the grown Si and Ge surfaces. Based on these experimental results, the in-situ doping processes are explained by the modified Langmuir-type adsorption and reaction scheme.

(76) Nanoguided Filament Approaches for Reliable RRAM
G. Niu, P. Calka, M. Auf der Maur, F. Santoni, M. Fraschke, P. Hamoumou, B. Gautier, E. Perez, C. Wenger, A. Di Carlo, T. Schroeder
Proc. 20^th Workshop on Dielectrics in Microelectronics (WODIM 2018), (2018)

(77) Characterization of the Demonstrator of the Fast Silicon Monolithic ASIC for the TT-PET Project
L. Paolozzi, Y. Bandi, R. Cardarelli, S. Debieux, Y. Favre, D. Ferrere, D. Forshaw, D. Hayakawa, G. Iacobucci, M. Kaynak, A. Miucci, M. Nessi, E. Ripiccini, H. Rücker, P. Valerio, M. Weber
Instrumentation and Detectors 13, P04015 (2018)
DOI: 10.1088/1748-0221/14/02/P02009

(78) Data Retention Investigation in HfO₂-based RRAM Arrays by using Accelerated Tests
E. Perez, M.K. Mahadevaiah, C. Zambelli, P. Olivo, Ch. Wenger
Proc. 20^th Workshop on Dielectrics in Microelectronics (WODIM 2018), 39 (2018)
(NeuroMem)
In this work the feasibility of accelerated tests at high temperatures to test data retention on RRAM devices was evaluated on HfO₂-based 4kbit arrays. By baking the samples at three different temperatures (190, 210, and 230 ^oC) for 10 h, the activation energy of the degradation process was calculated (1.35 eV). In addition, the retention time was extrapolated to room temperature featuring an acceleration factor of about one billion.

(79) The Role of the Bottom and Top Interfaces in the 1^st Reset Operation in HfO₂ based RRAM Devices
E. Perez, M.K. Mahadevaiah, C. Zambelli, P. Olivo, Ch. Wenger
Proc. Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2018), (2018)
(NeuroMem)

(80) Temperature Impact and Programming Algorithm for RRAM Based Memories
E. Perez, A. Grossi, C. Zambelli, M.K. Mahadevaiah, P. Olivo, Ch. Wenger
Proc. IEEE MTT-S International Microwave Workshop Series on Advanced Materials Processes (IMWS-AMP 2018), (2018)
(NeuroMem)

(81) Strain and Band-Gap Engineering in Ge-Sn Alloys via P Doping
S. Prucnal, Y. Berencen, M. Wang, J. Grenzer, M. Voelskow, R. Hübner, Y. Yamamoto, A. Scheit, F. Bärwolf, V. Zviagin, R. Schmidt-Grund, M. Grundmann, J. Zuk, M. Turek, A. Drozdziel, K. Pyszniak, R. Kudrawiec, M.P. Polak, L. Rebohle, W. Skorupa, M. Helm, S. Zhou
Physical Review Applied 10(6), 060455 (2018)
DOI: 10.1103/PhysRevApplied.10.064055
Ge with a quasi-direct band gap can be realized by strain engineering, alloying with Sn or ultra-high n-type doping. In this paper, we use all three approaches together - strain engineering, Sn alloying and n-type doping to fabricate direct band gap GeSn alloys. The heavily-doped n-type GeSn was realized using a CMOS-compatible non-equilibrium material processing. P is used to form a highly-doped n-type GeSn layers and to modify the lattice parameter of GeSn:P alloys. The strain engineering in heavily P-doped GeSn films is confirmed by X-ray diffraction and micro-Raman spectroscopy. The change of the band gap in GeSn:P alloy as a function of P concentration is theoretically predicted using density functional theory and experimentally verified by near-infrared spectroscopic ellipsometry. According to the shift of the absorption edge it is shown that for an electron concentration above 1×1020 cm-3 the band gap renormalization is partially compensated by the Burstein– Moss effect. These results indicate that Ge-based materials have a large potential for the nearinfrared optoelectronic devices, fully compatible with CMOS technology.

(82) Towards 100 Gbps: A Fully Electronic 90 Gbps One Meter Wireless Link at 230 GHz
P. Rodriguez Vazquez, J. Grzyb, N. Sarmah, B. Heinemann, U.R. Pfeiffer
Proc. 48^th European Microwave Conference (EuMC 2018), 1389 (2018)
(Dotseven)

(83) Performance Evaluation of a 32-QAM 1-Meter Wireless Link Operating at 220–260 GHz with a Data-Rate of 90 Gbps
P. Rodriguez Vazquez, J. Grzyb, B. Heinemann, U.R. Pfeiffer
Asia-Pacific Microwave Conference (APMC 2018), 723 (2018)
DOI: 10.23919/APMC.2018.8617171

(84) A 65 Gbps QPSK One Meter Wireless Link Operating at a 225-255 GHz Tunable Carrier in a SiGe HBT Technology
P. Rodriguez-Vazquez, J. Grzyb, N. Sarmah, B. Heinemann, U.R. Pfeiffer
Proc. IEEE Radio and Wireless Symposium (RWS 2018), 146 (2018)
(Dotseven)

(85) Misfit-Dislocation Distributions in Heteroepitaxy: From Mesoscale Measurements to Individual Defects and Back
F. Rovaris, M.H. Zoellner, P. Zaumseil, M.A. Schubert, A. Marzegalli, L. Di Gaspare, M. De Seta, T. Schroeder, P. Storck, G. Schwalb, C. Richter, T.U. Schülli, G. Capellini, F. Montalenti
Physical Review Applied 10(5), 05406 (2018)
(Siltronic Project)
We provide an in-depth characterization of the dislocation distribution in partially relaxed Si0.92Ge0.08/Si(001) films. This is achieved by an innovative and general method, combining two stateof-the-art characterization techniques through suitable modeling. After having inferred the dislocation positions from transmission-electron-microscopy images, we theoretically reproduce scanning-x-raydiffraction-microscopy tilt maps measured on the very same region of the sample. We obtain a nearly perfect match between model predictions and experimental data. As a result, we claim that it is possible to establish a local, direct correlation between the dislocatio

(86) High-Performance SiGe HBTs for Next Generation BiCMOS Technology
H. Rücker, B. Heinemann
Semiconductor Science and Technology 33, 114003 (2018)
(Taranto)
This paper addresses fabrication aspects of SiGe heterojunction bipolar transistors which record
high-speed performance. We previously reported fT values of 505 GHz, fMAX values of 720 GHz, and ring oscillator gate delays of 1.34 ps for these transistors. The impact of critical process steps on radio frequency performance is discussed. This includes millisecond annealing for enhanced dopant activation and optimization of the epitaxial growth process of the base layer. It is demonstrated that the use of a disilane precursor instead of silane can result in reduced base resistance and favorable device scalability.

(87) SiGe HBT Technology
H. Rücker, B. Heinemann
Silicon-Germanium Heterojunction Bipolar Transistors for mm-Wave Systems: Technology, Modeling and Circuit Applications, 1st Edition, Editors N. Rinaldi, M. Schröter, Chapter 1. SiGe HBT Technology, Rivers Publ., 11 (2018)
(Dotseven)

(88) SiGe HBTs for High-Performance BiCMOS Technology
H. Rücker, B. Heinemann
Proc. 1^st Joint Conference International SiGe Technology and Device Meeting and International Conference on Silicon Epitaxy and Heterostructures (ISTDM/ICSI 2018), 69 (2018)
(Taranto)

(89) Ring Filter Synthesis and its BiCMOS 60 GHz Implementation
P. Rynkiewicz, A.-L. Franc, F. Coccetti, M. Wietstruck, Ch. Wipf, S. Tolunay Wipf, M. Kaynak, G. Prigent
International Journal of Microwave and Wireless Technologies (IJMWT) 10(3), 291 (2018)
The detailed synthesis of a direct access ring filter topology fully controlled with the following
targeted specification (center frequency, low transmission zero frequency, and matching level in the passband) is hereby presented. For this topology, the lowest achievable bandwidth is limited by technological constraints. Thereby a solution consisting in adding capacitive loads is proposed. The associated synthesis is also given and discussed. Both syntheses are illustrated with 60 GHz integrated planar filters implemented in the IHP 130 nm BiCMOS technology. Various 3 dB fractional bandwidths from 18 to 8% are targeted, some of them require the implementation of the capacitive loaded solution. The latter allows us to lower the bandwidth limit of the nominal topology as well as to get a high miniaturization, up to 3.4, depending on the capacitance value. Thanks to good measurement results, this implementation highlights the high efficiency, reliability, and versatility of the synthesis without the need of tuning simulations or post-simulations.

(90) Morphological Evolution of Ge/Si Nano-Strips Driven by Rayleigh-Like Instability
M. Salvalaglio, P. Zaumseil, Y. Yamamoto, O. Skibitzki, R. Bergamaschini, T. Schroeder, A. Voigt, G. Capellini
Applied Physics Letters 112(2), 022101 (2018)
(DFG-DACh)
We present the morphological evolution obtained during the annealing of Ge strips grown on Si ridges as a prototypical process for 3D device architectures and nanophotonic applications. In particular, the morphological transition occurring from Ge/Si nanostrips to nanoislands is illustrated. The combined effect of performing annealing at different temperatures and varying the lateral size of the Si ridge underlying the Ge strips is addressed by means of a synergistic experimental and theoretical analysis. Indeed, three dimensional phase-field simulations of surface diffusion, including the contributions of both surface and elastic energy, are exploited to understand the outcomes of annealing experiments. The breakup of Ge/Si strips, due to the activation of surface diffusion at high temperature, is found to be mainly driven by surface-energy reduction, thus pointing to a Rayleigh-like instability. The residual strain is found to play a minor role, only inducing
local effects at the borders of the islands and an enhancement of the instability

(91) Undoped Ge/SiGe Heterostructures: A Platform for Planar Ge Quantum Dots
A. Sammak, D. Sabbagh, N. Hendrick, D. Franke, L.A. Yeoh, M. Virgilio, P. Zaumseil, M.A. Schubert, G. Capellini, M. Veldhorst, G. Scappucci
Proc. 1^st Joint Conference International SiGe Technology and Device Meeting and International Conference on Silicon Epitaxy and Heterostructures (ISTDM/ICSI 2018), 179 (2018)

(92) Morphology Adjustment for Selective Silicon Chemical Vapor Deposition
A. Scheit, Y. Yamamoto, St. Marschmeyer, R. Sorge
Proc. 1^st Joint Conference International SiGe Technology and Device Meeting and International Conference on Silicon Epitaxy and Heterostructures (ISTDM/ICSI 2018), 151 (2018)

(93) Millisecond Flash Lamp Annealing and Application for SiGe-HBT
A. Scheit, T. Lenke, B. Heinemann, H. Rücker, D. Wolansky, W. Skorupa, T. Schumann, L. Rebohle, S. Häberlein
Proc. 12^th International Conference Ion Implantation And Other Applications Of Ions And Electrons (ION 2018), abstr. book 32 (2018)

(94) Suppresion of Sn Segregation During High Temperature Growth of GeSn Nanostructures by Encapsulation
V. Schlykow, G. Capellini, P. Zaumseil, M.A. Schubert, O. Skibitzki, Y. Yamamoto, M. De Seta, L. Di Gaspare, W.M. Klesse, T. Schroeder
Proc. 1^st Joint Conference International SiGe Technology and Device Meeting and International Conference on Silicon Epitaxy and Heterostructures (ISTDM/ICSI 2018), 121 (2018)

(95) Photoluminescence from GeSn Nano-Heterostructures
V. Schlykow, P. Zaumseil, M.A. Schubert, O. Skibitzki, Y. Yamamoto, W.M. Klesse, Y. Hou, M. Virgilio, M. De Seta, L. Di Gaspare, T. Schroeder, G. Capellini
Nanotechnology 29(41), 415702 (2018)
(DFG-DACh)
We investigate the distribution of Sn in GeSn nano-heteroepitaxial clusters deposited at temperatures well exceeding the eutectic temperature of the GeSn system. The 600 °C molecular beam epitaxy on Si-patterned substrates results in the selective growth of GeSn nano-clusters having a 1.4±0.5 at% Sn content. These nano-clusters feature Sn droplets on their faceted surfaces. The subsequent deposition of a thin Ge cap layer induced the incorporation of the Sn atoms segregated on the surface in a thin layer wetting the nano dots surface with 8±0.5 at% Sn. The presence of this wetting layer is associated with a relatively strong photoluminescence emission that we attribute to the direct recombination occurring in the GeSn nano-dots outer region.

(96) Master-Clone Placement with Individual Clock Tree Implementation – a Case on Physical Chip Design
O. Schrape, A. Balashov, A. Simevski, C. Benito, M. Krstic
Proc. IEEE Nordic Circuits and Systems Conference (NORCAS 2018), 122 (2018)

(97) Strain Distribution Analysis of Self-Ordered SiGe Nanodot Structures by Nano Beam Diffraction
M.A. Schubert, Y. Yamamoto, Y. Itoh, P. Zaumseil, G. Capellini, K. Washio, B. Tillack
Proc. 1^st Joint Conference International SiGe Technology and Device Meeting and International Conference on Silicon Epitaxy and Heterostructures (ISTDM/ICSI 2018), 245 (2018)

(98) Impact of TiN Barrier Layer on Contact Resistance of Tungsten Filled Vias
S. Schulze, D. Wolansky, J. Katzer, M.A. Schubert, I. Costina, A. Mai
IEEE Transactions on Semiconductor Manufacturing 31(4), 528 (2018)
In this paper we directly compare the influence of sputtered and chemical vapor deposited TiN liners on the contact resistance of large tungsten filled vias with an aspect ratio of 3:1. Scanning Transmission Electron Microscopy (STEM), Energy-Dispersive X-ray Spectroscopy (EDX) and Time-of-Flight Secodary Ion Mass Spectrometry (ToF-SIMS) studies revealed that during WF₆ based tungsten Chemical vapor deposition (CVD), fluorine diffuses through a poor physical vapor deposited (PVD) TiN barrier layer and reacts with the underlying titanium and aluminum to form high resistive compounds. Aside from depositing a thicker TiN PVD barrier, the replacement of the 40 nm PVD layer with a 2x5 nm TiN CVD liner has led to significantly reduced via resistances with very small deviations across the wafer and lot. We show that the CVD layer has a superior barrier performance against fluorine penetration, provides a conformal coverage and can be used at a reduced thickness compared to the PVD process.

(99) Physical Device Modeling of Si/Si_1-xGe_x Multi-Quantum Well Detector to Optimize Ge Content for Higher Thermal Sensitivity
A. Shafique, S. Abbasi, O. Ceylan, C. Baristiran Kaynak, M. Kaynak, Y. Gurbuz
Proc. SPIE Defense+Security (2018) 10624, 106241A (2018)
(IHP-Sabanci Joint Lab)

(100) A Behavioral Model for High Ge Content in Si/Si_1-xGe_x Multi-Quantum Well Detector
A. Shafique, S. Abbasi, O. Ceylan, A. Göritz, Y. Yamamoto, C. Baristiran Kaynak, M. Kaynak, Y. Gurbuz
IEEE Sensors Journal 18(20), 8280 (2018)
(IHP-Sabanci Joint Lab)
This paper presents a behavioral model for a Si/Si_1−xGe_x multi-quantum well (MQW) detector that predicts device characteristics to investigate the effect of increasing Ge content in Si/Si_1−xGe_x MQW. The modeling approach in this paper is based on a physical instead of empirical approach, which allows to obtain a predictive behavioral analysis of high Ge content with only a few fitting parameters. The model is used to simulate device transfer characteristics with respect to various amounts of Ge content used for Si_1−xGe_x layer in MQW. The simulation results of the proposed model are validated with the experimental data. The simulated and the experimental data are consistent over a wide range of Ge content varied from 30% up to 50%. The primary objective of this paper is to optimize Ge content in the Si/Si_1−xGe_x MQW detector to achieve desired thermal sensitivity measured in terms of temperature coefficient of resistance for a potential microbolometer application. This is the first study in the literature to develop such a highly predictive behavioral model of a Ge-enriched Si/Si_1−xGe_x MQW. The study also presents the effect of including the carbon delta layers at the Si/Si_1−xGe_x heterointerface on the device transfer characteristics. The effect of Ge content on the overall noise is also investigated by the noise characterization of the test devices.

(101) Comprehensive Predictive Device Modeling and Analysis of a Si/Si_1-xGe_x Multiquantum-Well Detector
A. Shafique, S. Abbasi, O. Ceylan, Y. Yamamoto, C. Baristiran Kaynak, M. Kaynak, Y. Gurbuz
IEEE Transactions on Electron Devices 65(10), 4353 (2018)
(IHP-Sabanci Joint Lab)
This paper presents a predictive device model implemented by a self-consistent solution of
Poisson–Schrödinger drift-diffusion formulation for a thermally sensitive detector based on a Si/Si_1−xGe_x multiquantum-well structure. The physical phenomena governing the carrier transport were modeled to investigate the effect of physical design aspects (Ge content, well
periodicity, and well thickness). In particular, we have analyzed the effect of these physical design parameters on the carrier dynamics quantified by the dc performance in terms of net current density. A fully integrated simulation framework was developed and employed to optimize Ge content and device doping for a desired figure of merits specified by temperature coefficient of resistance (TCR) and dc resistance (R). This methodology was successfully utilized to realize device profiles for various amounts of Ge content and optimization of (R) geared for both high TCR and low noise. The dc performance metrics of the optimized profiles obtained bymodeling presented here are compared and validated with the fabricated test devices.

(102) Plasma-Assisted Atomic Layer Deposition of Germanium Antimony Tellurium Compounds
M. Silinskas, B. Kalkofen, R. Balasubramanian, A. Batmanov, E.P. Burte, N. Harmgarth, F. Zörner, F.T. Edelmann, B. Garke, M. Lisker
Journal of Vacuum Science and Technology A 36(2), 021510 (2018)
Plasma atomic layer deposition of Ge-Sb-Te (GST) thin films using halogen-free precursors is
reported. The Sb and Te precursors tris(aziridinyl)antimony (III) (Sb[cyclo-NC₂H₄]₃) and di-nbutylditelluride [Te₂(n-C₄H₉)₂] were employed for the first time in the deposition of GST thin films. Conformal filling of trenches has been demonstrated. The film thickness ratio between the top and the wall/bottom of trenches was evaluated: for “wide” (7:1 aspect ratio) trenches—d_bottom/d_top ≈ 0.65, and for “narrow” (23:1 aspect ratio) trenches d_wall/d_top > 0.63. Due to the use of amino precursors the as-deposited GST films were doped with nitrogen.

(103) P-N-P-Based RF Switches for the Mitigation of Single-Event Transients in a Complementary SiGe BiCMOS Platform
I. Song, M.-K. Cho, Z.E. Fleetwood, Y. Gong, S. Pavlidis, S.P. Buchner, D. McMorrow, P. Paki, M. Kaynak, J.D. Cressler
IEEE Transactions on Nuclear Science 65(1), 391 (2018)
DOI: 10.1109/TNS.2017.2780120
The benefits of using p-n-p silicon-germanium (SiGe) heterojuction bipolar transistors (HBTs) in radio frequency (RF) circuits for the mitigation of single-event transients (SETs) have been investigated. As a representative circuit example, p-n-p SiGe-HBT RF single-pole single-throw (SPST) switches have been designed in a complementary SiGe BiCMOS platform. The fabricated p-n-p-based RF switches provide comparable RF performance to n-p-n-based switches. In terms of SET transient peaks and duration, the p-n-p SiGe HBT RF switches exhibit a significant reduction in SET sensitivity compared with their n-p-n counterparts. In the frequency domain, the p-n-p switches show fewer low-frequency spurs than that of the n-p-n switches. In addition, inverse-mode p-n-p SiGe HBT switches provide the best overall SET response among all RF SPST switches investigated.

(104) JICG MOS Transistors for Reduction of Radiation Effects in CMOS Electronics
R. Sorge, J. Schmidt, Ch. Wipf, F. Reimer, R. Pliquett, Th. Mausolf
Proc. IEEE Topical Workshop on Internet of Space (TWIOS 2018), 17 (2018)
(0,25 µm BiCMOS)
In order to improve the total ionizing dose (TID) and single event upset (SEU) radiation tolerance of bulk CMOS technologies we applied two constructive measures. TID induced source-drain leakage is suppressed by a junction isolation (JI) of the source drain regions using silicide blocked well regions. To decrease the susceptibility against SEU we introduced a redundancy on transistor level, where each MOS transistor is replaced by a stack of two locally separated single transistors which share a common gate (CG). The radiation hardness and device performance of the novel JICG MOS transistors fabricated in IHP’s 250 nm SGB25RH technology were evaluated.

(105) Silicon-on-Insulator Slot Waveguides: Theory and Applications in Electro-Optics and Optical Sensing
P. Steglich
Emerging Waveguide Technology, 1st Edition, Editor: K.Y. You, Chapter 10. Silicon-on-Insulator Slot Waveguides: Theory and Applications in Electro-Optics and Optical Sensing, IntechOpen, 187 (2018)
DOI: 10.5772/intechopen.75539

(106) Quadratic Electro-Optical Silicon-Organic Hybrid RF Modulator in a Photonic Integrated Circuit Technology
P. Steglich, Ch. Mai, A. Peczek, F. Korndörfer, C. Villringer, B. Dietzel, A. Mai
Proc. 64^th IEEE International Electron Devices Meeting (IEDM 2018), 23.3.1 (2018)
(HOPBIT)
For the first time, an integrated electro-optical RF modulator based on the quadratic electro-optical effect with CMOS compatible sub-volt driver voltages is presented. As unique feature, this modulator provides a linear amplitude tuning of the modulated carrier wave. The silicon-based modulator was fabricated using process steps of an established photonic integrated circuit technology and covered by a nonlinear optical polymer in a post-process. We demonstrate a device tunability of up to 350 pm/V, surpassing state-of-the-art silicon modulators with an order of magnitude. Moreover, the ring resonator is designed to have an ultra-low per-bit energy consumption of 87 aJ/bit demonstrating the potential for high-performance photonic devices with low energy consumption.

(107) Quadratic Electro-Optic Effect in Silicon-Organic Hybrid Slot-Waveguides
P. Steglich, Ch. Mai, C. Villringer, S. Pulwer, M. Casalboni, S. Schrader, A. Mai
Optics Letters 43(15), 3598 (2018)
(HOPBIT)
This work reports on the quadratic electro-optic effect of polymers, observed in a silicon slot-waveguide at low voltages. We demonstrate, that in narrow slots the electro-optic response with respect to refractive index change is strong enough for on-chip wavelength tuning and intensity modulation using voltages as low as 1 V. A silicon slot-waveguide embedded by a nonlinear optical polymer, consisting of the dye Disperse Red \nolinebreak1 in poly(methyl methacrylate), serves as phase-shifter in a racetrack ring resonator. As deduced from the experimental data, the third-order susceptibility of the utilized electro-optic polymer is about 2 *10^-19 m^2/V^2. The demonstrated low-voltage operation and inherently thermal stability show the potential for silicon-organic hybrid devices using the quadratic electro-optic effect.

(108) BiCMOS Embedded RF-MEMS Technologies
S. Tolunay Wipf, A. Göritz, M. Wietstruck, Ch. Wipf, M. Kaynak
Microsystems Technology in Germany 34 (2018)
Novel communication system technologies demand not only miniaturization but also multifunctionality. From this perspective, RF-MEMS devices are promising candidates to add functionality into future RF systems. With their good RF performances, there is a growing need and interest in RF-MEMS switches for both RF and mm-wave applications in the recent years. This need is expected to increase tremendously in the near future with more applications operating at mm-wave frequencies.

IHP has developed two BiCMOS embedded RF-MEMS switch technologies for two different technology lines, namely the 0.25 µm and the 0.13 µm SiGe BiCMOS. In both technologies, RF-MEMS Single-Pole Single-Throw (SPST) and Single-Pole Double-Throw (SPDT) switches are realized for mm-wave applications. The technologies offer two different packaging technologies for the RF-MEMS switches, namely Silicon cap packaging and thin film wafer-level encapsulation.

(109) A SiGe HBT D-Band LNA with Butterworth Response and Noise Reduction Technique
E. Turkmen, A. Burak, A. Guner, I. Kalyoncu, M. Kaynak, Y. Gurbuz
IEEE Microwave and Wireless Components Letters 28(6), 524 (2018)
(IHP-Sabanci Joint Lab)

(110) High Responsivity Power Detectors for W/D-Bands Passive Imaging Systems in 0.13µm SiGe BiCMOS Technology
B. Ustundag, E. Turkmen, B. Cetindogan, M. Kaynak, Y. Gurbuz
Proc. 30^th Asia-Pacific Microwave Conference (APMC 2018), (2018)
(IHP-Sabanci Joint Lab)

(111) Low-Noise Amplifiers for W-Band and D-Band Passive Imaging Systems in SiGe BiCMOS Technology
B. Ustundag, E. Turkmen, B. Cetindogan, A. Guner, M. Kaynak, Y. Gurbuz
Proc. 30^th Asia-Pacific Microwave Conference (APMC 2018), (2018)
(IHP-Sabanci Joint Lab)

(112) A 219–266 GHz LO-Tunable Direct-Conversion IQ Receiver Module in a SiGe HBT Technology
P.R. Vazquez, J. Grzyb, N. Sarmah, B. Heinemann, U.R. Pfeiffer
International Journal of Microwave and Wireless Technologies (IJMWT) 10(5-6), 587 (2018)
(Dotseven)

(113) Development of Tunable Fabry-Pérot Polymer Film Sensors for Parellelised Photoacoustic Signal Acquisition
C. Villringer, T.S. Gilani, S. Gehauf, C. Wiedenhöft, P. Steglich, S. Pulwer, M. Richetta, S. Schrader, J. Laufer
Proc. SPIE Photons Plus Ultrasound: Imaging and Sensing (2018), 10494, 1049421 (2018)
DOI: 10.1117/12.2290409

(114) Homodyne and Heterodyne Terahertz Dielectric Sensors: Prototyping and Comparison in BiCMOS Technology for Lab-on-Chip Applications
D. Wang, K. Schmalz, M.H. Eissa, J. Borngräber, M. Kucharski, M. Elkhouly, M. Ko, Y. Wang, H.J. Ng, J. Yun, B. Tillack, D. Kissinger
Proc. IEEE MTT-S International Microwave Bio Conference (IMBioC 2018), 4 (2018)
(DFG-THz LoC)

(115) Development of a Through-Silicon Via (TSV) Process Module for Multi-Project Wafer SiGe BiCMOS and Silicon Interposer
M. Wietstruck, St. Marschmeyer, P. Kulse, T. Voß, M. Lisker, A. Krüger, D. Wolansky, M. Fraschke, M. Kaynak
Proc. 68^th IEEE Electronic Components and Technology Conference (ECTC 2018), 2261 (2018)

(116) Design Optimization of Through-Silicon Vias for Substrate-Integrated Waveguides Embedded in High-Resistive Silicon Interposer
M. Wietstruck, St. Marschmeyer, S. Tolunay Wipf, Ch. Wipf, T. Voß, M. Bertrand, E. Pistono, G. Acri, F. Podevin, P. Ferrari, M. Kaynak
Proc. 20^th IEEE Electronics Packaging Technology (EPTC 2018), (2018)

(117) High Voltage LDMOS Inverter for On-Chip RF-MEMS Actuation
Ch. Wipf, R. Sorge, A. Göritz, S. Tolunay Wipf, A. Scheit, D. Kissinger, M. Kaynak
Proc. 19^th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2018), 48 (2018)
(MEMS Integration)
In this work, two high voltage LDMOS inverters, a charge pump and a differential ring oscillator are designed and combined with a Ka-band RF-MEMS SPDT (single-pole double-throw) switch in a single BiCMOS chip. The circuit is fabricated in a triple well 0.25μm SiGe:C BiCMOS process which includes a LDMOS- and a RFMEMS module. The measured rise and fall times of the high voltage inverter are below 2.5 μs and 2 μs considering a 65 pF capacitor in parallel with a 1M resistor as the load caused by the measurement setup. Simulations based on the RFMEMS electrode capacitance of ˜200 fF – as the real case application – result in a drastically decreased rise (charge) time and fall (discharge) time of 10 ns and 8 ns, respectively. The maximum operating voltage of the LDMOS inverter is 45V, which enables the actuation of the RF-MEMS switch. The measured S-parameters of the RF-MEMS SPDT switch, driven by the developed LDMOS inverters and charge pump, demonstrate the successful implementation.

(118) High Voltage LDMOS Inverter for On-Chip RF-MEMS Actuation
Ch. Wipf, R. Sorge, A. Göritz, S. Tolunay Wipf, A. Scheit, D. Kissinger, M. Kaynak
Proc. 19^th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2018), 48 (2018)
(LDMOS)
In this work, two high voltage LDMOS inverters, a charge pump and a differential ring oscillator are designed and combined with a Ka-band RF-MEMS SPDT (single-pole double-throw) switch in a single BiCMOS chip. The circuit is fabricated in a triple well 0.25μm SiGe:C BiCMOS process which includes a LDMOS- and a RFMEMS module. The measured rise and fall times of the high voltage inverter are below 2.5 μs and 2 μs considering a 65 pF capacitor in parallel with a 1M resistor as the load caused by the measurement setup. Simulations based on the RFMEMS electrode capacitance of ˜200 fF – as the real case application – result in a drastically decreased rise (charge) time and fall (discharge) time of 10 ns and 8 ns, respectively. The maximum operating voltage of the LDMOS inverter is 45V, which enables the actuation of the RF-MEMS switch. The measured S-parameters of the RF-MEMS SPDT switch, driven by the developed LDMOS inverters and charge pump, demonstrate the successful implementation.

(119) First Demonstration of Fully Integrated Segmented Driver and MZM in 0.25−μm  SiGe BiCMOS Employing 112 Gb/s PAM4 over 60 km SSMF
B. Wohlfeil, N. Eiselt, P. Rito, A. Dochhan, G.R. Mehrpoor, D. Rafique, D. Petousi, I. Garcia Lopez, St. Lischke, D. Kissinger, L. Zimmermann, M. Eiselt, H. Griesser, J.-P. Elbers
Proc. European Conference on Optical Communication (ECOC 2018), (2018)
DOI: 10.1109/ECOC.2018.8535510

(120) Impact of Nickel Silicide Formations on SiGe BiCMOS Devices
D. Wolansky, T. Grabolla, T. Lenke, S. Schulze
Proc. 1^st Joint Conference International SiGe Technology and Device Meeting and International Conference on Silicon Epitaxy and Heterostructures (ISTDM/ICSI 2018), 239 (2018)
(Taranto)

(121) Impact of Nickel Silicide on SiGe BiCMOS Devices
D. Wolansky, T. Grabolla, T. Lenke, S. Schulze, P. Zaumseil
Semiconductor Science and Technology 33(12), 124003 (2018)
(Taranto)
Nickel silicide (NiSi) can improve the RF performance of SiGe hetero bipolar transistors (HBT) compared to cobalt silicide (Heinemann et al 2016 IEDM Tech. Dig. 51–4). In this paper, the impact of different procedures to form NiSi on HBT and MOS devices of a 0.13 μm BiCMOS cobalt silicide technology is studied. The different NiSi formations are carried out by partly or fully Ni consumption (PC, FC) for low temperature furnace and low pressure anneals. Our investigations indicate, PC results in rough silicide surfaces and substrate interfaces, whereas FC leads to smooth surfaces and interfaces associated with lower resistivities. FC nickel silicidation at 300 °C and 450 °C exhibits an excessive NiSi growth on the STI edges of n doped source drain (N+SD) regions, reducing the breakdown voltage to substrate or p well. An enhanced NiSi growth is found for all investigated silicide schemes on narrow P+SD regions along polysilicon gates. The leakage current of these structures is caused by enlarged lateral silicidation towards the gates. The enhanced lateral NiSi growth could be suppressed by partly Ni silicidation with furnace anneals at 200 °C or 230 °C.

(122) Wafer-Scale Material-Device Correlation of Tellurene MOSFETs
K. Xiong, L. Li, R.J. Marstell, A. Madjar, N.C. Strandwitz, J.C.M. Hwang, G. Qiu, Y. Wang, W. Wu, P.D. Ye, A. Göritz, M. Wietstruck, M. Kaynak
Proc. IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes (IMWS-AMP 2018), 81 (2018)
Abstract – For the first time, thousands of tellurene MOSFETs were batch-fabricated by a CMOS-compatible wafer process. However, the yield was only approximately 1% mainly because the tellurene was nonuniform and discontinuous. Nevertheless, the large-scale material-device correlation confirmed that the thicker the tellurene, the higher the current capacity, but the lower the on/off ratio. Such large-scale material/device correlation can help improve both the material and the device in the future.

(123) Large-Scale Fabrication of RF MOSFETs on Liquid-Exfoliated MoS₂
K. Xiong, L. Li, A. Madjar, J.C.M. Hwang, Z. Lin, Y. Huang, X. Duan, A. Göritz, M. Wietstruck, M. Kaynak
Proc. 48^th European Microwave Conference (EuMC 2018), 1105 (2018)

(124) Improvement by Channel Recess of Contact Resistance and Gate Control of Large-Scale Spin-Coated MoS₂ MOSFETs
K. Xiong, L. Li, R.J. Marstell, A. Madjar, N.C. Strandwitz, J.C.M. Hwang, Z. Lin, Y. Huang, X. Duan, A. Göritz, M. Wietstruck, M. Kaynak
IEEE Electron Device Letters 39(9), 1453 (2018)
Solution-processed 2-D materials, being low temperature, lowcost, and scalable, are attractive for futuregeneration thin-film and flexible transistors. However, it is challenging to dispense solution-processed 2-D material into a thin and continuous channel for effective and uniform gate control. In addition, a thick channel under the source and drain contacts is requiredto increase the transfer length and decrease the edge contact resistance. To overcome such a dilemma and to obtain the optimum combination of effective gate control and low contact resistance, channel recess was demonstrated for the first time on MoS₂, so that the channel is thin in the gate region but thick in the source and drain regions. Specifically, channel recess by CHF₃/O₂ dry etching up to 60 s was performed on submicron buried-gate MOSFETs fabricated on 20-nm-thick spincoatedMoS₂. It was found that the channel recess improved the current on/off ratio by 3 orders of magnitude while maintaining approximately the same contact resistance and peak transconductance as that of a uniformly 20-nm-thick channel. The resulted performance was among the best of all solution-processed MoS₂ MOSFETs. The same channel recess technique can be used to improve the performance of MOSFETs made of other solution-processed 2-D materials.

(125) CMOS-Compatible Batch Processing of Monolayer MoS₂ MOSFETs
K. Xiong, H. Kim, R.J. Marstell, A. Göritz, Ch. Wipf, L. Li, J.-H. Park, X. Luo, M. Wietstruck, A. Madjar, N.C. Strandwitz, M. Kaynak, Y.H. Lee, J.H.C. Hwang
Journal of Physics D: Applied Physics 51(15), 15LT02 (2018)
Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors
(MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS₂ with fully-
CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS₂ and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS₂ MOSFETs, whether the MoS₂ was grown by a thin-film process or exfoliated from a bulk crystal.

(126) Self-Ordered Ge Nanodot Fabrication by Reduced Pressure Chemical Vapor Deposition
Y. Yamamoto, Y. Itoh, P. Zaumseil, M.A. Schubert, G. Capellini, K. Washio, B. Tillack
Proc. Americas International Meeting on Electrochemistry and Solid State Science (AiMES 2018), (2018)

(127) Self-Ordered Ge Nanodot Fabrication by Reduced Pressure Chemical Vapor Deposition
Y. Yamamoto, Y. Itoh, P. Zaumseil, M.A. Schubert, G. Capellini, K. Washio, B. Tillack
ECS Transactions 86(7), 259 (2018)
Ge nanodot formation on Si surface and its three dimensional alignment is investigated using a reduced pressure chemical vapor deposition (RPCVD) system. By exposing GeH₄ on Si (001) surface at 550^oC, a smooth wetting Ge layer is deposited for the first ~0.9 nm, and then Ge nanodot formation occurs as Stranski-Krastanov growth mechanism. The Ge nanodots are randomly distributed with density of ~6×10¹⁰ cm^-2. By postannealing at 600^oC, the Ge nanodots are coalesced. The size and density become ~60 nm diameter 5 nm height and ~1.5×10¹⁰ cm^-2, respectively. By exposing GeH₄ followed by postannealing at 600^oC on checkerboard mesa structured Si surface which is fabricated by embedded body-centered tetragonal (BCT) Si_0.6Ge_0.4 nanodot, the Ge nanodot formation occurs at concave regions of the checkerboard mesa. By repeating Ge nanodot deposition and Si spacer deposition by two step epitaxy using SiH₄ at 600^oC and using SiH₂Cl₂ at 700^oC, vertical alignment of the Ge nanodots is observed. The lateral periodicity of the Ge nanodots is the same as that of the BCT Si_0.6Ge_0.4 nanodot template. The driving force of the self-ordered alignment is tensile strain of Si spacer surface above the Ge nanodots.

(128) Alignment Control of Self-Ordered Three Dimensional SiGe Nanodots
Y. Yamamoto, Y. Itoh, P. Zaumseil, M.A. Schubert, G. Capellini, K. Washio, B. Tillack
Proc. 1^st Joint Conference International SiGe Technology and Device Meeting and International Conference on Silicon Epitaxy and Heterostructures (ISTDM/ICSI 2018), 25 (2018)

(129) Alignment Control of Self-Ordered Three Dimensional SiGe Nanodots
Y. Yamamoto, Y. Itoh, P. Zaumseil, M.A. Schubert, G. Capellini, F. Montalenti, K. Washio, B. Tillack
Semiconductor Science and Technology 33(11), 114014 (2018)
Alignment control of three dimensional (3D) SiGe nanodot arrangements is investigated using a reduced pressure chemical vapor deposition system. Several cycles of SiGe layers with 30% Ge content and Si spacers are deposited by SiH₄-GeH₄ at 550 °C and SiH₄ or SiH₂Cl₂ at 700 °C, respectively, to form a 3D SiGe nanodot structure. By using SiH₄ as a precursor for the Si spacer deposition, SiGe nanodots are aligned at staggered positions resulting in a body-centered tetragonal (BCT) structure, because a checkerboard mesa structured Si surface is formed and the next SiGe nanodot formation occurs at the concave region to reduce surface energy. On the other hand, after planarizing the Si surface with checkerboard structure by chemical mechanical polishing (CMP), the new SiGe nanodot formation occurs directly above the embedded SiGe nanodot located nearest to the Si surface (dot-on-dot). The driving force seems to be local tensile strain formed at the Si surface above the embedded SiGe nanodot. By using SiH₂Cl₂ as precursor for the Si spacer deposition, a smooth Si surface can be realized on BCT SiGe nanodot structures without CMP process resulting in a vertically aligned SiGe nanodot formation. The local tensile strain formation in Si above SiGe nanodots is confirmed by nano beam diffraction analysis.

(130) Influence of Annealing Conditions on Threading Dislocation Density in Ge Deposited on Si by Reduced Pressure Chemical Vapor Deposition
Y. Yamamoto, P. Zaumseil, M.A. Schubert, B. Tillack
Semiconductor Science and Technology 33(12), 124007 (2018)
The influence of annealing conditions on the crystallinity of Ge deposited on Si(001) is
investigated. Ge deposited with postannealing at 800 °C and 850 °C, five cycles of postannealing at 750 °C and 850 °C (temperature-swing postannealing) and several cycles of annealing at 800 °C or 850 °C during the Ge growth by interrupting the deposition step (cyclic annealing) are compared. To check the threading dislocation density (TDD) of the deeper part of the Ge, thinning by HCl vapor phase etching (VPE) followed by Secco defect etching is performed for 5 μm thick Ge of all three annealing variants. By comparing the TDD of the same Ge thickness with and without HCl VPE, TDD reduction by VPE is observed for the sample using the cyclic annealing process only. Lower TDD is observed at higher postannealing temperature. By the five cycles of temperature swinging, TDD becomes around a half compared to conventional postannealing at 850 °C. In the case of the cyclic annealing process significant improvement of TDD is observed with increasing Ge thickness. Even at a maximum temperature of 800 °C, the same or lower TDD levels were observed for higher than 2 μm thick Ge compared to that with five cycles of temperature-swing postannealing. For the sample with cyclic annealing at 800 °C, a lower Si diffusion length into Ge is also observed for the cyclic annealing process indicating a lower thermal budget. A lower amount of tilted Ge planes at the interface is confirmed showing higher crystal quality also in the deeper part of the Ge layer.

(131) Alignment Control of Vertical / Body-Centered-Tetragonal SiGe Nanodot
Y. Yamamoto, Y. Itoh, P. Zaumseil, M.A. Schubert, G. Capellini, K. Washio, B. Tillack
Proc. 12^th International WorkShop on New Group IV Semiconductor Nanoelectronics (2018), abstr. (2018)

(132) 12 GHz to 40 GHz 0.13-µm SiGe BiCMOS Circuits for UWB 3D Real-Time OFDM MIMO Imaging Radar Applications
U. Yodprasit, W. Winkler, T. Multerer, A.R. Ganis, V. Ziegler, Ch. Wipf, M. Wietstruck
Proc. 11^th German Microwave Conference (GeMiC 2018), 339 (2018)

(133) A Fully-Integrated 60-GHz Voltage-Controlled Oscillator Synchronized by Optoelectronic Signal
U. Yodprasit, M. Kroh, S. Simon, T. Mausolf, W. Winkler
Proc. 25^th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), 173 (2018)
This paper presents a low-phase-noise frequency generator at 60 GHz deploying injection locking of a voltage-controlled oscillator (VCO) to an optical signal. The VCO is a Colpitts push-push oscillator, which is fundamentally locked to an external optical reference laser source. The chip is fabricated using IHP SG25H4 EPIC SiGe technology [1]. Operated from a 3.3-V supply and consuming a DC current of 80 mA, the VCO has a tuning range from 58.5 GHz to 65.7 GHz. At 58.5 GHz, the free-running VCO has a phase noise of -85 dBc/Hz at 1-MHz offset and it was reduced to -111 dBc/Hz under injection locking. This indicated a significant improvement in the phase noise performance of the VCO with optical injection-locking technique.

(134) Single-Chip Si Optical Single-Sideband Modulator
B.-M. Yu, J.-M. Lee, Ch. Mai, St. Lischke, L. Zimmermann, W.-Y. Choi
Photonics Research 6(1), 6 (2018)
We demonstrate an integrated Si optical single-sideband (OSSB) modulator composed of a parallel dual-ring modulator (PDRM) and a quadrature hybrid coupler (QHC). Both the PDRM and the QHC are carefully designed for 30 GHz opearation, and their operations are verified by measurement. The Si OSSB modulator successfully generates a single sideband with larger than 15 dB suppression of the undesired sideband.

(135) The Thermal Stability of Epitaxial GeSn Layers
P. Zaumseil, Y. Hou, M.A. Schubert, N. von den Driesch, D. Stange, D. Rainko, M. Virgilio, D. Buca, G. Capellini
APL Materials 6(7), 076108 (2018)
(DFG GeSn Laser)