Publikationen 2021

Script list Publications

(1) Extended Horizontal SCA Attack using Clustering Algorithm
M. Aftowicz, D. Klann, I. Kabin, Z. Dyka, P. Langendörfer
Proc. 32nd Crypto Day Matters 2021, (2021)
DOI: 10.18420/cdm-2021-32-25

(2) Clustering versus Statistical Analysis for SCA: When Machine Learning is Better
M. Aftowicz, I. Kabin, Z. Dyka, P. Langendörfer
Proc. 10th Mediterranean Conference on Embedded Computing (MECO 2021), 174 (2021)
DOI: 10.1109/MECO52532.2021.9460161, (Total Resilience)

(3) A TOPSIS-Assisted Feature Selection Scheme and SOM-Based Anomaly Detection for Milling Tools under Different Operating Conditions
M. Assafo, P. Langendörfer
IEEE Access 9, 90011 (2021)
DOI: 10.1109/ACCESS.2021.3091476, (iCampus)
Anomaly detection modeled as a one-class classification is an essential task for tool condition monitoring (TCM) when only the normal data are available. To confront with the real-world settings, it is crucial to take the different operating conditions, e.g. rotation speed, into account when approaching TCM solutions. This work mainly addresses the issues associated with multi-operating-condition TCM models, namely the varying discrimination ability of sensory features; the overlap between normal and anomalous data; and the complex structure of input data. A feature selection scheme is proposed in which the Technique for Order Preference by Similarity to Ideal Solution (TOPSIS) is presented as a tool to aid the multi-objective feature selection. In addition, four anomaly detection approaches based on Self-Organizing Map (SOM) are studied, namely the traditional approach, two existing approaches in the literature and a hybrid approach of the two. To examine the stability of the four approaches, they are applied on different single-operating-condition models. Further, to examine their robustness when dealing with complex data structures, they are applied on multi-operating-condition models. The results of the experiments conducted using the NASA Milling Data Set showed that the superior approach was the one which sets local thresholds and utilizes the minimum quantization error as a health indicator. Moreover, our proposed feature selection scheme was compared with the Principal Component Analysis (PCA). The results showed that all the four approaches achieved a higher assessment accuracy with our proposed scheme, with differences of up to 38.6% compared with the PCA.

(4) Single-Trace Address Bit SCA: Atomicity and Regularity are not Effective Countermeasures
Z. Dyka, I. Kabin, D. Klann, P. Langendoerfer
Proc. 33rd Crypto-Day Matters 2021, (2021)
DOI: 10.18420/cdm-2021-33-22, (Total Resilience)

(5) Multiplier as a Mean for Reducing Vulnerability of Atomic Patterns to Horizontal Address-Bit Attacks
Z. Dyka, I. Kabin, D. Klann, P. Langendörfer
Proc. 10th Mediterranean Conference on Embedded Computing (MECO 2021), 183 (2021)
DOI: 10.1109/MECO52532.2021.9460158, (Total Resilience)

(6) On the Complexity of Attacking Commercial Authentication Products
I. Kabin, Z. Dyka, D. Klann, J. Schäffner, P. Langendörfer
Microprocessors and Microsystems 80, 103480 (2021)
DOI: 10.1016/j.micpro.2020.103480, (Total Resilience)
In this paper we discuss the difficulties of mounting successful attack against crypto implementations when essential information is missing. We start with a detailed description of our attack against our own design, to highlight which information is needed to increase the success of an attack, i.e. we use it as a blueprint to the following attack against commercially available crypto chips. We would like to stress that our attack against our own design is very similar to what happens during certification e.g. according to Common Criteria Standard as in those cases the manufacturer need to provide detailed information. When attacking the commercial designs without signing NDAs, we needed to intensively search the Internet for information about the designs. We cannot to reveal the private keys used by the attacked commercial authentication chips 100% correctly. Moreover, the missing knowledge of the used keys does not allow us to evaluate the success of our attack. We were able to reveal information on the processing sequence during the authentication process even as detailed as identifying the clock cycles in which the individual key bits are processed. To summarize the effort of such an attack is significantly higher than the one of attacking a well-known implementation.

(7) Breaking of an Open Source Fully Balanced Elliptic Curve Design using Automated Simple SCA
I. Kabin, Z. Dyka, D. Klann, P. Langendörfer
Proc. 32nd Crypto-Day Matters 2021, (2021)
DOI: 10.18420/cdm-2021-32-23, (Total Resilience)

(8) FFT based Horizontal SCA Attack against ECC
I. Kabin, Z. Dyka, D. Klann, M. Aftowicz, P. Langendörfer
Proc. 11th IFIP International Conference on New Technologies, Mobility & Security (NTMS 2021), (2021)
DOI: 10.1109/NTMS49979.2021.9432665, (Total Resilience)

(9) Fast Dual-Field ECDSA Accelerator with Increased Resistance against Horizontal SCA Attacks
I. Kabin, D. Klann, Z. Dyka, P. Langendörfer
Proc. IEEE International Conference on Cyber Security and Resilience (CSR 2021), 273 (2021)
DOI: 10.1109/CSR51186.2021.9527912, (Total Resilience)

(10) EC Scalar Multiplication: Successful Simple Address-Bit SCA Attack against Atomic Patterns
I. Kabin, Z. Dyka, D. Klann, P. Langendörfer
Proc. 22nd IEEE Latin-American Test Symposium (LATS 2021), (2021)
(Total Resilience)

(11) Resistance of the Montgomery Ladder against Simple SCA: Theory and Practice
I. Kabin, Z. Dyka, D. Klann, M. Aftowicz, P. Langendörfer
Journal of Electronic Testing 37, 289 (2021)
DOI: 10.1007/s10836-021-05951-, (Total Resilience)
The Montgomery kP algorithm i.e. the Montgomery ladder is reported in literature as resistant against simple SCA due to the fact that the processing of each key bit value of the scalar k is done using the same sequence of operations. We implemented the Montgomery kP algorithm using Lopez-Dahab projective coordinates for the NIST elliptic curve B-233. We instantiated the same VHDL code for a wide range of clock frequencies for the same target FPGA and using the same compiler options. We measured electromagnetic traces of the kP executions using the same input data, i.e. scalar k and elliptic curve point P, and measurement setup. Additionally, we synthesized the same VHDL code for two IHP CMOS technologies, for a broad spectrum of frequencies. We simulated the power consumption of each synthesized design during an execution of the kP operation, always using the same scalar k and elliptic curve point P as inputs. Our experiments clearly show that the success of simple electromagnetic analysis attacks against FPGA implementations as well as the one of simple power analysis attacks against synthesized ASIC designs depends on the target frequency for which the design was implemented and at which it is executed significantly. In our experiments the scalar k was successfully revealed via simple visual inspection of the electromagnetic traces of the FPGA for frequencies from 40 to 100 MHz when standard compile options were used as well as from 50 MHz up to 240 MHz when performance optimizing compile options were used. We obtained similar results attacking the power traces simulated for the ASIC. Despite the significant differences of the here investigated technologies the designs’ resistance against the attacks performed is similar: only a few points in the traces represent strong leakage sources allowing to reveal the key at very low and very high frequencies. For the “middle” frequencies the number of points which allow to successfully reveal the key increases when increasing the frequency.

(12) EC P-256: Successful Simple Power Analysis
I. Kabin, Z. Dyka, D. Klann, P. Langendörfer
zu finden unter: https://arxiv.org/abs/2106.12321
(Total Resilience)

(13) Efficient Implementation of Unified ECC Accelerators based on the Karatsuba Multiplication Method
D. Klann, I. Kabin, Z. Dyka, P. Langendörfer
Proc. 32nd Crypto-Day Matters 2021, (2021)
DOI: 10.18420/cdm-2021-32-24, (fast sign)

(14) Assessing AFEDC Architecture's Robustness to Timing Faults
F.A. Kuentzer, M. Krstic
Proc. 33. GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2021), 43 (2021)
(ENROL)

(15) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (NeuroMem)

(16) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (Total Resilience)

(17) Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits
V. Milo, A. Glukhov, E. Perez, C. Zambelli, N. Lepri, M.K. Mahadevaiah, E. Perez-Bosch Quesada, P. Olivo, Ch. Wenger, D. Ielmini
IEEE Transactions on Electron Devices 68(8), 3832 (2021)
DOI: 10.1109/TED.2021.3089995, (Neutronics)
Resistive switching memory (RRAM) is a promising technology for embedded memory and their application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations which might cause a degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slope in the programming characteristics. We test the accuracy of a 2-layer fully-connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a trade-off between the FC-NN accuracy, size and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.

(18) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (KI-PRO)

(19) Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits
V. Milo, A. Glukhov, E. Perez, C. Zambelli, N. Lepri, M.K. Mahadevaiah, E. Perez-Bosch Quesada, P. Olivo, Ch. Wenger, D. Ielmini
IEEE Transactions on Electron Devices 68(8), 3832 (2021)
DOI: 10.1109/TED.2021.3089995, (Total Resilience)
Resistive switching memory (RRAM) is a promising technology for embedded memory and their application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations which might cause a degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slope in the programming characteristics. We test the accuracy of a 2-layer fully-connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a trade-off between the FC-NN accuracy, size and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.

(20) Ensuring a Secure Communication Between a GCS and a UAV via the MAVlink Protocol
P. Mykytyn, I. Kabin, Z. Dyka, P. Langendörfer
Proc. 33rd Crypto-Day Matters 2021, (2021)
DOI: 10.18420/cdm-2021-33-21, (iCampus)

(21) Ensuring a Secure Communication Between a GCS and a UAV via the MAVlink Protocol
P. Mykytyn, I. Kabin, Z. Dyka, P. Langendörfer
Proc. 33rd Crypto-Day Matters 2021, (2021)
DOI: 10.18420/cdm-2021-33-21, (Total Resilience)

(22) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10, 083002 (2021)
Proc. 239th ECS Meeting (2021)
(KI-PRO)

(23) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
DOI: 10.1149/10202.0029ecst, (NeuroMem)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.

(24) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
DOI: 10.1149/10202.0029ecst, (Total Resilience)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.

(25) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
DOI: 10.1149/10202.0029ecst, (KI-PRO)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.

(26) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10, 083002 (2021)
Proc. 239th ECS Meeting (2021)
(Total Resilience)

(27) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10, 083002 (2021)
Proc. 239th ECS Meeting (2021)
(NeuroMem)

(28) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (Total Resilience)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.

(29) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (Neutronics)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.

(30) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (KI-PRO)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.

(31) Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays
E. Perez, M.K. Mahadevaiah, E. Perez-Bosch Quesada, Ch. Wenger
IEEE Transactions on Electron Devices 68(6), 2693 (2021)
DOI: 10.1109/TED.2021.3072868, (Total Resilience)
Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.

(32) Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays
E. Perez, M.K. Mahadevaiah, E. Perez-Bosch Quesada, Ch. Wenger
IEEE Transactions on Electron Devices 68(6), 2693 (2021)
DOI: 10.1109/TED.2021.3072868, (Neutronics)
Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.

(33) Laser Fault Injection Attacks against IHP Chips
D. Petryk, Z. Dyka, P. Langendörfer
Proc. 32nd Crypto-Day Matters 2021, (2021)
DOI: 10.18420/cdm-2021-32-22, (RESCUE)

(34) Optical Fault Injection Attacks: Single-Mode versus Multi-Mode Laser
D. Petryk, Z. Dyka, P. Langendörfer
Proc. 33rd Crypto-Day Matters 2021, (2021)
DOI: 10.18420/cdm-2021-33-23, (Total Resilience)

(35) Sensitivity of HfO2-based RRAM Cells to Laser Irradiation
D. Petryk, Z. Dyka, E. Perez, I. Kabin, J. Katzer, J. Schäffner, P. Langendörfer
Microprocessors and Microsystems 87, 104376 (2021)
(RESCUE)

(36) Radiation Hardness Does Not Mean Tamper Resistance
D. Petryk, Z. Dyka, P. Langendörfer
Proc. Design, Automation and Test in Europe Conference (DATE 2021), Workshop on Interdependent Challenges of Reliability, Security and Quality (RESCUE 2021), (2021)
(RESCUE)

(37) Optical Fault Injection Attacks against Radiation-Hard Registers
D. Petryk, Z. Dyka, R. Sorge, J. Schäffner, P. Langendörfer
Proc. 24th EUROMICRO Conference on Digital System Design (DSD 2021), Special Session: Architectures and Hardware for Security Applications (AHSA), 371 (2021)
DOI: 10.1109/DSD53832.2021.00062, (RESCUE)

(38) Study of Quantized Hardware Deep Neural Networks Based on Resistive Switching Devices, Conventional versus Convolutional Approaches
R. Romero-Zaliz, E. Perez, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Electronics (MDPI) 10(3), 346 (2021)
DOI: 10.3390/electronics10030346, (Total Resilience)
A comprehensive analysis of two types of artificial neural networks (ANN) is performed to assess the influence of quantization on the synaptic weights. Conventional multilayer-perceptron (MLP) and convolutional neural networks (CNN) have been considered by changing their features in the training and inference contexts, such as number of levels in the quantization process, the number of hidden layers on the network topology, the number of neurons per hidden layer, the image databases, the number of convolutional layers, etc. A reference technology based on 1T1R structures with bipolar memristors including HfO2 dielectrics was employed, accounting for different multilevel schemes and the corresponding conductance quantization algorithms. The accuracy of the image recognition processes was studied in depth. This type of studies are essential prior to hardware implementation of neural networks. The obtained results support the use of CNNs for image domains. This is linked to the role played by convolutional layers at extracting image features and reducing the data complexity. In this case, the number of synaptic weights can be reduced in comparison to conventional MLPs.

(39) Study of Quantized Hardware Deep Neural Networks Based on Resistive Switching Devices, Conventional versus Convolutional Approaches
R. Romero-Zaliz, E. Perez, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Electronics (MDPI) 10(3), 346 (2021)
DOI: 10.3390/electronics10030346, (KI-PRO)
A comprehensive analysis of two types of artificial neural networks (ANN) is performed to assess the influence of quantization on the synaptic weights. Conventional multilayer-perceptron (MLP) and convolutional neural networks (CNN) have been considered by changing their features in the training and inference contexts, such as number of levels in the quantization process, the number of hidden layers on the network topology, the number of neurons per hidden layer, the image databases, the number of convolutional layers, etc. A reference technology based on 1T1R structures with bipolar memristors including HfO2 dielectrics was employed, accounting for different multilevel schemes and the corresponding conductance quantization algorithms. The accuracy of the image recognition processes was studied in depth. This type of studies are essential prior to hardware implementation of neural networks. The obtained results support the use of CNNs for image domains. This is linked to the role played by convolutional layers at extracting image features and reducing the data complexity. In this case, the number of synaptic weights can be reduced in comparison to conventional MLPs.

(40) Study of Quantized Hardware Deep Neural Networks Based on Resistive Switching Devices, Conventional versus Convolutional Approaches
R. Romero-Zaliz, E. Perez, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Electronics (MDPI) 10(3), 346 (2021)
DOI: 10.3390/electronics10030346, (NeuroMem)
A comprehensive analysis of two types of artificial neural networks (ANN) is performed to assess the influence of quantization on the synaptic weights. Conventional multilayer-perceptron (MLP) and convolutional neural networks (CNN) have been considered by changing their features in the training and inference contexts, such as number of levels in the quantization process, the number of hidden layers on the network topology, the number of neurons per hidden layer, the image databases, the number of convolutional layers, etc. A reference technology based on 1T1R structures with bipolar memristors including HfO2 dielectrics was employed, accounting for different multilevel schemes and the corresponding conductance quantization algorithms. The accuracy of the image recognition processes was studied in depth. This type of studies are essential prior to hardware implementation of neural networks. The obtained results support the use of CNNs for image domains. This is linked to the role played by convolutional layers at extracting image features and reducing the data complexity. In this case, the number of synaptic weights can be reduced in comparison to conventional MLPs.

(41) An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks based on Memristors
R. Romero-Zaliz, A. Cantudo, E. Perez, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Electronics (MDPI) 10, 03141 (2021)
DOI: 10.3390/electronics10030346, (NeuroMem)

(42) An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks based on Memristors
R. Romero-Zaliz, A. Cantudo, E. Perez, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Electronics (MDPI) 10, 03141 (2021)
DOI: 10.3390/electronics10030346, (Total Resilience)

(43) An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks based on Memristors
R. Romero-Zaliz, A. Cantudo, E. Perez, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Electronics (MDPI) 10, 03141 (2021)
DOI: 10.3390/electronics10030346, (KI-PRO)

(44) Octopuses: Biological Facts and Technical Solutions
O. Shamilyan, I. Kabin, Z. Dyka, M. Kuba, P. Langendörfer
Proc. 9th International Conference on Cyber-Physical Systems and Internet-of-Things (CPS&IoT 2021), 91 (2021)
DOI: 10.1109/MECO52532.2021.9459727, (Total Resilience)

(45) JICG CMOS Transistors for Reduction of Total Ionizing Dose and Single Event Effects in a 130 nm Bulk SiGe BiCMOS Technology
R. Sorge, J. Schmidt, Ch. Wipf, F. Reimer, F. Teply, F. Korndörfer
Nuclear Instruments and Methods in Physics Research Section A 987, 164832 (2021)
DOI: 10.1016/j.nima.2020.164832, (Total Resilience)
We report on a novel radiation hardening by design (RHBD) approach for mitigation of total ionization dose (TID) induced drain leakage currents and single event transient (SET) in digital circuits fabricated in a 130 nm bulk SiGe BiCMOS technology. In order to avoid significant TID induced increase of drain leakage currents for NMOS transistors and channel pinch-off for PMOS transistors due to positive charges trapped at the lateral shallow trench insulator silicon interface we introduced junction isolation (JI) for the lateral MOS channel regions. The device construction measures applied also support to suppress the generation SETs. The tolerance of JI MOS transistors against TID induced drain leakage currents was verified up to a TID > 1.3 Mrad(Si). SET tests performed at four different inverter types varying in the arrangement the deep well in the layout. For CMOS inverters with isolated NMOS transistors a LET threshold > 130 MeV cm2 mg−1 was obtained.

(46) Cryptographic ICs: Simulation of Electromagnetic Radiation
A. Sosa, Z. Dyka, I. Kabin, P. Langendörfer
Proc. 33rd Crypto-Day Matters 2021, (2021)
DOI: 10.18420/cdm-2021-33-13, (Total Resilience)

(47) Simulation of Electromagnetic Emanation of Cryptographic ICs: Tools, Methods, Problems
A. Sosa, Z. Dyka, I. Kabin, P. Langendörfer
Proc. 19th IEEE East-West Design & Test Symposium (EWDTS 2021), 12 (2021)
DOI: 10.1109/EWDTS52692.2021.9581013, (Total Resilience)

(48) Resilience in the Cyberworld: Definitions, Features and Models
E. Vogel, Z. Dyka, D. Klann, P. Langendörfer
Future Internet 13(11)
DOI: 10.3390/fi13110293, (TR-SD)
Resilience is a feature that is gaining more and more attention in computer science and computer engineering. However, the definition of resilience for the cyber landscape, especially embedded systems, is not yet clear. This paper discusses definitions provided by different authors, on different years and with different application areas the field of computer science/computer engineering. We identify the core statements that are more or less common to the majority of the definitions, and based on this we give a holistic definition using attributes for (cyber-) resilience. In order to pave a way towards resilience engineering, we discuss a theoretical model of the life cycle of a (cyber-) resilient system that consists of key actions presented in the literature. We adapt this model for embedded (cyber-) resilient systems.

(49) Resilience in the Cyber World: Definitions, Features and Models
E. Vogel, Z. Dyka, D. Klann, P. Langendörfer
zu finden unter: https://arxiv.org/abs/2105.10235
(Total Resilience)

(50) Resilience in the Cyber World: Definitions, Features and Models
E. Vogel, Z. Dyka, D. Klann, P. Langendörfer
Biosensors (MDPI)
(TR-SD)

(51) Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment
J. Wen, M. Ulbricht, E. Perez, X. Fan, M. Krstic
Proc. 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2021), 29 (2021)
DOI: 10.1109/DDECS52668.2021.9417070, (KI-PRO)

(52) Vibration Analysis of a Wind Turbine Gearbox for Off-Cloud Health Monitoring through Neuromorphic-Computing
P.S. Zarrin, C. Martin, P. Langendörfer, Ch. Wenger, M. Diaz
Proc. 47th Annual Conference of the IEEE Industrial Electronics Society (IECON 2021), (2021)
DOI: 10.1109/IECON48115.2021.9589879, (Total Resilience)

(53) Vibration Analysis of a Wind Turbine Gearbox for Off-Cloud Health Monitoring through Neuromorphic-Computing
P.S. Zarrin, C. Martin, P. Langendörfer, Ch. Wenger, M. Diaz
Proc. 42th International Conference on Information Systems (ICIS 2021), (2021)
DOI: 978-0-9966831-5-9, (RRAM (Resistive RAM))

(54) Vibration Analysis of a Wind Turbine Gearbox for Off-Cloud Health Monitoring through Neuromorphic-Computing
P.S. Zarrin, C. Martin, P. Langendörfer, Ch. Wenger, M. Diaz
Proc. 42th International Conference on Information Systems (ICIS 2021), (2021)
DOI: 978-0-9966831-5-9, (NeuroMem)

(55) Vibration Analysis of a Wind Turbine Gearbox for Off-Cloud Health Monitoring through Neuromorphic-Computing
P.S. Zarrin, C. Martin, P. Langendörfer, Ch. Wenger, M. Diaz
Proc. 42th International Conference on Information Systems (ICIS 2021), (2021)
DOI: 978-0-9966831-5-9, (Total Resilience)

(56) Vibration Analysis of a Wind Turbine Gearbox for Off-Cloud Health Monitoring through Neuromorphic-Computing
P.S. Zarrin, C. Martin, P. Langendörfer, Ch. Wenger, M. Diaz
Proc. 47th Annual Conference of the IEEE Industrial Electronics Society (IECON 2021), (2021)
DOI: 10.1109/IECON48115.2021.9589879, (RRAM (Resistive RAM))

(57) Vibration Analysis of a Wind Turbine Gearbox for Off-Cloud Health Monitoring through Neuromorphic-Computing
P.S. Zarrin, C. Martin, P. Langendörfer, Ch. Wenger, M. Diaz
Proc. 47th Annual Conference of the IEEE Industrial Electronics Society (IECON 2021), (2021)
DOI: 10.1109/IECON48115.2021.9589879, (NeuroMem)

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