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Design Kit

The design kits support a Cadence mixed signal platform:

Analog/Mixed-Signal Flow:


  • Design Framework II (Cadence 6.1)
  • Schematic Design Entry (Cadence Virtuoso Schematic Editor)
  • Simulation
       · Simulation Cockpit: Analog Design Environment – ADE (Cadence)
       · RF: SpectreRF (Cadence)
       · Analog: Spectre/APS (Cadence)
       · Mixed-Signal: AMS Designer/XPS (Cadence)
  • Full Custom Layout (Cadence Virtuoso Layout Editor)
  • Physical Verification (Cadence Assura: DRC/LVS, Cadence QRC: Parasitic Extraction, selected PDKs support Substrate Noise Analysis)
  • Selected PDKs support Cadence VPS for EMIR analysis
  • Support of Analog Office and TexEDA via partners is available
  • Sonnet support for all design kits
  • Cadence interoperable ADS PDK including Momentum and Electro-thermal simulation
  • Physical verification POLYTEDA PowerDRC/LVS and PVCLOUD:

    · DRC/LVS, parasitic extraction and filler generation

    · Integrated with Keysight ADS, Cadence Virtuoso and TexEDA LayTOOLS environments

    Digital Design Flow:
    • Digital CMOS libraries and IO Cells for 0.25µm CMOS and 0.13µm CMOS are available:
      • Behavorial Models (Verilog)
      • Timing Files (LIB)
      • Abstracts (LEF)
    • Digital ECL Library in a future release (additional fee)
    • Simulation: ModelSim (Mentor Graphics), Incisive Enterprise Simulator IES (Cadence)
    • Logic Synthesis: Design Compiler (Synopsys), RTL Compiler (Cadence)
    • Formal Verification: Formality (Synopsys)
    • Scan Insertation and Test Pattern Generation:  DFT Compiler/TetraMax (Synopsys)
    • Place & Route: Encounter Digital Implementation System (Cadence)
      • OA views of digital libraries are available for mixed signal flow
    • Power Analysis: PrimeTime with PrimePower Option (Synopsys)
    • Static Timing Analysis: PrimeTime (Synopsys)


    Please consider that the lists above are non-binding regarding the supported tools and design flows.  If you have any questions please do not hesitate to contact us.

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