1. V. Petrovic , G. Schoof, Z. Stamenkovic, “Fault-tolerant TMR and DMR circuits with latchup protection switches”, Journal Paper - Microelectronics Reliability, Volume 54, Issue 8, Pages 1613-1626, August 2014 Elsevier Ltd.
2. M. Krstic, X. Fan, E. Grass, L. Benini, M. R. Kakoee, C. Heer, B. Sanders, A. Strano, D. Bertozzi, Evaluation of GALS Methods in scaled CMOS Technology – Moonrake Chip Experience, International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 2012, Vol. 3. Iss.4, pp 1-18, DOI: 10.4018/jertcs.2012100101
3. M. Krstić, T. Krol, X. Fan, E. Grass, Reducing EMI using GALS Approach, Journal of Low-Power Electronics, JOLPE - Vol. 6, N° 1, April 2010 - Special Section on PATMOS'09, American Scientific Publishers, Volume 6, Number 1, April 2010, pp. 181-191(11).
4. M. Krstić, E. Grass, F. Gürkaynak, P. Vivet, Globally Asynchronous, Locally Synchronous Circuits: Overview & Outlook, IEEE Design & Test of Computers, Vol. 24, No. 5. September-October 2007, pp. 430-441.
5. V. Petrovic, G. Schoof, M. Krstic, Verbesserter TMR-Strahlungsschutz für ASIC-Layouts, 27. Gesellschaft für Informatik / VDE/VDI-Gesellschaft Mikroelektronik, Mikrosystem- und Feinwerktechnik / Informationstechnische Gesellschaft im VDE – Workshop, Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2015).
6. N. Savic, M. Junghans, M. Krstic, Evaluating Tire Pressure Monitoring System for Traffic Management Purposes – Simulation study, 17th International IEEE Conference on Intelligent Transportation Systems - ITSC 2014, Qingdao, China, October 8-11, 2014.
7. O. Schrape, M. Appel, F. Winkler, M. Krstic, Low-Power Design Methodology for CML and ECL Circuits, 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2014), Palma de Mallorca, Spain.
8. A. Simevski, R. Kraemer, M. Krstic, Investigating core-level N-modular redundancy in multiprocessors, 8th IEEE 8th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-14) September 23-25, 2014, Aizu-Wakamatsu, Japan.
9. A. Simevski, R. Kraemer; M. Krstic, Increasing multiprocessor lifetime by Youngest-First Round-Robin core gating patterns, NASA/ESA Adaptive Hardware and Systems conference (AHS-2014), Leicester, 2014.
10. M. Krstic, S. Weidling, V. Petrovic, M. Gössel, Improved Circuitry for Soft Error Correction in Combinational Logic in Pipelined Designs, IEEE International On-Line Testing Symposium 2014.
11. S. Zeidler, M. Goderbauer, M. Krstic, Design of a Low-Power Asynchronous Elliptic Curve Cryptography Coprocessor, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Abu Dhabi, UAE, Dec, 2013.
12. A. Simevski, R. Kraemer; M. Krstic, Automated Integration of Fault Injection into the ASIC Design Flow, 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), New York, USA.
13. X. Fan, O. Schrape, M. Marinkovic, P. Dähnert, M. Krstic, E. Grass, Optimal GALS Design for Spectral Peak Attenuation on Digital Switching Current, IEEE ASYNC 2013, Santa Monica, USA.
14. S. Zeidler, C. Wolf, M. Krstic, R. Kraemer, Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment, IEEE Asian Test Symposium 2012.
15. A. Simevski, E. Hadzieva, R. Kraemer, M. Krstic, Scalable Design of a Programmable NMR Voter with Inputs’ State Descriptor and Self-checking capability, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012).
16. X. Fan, M. Krstic, E. Grass, Performance analysis of GALS datalink based on pausible clocking scheme, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2012.
17. X. Fan, M. Krstić, E. Grass, B. Sanders, C. Heer, Exploring Pausible Clocking Based GALS Design for 40-nm System Integration, DATE 2012.
18. X. Fan, M. Krstic, C. Wolf, E. Grass, GALS Design for On-Chip Ground Bounce Suppression, 17th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2011.
19. X. Fan, M. Krstic, T. Krol, C. Wolf, E. Grass, A GALS FFT Processor with Clock Modulation for Low-EMI Applications, In Proc. ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, July 7-9, 2010 Rennes, France.
20. X. Fan, M. Krstić, E. Grass, Analysis and Optimization of Pausible Clocking based GALS Design, In Proc. of XXVII IEEE International Conference on Computer Design (ICCD) 2009, Resort at Squaw Creek, Lake Tahoe, California, pp 358-365, "Best Paper" award.