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CMOS

CMOS

High-k gate dielectrics for future CMOS device technologies

Objective

Shrinking conventional CMOS technology in the sub-50 nm regime requires to reduce the thickness of the conventional SiO2 gate oxide to below 1.5 nm. Direct tunnelling becomes the dominant conduction mechanism across the dielectric layer in this thickness range, which results in unacceptably high leakage currents. A materials science approach to enable further transistor scaling in this regime is to to replace the traditional SiO2 gate oxide with alternative high-k gate dielectrics.

IHP`s Contribution

The Materials Research department at IHP is a key player in the field of rare earth dielectric films, in particular Praseodymium (Pr)- based insulators are developed.

Funding

This project is funded by IHP.

Project Partners

  • BTU Cottbus (AG Schmeisser),
  • TU Dresden (AG Bartha),
  • TU Berlin (AG Boit)
The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.