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Virtual GaN substrates on Si wafers

Global and Local Integration Approaches

Concerning the integration of functional semiconductor layers on the technology platform, two main philosophies must be distinguished, depending upon the targeted application:

 

 

Hybrid Devices by Local Integration:

 

Integrated device manufacturers (IDM`s) generally focus R&D activities on local integration approaches where the functional semiconductor is deposited on the Si wafer only in the processed window of the future hybrid device.

 

Hybrid Devices by Global Integration:

Substrate supplier companies focus R&D activities on global integration approaches where the functional semiconductor layer is deposited over the whole wafer.

Depending upon the global or local integration strategy, the following main functional film preparation techniques can be distinguished:

1. Layer transfer techniques:

The most important innovation in the field of global integration approaches for preparing engineered Si wafer systems is the so called layer transfer technique [12]. The sketch in Fig. 2 explains the main steps in the process.

Fig. 2: Soitec’s Smart CutTM technology for Layer transfer [13]

Fig. 2: Soitec’s Smart CutTM technology for Layer transfer [13]

The most important advantage of the layer transfer is its "anything on anything" vision. This term expresses the high flexibility of the approach to bond various materials to each other. However, limitations certainly exist, in especial by the fact that bulk crystal wafers of required quality and diameter do not exist for many interesting compound semiconductor materials. This is especially true for GaN crystals whose quality and diameter is still very limited, as GaN crystal growth by pulling techniques is a major challenge.

2. Die Bonding and Printing Techniques:
Strategies exist which intend to adopt the layer transfer to the task of local integration approaches. These are divided into "die to wafer bonding" and "microstructure printing" techniques. First, III-V die to Silicon on insulator (SOI) wafer bonding was demonstrated with the aim to set up III-V / Si photonic hybrid devices [14]. Fig. 3 illustrates the III-V die bonding of unprocessed InP / InGaAsP on SOI wafer, the subsequent removal of the InP substrate and the processing of the III-V devices.

 

Fig. 3: “Die to wafer bonding” technique for local integration of III-V materials on the Si material platform to fabricate Si photonics hybrid devices [14]

Fig. 3: “Die to wafer bonding” technique for local integration of III-V materials on the Si material platform to fabricate Si photonics hybrid devices [14]

Second, printing techniques are very similar to the die wafer bonding approach but here the functional semiconductor material is already micro-structured [15]. The microstructure is prepared by lithographic means on the bulk wafer of the alternative semiconductor material, lifted-off after applying underetching techniques and subsequently bonded to the bonding pads of the target wafer. An example from Semprius is shown in Fig. 4. Fig. 4 (a) shows an under-etched GaN microstructure on a Nitronex GaN-on-silicon (111) wafer which is afterwards bonded to a Si(001) substrate (Fig. 4(b)). In addition, Fig. 4(c) and 4(d) show Si ribbons printed onto GaAs wafers and GaAs solar cells transferred on a glass substrate, respectively. In this respect, the die bonding and printing techniques offers similar to the layer transfer in principle a high degree of flexibility and even circumvent the problem of the non-availability of large diameter compound semiconductor wafers. However, due to the recent emergence of these interesting innovations, little is known today about the cost-effectiveness of these rather process intensive integration approaches.

Fig. 4: Examples of “microstructure printing” techniques [15-17].

3. Heteroepitaxy growth technique

The classical film deposition approach to prepare single crystalline, functional semiconductor layers on Si substrates is heteroepitaxy. The ordered growth of the functional semiconductor layer on Si is carried out either by physical vapour deposition (PVD) (e.g. molecular beam epitaxy (MBE), pulse laser deposition (PLD) etc.) or chemical vapor deposition (CVD) (e.g. atomic layer deposition (ALD), atomic vapor deposition (AVD) etc.) techniques. Due to the large lattice and thermal mismatch of almost all alternative semiconductor materials with respect to Si, the direct heteroepitaxy of these materials on Si results in poor layer quality [18].  

In order to overcome the integration problems, two major approaches can be applied:

 

1.   Defect engineering

Method based on deposition of the semiconductor material on patterned Si wafers in order to minimize the thermal strain effects and reduce defects.

2.   Buffer approach

This technique is the strain engineering method, always based on the introduction of an additional buffer layer (one or more) between the semiconductor and the Si substrate to minimize the lattice mismatch or/and to compensate the strain which occurs during cooling down after deposition (thermal mismatch strain).

 

Although, defect engineering techniques have been proven to be very efficient to reduce the density of dislocations, the approach inherently suffers from the fact that the process requires lithography. Therefore, heteroepitaxy focusses mostly on the more economical approach, namely on the integration of new semiconductor materials on the Si platform via lattice adjusting buffer layers (as depicted in Fig. 5). The heterostructure is in consequence prepared by two subsequent simple epi-steps:

 

Step 1: growing lattice adjusted or lattice mismatched buffer structures on Si wafers. A wide class of buffer materials is exploited (dielectrics (oxides, fluorides, nitrides etc.), semiconductors (graded SiGe layers etc.).

Step 2: depositing functional semiconductors on the buffer film structures. The functional semiconductor layers are either IV-IV (SiGe, SiC etc), III-V (GaAs, GaN etc.) or II-VI (ZnO, ZnSe etc.) materials.

Fig. 5: Functional semiconductor integration on the Si material platform by heteroepitaxy via lattice matching buffer strategies.

The advantage of the heteroepitaxy approach is clearly its conceptual simplicity. In consequence, it is highly cost-effectiveness in comparison to the competing techniques sketched above. However, the main obstacles in heteroepitaxy to achieve the required layer quality is the fact that the lattice matched or mismatched functional semiconductor layers are grown on foreign materials. Crystal lattice symmetry breaks, geometrical as well as thermal lattice mismatch problems etc. require advanced defect engineering techniques to improve the layers and achieve technologically relevant qualities. For functional GaN thin films, heteroepitaxy is today the only way to achieve reliable GaN wafers and here sapphire as well as SiC substrates are mostly used. As both are expensive and limited in size, cost-reduction approaches in GaN technologies intensify research on “GaN on Si”, as the Si substrate platform with its large scale wafer technologies is comparatively cheap and of outstanding quality and reliability.

 

 

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.