• Start
  • Research print
  • Technology Platform for Wireless and Broadband print
  • Publications print
  • Publications 2015

Publications 2015

since January 2015

(1) A SiGe-Based D-Band Fundamental-Wave VCO with 9 dBm Output Power and -185 dBc/Hz FoMT
F. Ahmed, M. Furqan, B. Heinemann, A. Stelzer
Proc. IEEE Compound Semiconductor IC Symposium (CSICS 2015), 1 (2015)
(Dotseven)

(2) A 40 Gb/s Monolithically Integrated Linear Photonic Receiver in a 0.25 μm BiCMOS SiGe:C Technology
A. Awny, R. Nagulapalli, G. Winzer, M. Kroh, D. Micusik, St. Lischke, D. Knoll, G. Fischer, D. Kissinger, A.C. Ulusoy, L. Zimmermann
IEEE Microwave and Wireless Components Letters 25(7), 469 (2015)
(SASER)
This letter presents the first 40 Gb/s monolithically integrated silicon photonics linear receiver (Rx) comprising a germanium photodiode (Ge-PD) and a linear transimpedance amplifier
(TIA). Measured optical-electrical (O/E) 3 dB bandwidth (BW) of the Rx is 31 GHz. At 40 Gb/s, the Rx achieves a sensitivity of -3dBm average optical input power with BER of 2,5x10-11.
It operates at  wavelength λ= 1.55. µm, uses 3.3 and 3.7 V power supplies, dissipates 275 mW of power, provides maximum differential output amplitude of 500 mVpp , and occupies an area of 3.2. mm2. The presented receiver achieves the highest bit rate among the published work in monolithically integrated silicon photonics receivers.

(3) Mikrostrukturierte Elektroden für Brennstoffzellen
F. Berthold, P. Berthold, N. Kroh
Junge Wissenschaft 30, 18 (2015)

(4) 5-35 GHZ Broadband IF Amplifier Section in 0.13 μm SiGe Technology for W-Band Heterodyne Receiver RFICS
S. Bint Reyaz, R. Jonsson, A. Gustafsson, R. Malmqvist, A. Strodl, V. Valenta, H. Schumacher, M. Kaynak
Microwave and Optical Technology Letters 57, 2286 (2015)
This letter presents the results of a broadband intermediate frequency (IF) section radio frequency integrated circuit designed for a W-band heterodyne radiometer receiver in a 0.13 lm SiGe BiCMOS process. The differential IF section which consists of an amplifier and a power detector uses inductive and resistive matching to obtain a wideband response. The IF amplifier has a measured gain of 10.0–19.5 dB at 2–37 GHz, noise figure of 6–8 dB at 1–26 GHz, and OIP3 of 7–17 dBm at 1–40 GHz. The detector has a measured responsivity of 1 kV/W
and an estimated noise equivalent power (NEP) of 4–6 pW/Hz1/2 at 5–35 GHz, respectively. For the IF section, the input return loss is better than 10 dB at 7–40 GHz and the responsivity is 10–82 kV/W at 5–35 GHz. The broadband properties over significantly wider bandwidths
than earlier reported silicon-based IF amplifier and power detector circuits make the SiGe 5–35 GHz IF section suitable for W-band directconversion radiometer receiver Radio Frequency Integrated Circuits with a larger predetection bandwidth and improved sensitivity.

(5) SiGe BiCMOS High-Gain and Wideband Differential Intermediate Frequency Amplifier for W-band Passive Imaging Single-Chip Receivers
S. Bint Reyaz, R. Malmqvist, A. Gustafsson, M. Kaynak
IET Microwaves, Antennas & Propagation 9(6), 569 (2015)

(6) Depth-Dependent Evolution of Texture and Stress in Thin Films
M. Birkholz
Acta Crystallographica Section C 71, 159 (2015)
(Bioelectronics)

(7) SiGe HBT and BiCMOS Process Integration Optimization within the DOTSEVEN Project
J. Böck, K. Aufinger, S. Boguth, C. Dahl, H. Knapp, W. Liebl, D. Manger, T.F. Meister, A. Pribil, J. Wursthorn, R. Lachner, B. Heinemann, H. Rücker, A. Fox, R. Barth, G. Fischer, St. Marschmeyer, D. Schmidt, A. Trusch, Ch. Wipf
Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2015), 121 (2015)
(Dotseven)
This paper describes the technology development activities within the European funding project DOTSEVEN done by Infineon and IHP. After half of the project duration Infineon has developed a 130 nm SiGe BiCMOS technology with fT of 250 GHz and fmax of 370 GHz. State-of-the-art MMIC performance is demonstrated by a 77 GHz automotive radar transmitter. The suitability of IHP´s advanced SiGe HBT module with epitaxial base link for future industrial BiCMOS platforms is demonstrated by integrating it in Infineon´s 130 nm process resulting in an fmax of 500 GHz, 1.8 ps gate delay and a record 161 GHz static frequency divider. IHP has achieved an fmax of 570 GHz for the first time using an HBT concept with non-selective epitaxial base deposition and an elevated extrinsic base.

(8) Coulomb-Driven Energy Boost of Heavy Ions for Laser-Plasma Acceleration
J. Braenzel, A. Andreev, K. Platonov, M. Klingsporn, L. Ehrentraut, W. Sandner, M. Schnurer
Physical Review Letters 114, 124801 (2015)

(9) A Novel Dual Gap MEMS Varactor Manufactured in a Fully Integrated BiCMOS-MEMS Process
A. Cazzorla, M. Kaynak, P. Farinelli, R. Sorrentino
Proc. Asia-Pacific Microwave Photonics Conference (APMP 2015) (2015)


(10) Strain and Lattice Orientation Distribution in SiN/Ge Complementary Metal–Oxide–Semiconductor Compatible Light Emitting Microstructures by Quick X-Ray Nano-Diffraction Microscopy
G. Chahine, M.H. Zoellner, M.I. Richard, S. Guha, Ch. Reich, P. Zaumseil, G. Capellini, T. Schroeder, T.U. Schülli
Applied Physics Letters 106, 071902 (2015)
This paper presents a study of the spatial distribution of strain and lattice orientation in CMOS fabricated strained Ge microstripes using high resolution x-ray micro-diffraction. The recently
developed model-free characterization tool, based on a quick scanning x-ray diffraction microscopy technique can image strain down to levels of 105 (Da/a) with a spatial resolution of
0.5 lm. Strain and lattice tilt are extracted using the strain and orientation calculation software
package X-SOCS. The obtained results are compared with the biaxial strain distribution obtained
by lattice parameter-sensitive l-Raman and l-photoluminescence measurements. The experimental data are interpreted with the help of finite element modeling of the strain relaxation dynamics in the investigated structures.

(11) A Highly-Efficient 138-170 GHz SiGe HBT Frequency Doubler for Power-constrained Applications
C. Coen, S. Zeinolabedinzadeh, M. Kaynak, B. Tillack, J.D. Cressler
Proc. IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2016), 23 (2016)

(12) X-Band High Dynamic Range Flat Gain SiGe BiCMOS Low Noise Amplifier
M. Davulcu, C. Caliskan, E. Ozeren, Y. Gurbuz, M. Kaynak
Proc. 10th European Microwave Integrated Circuits Conference (EuMIC 2015), 242 (2015)

(13) D-Band MEMS Switch in Standard BiCMOS Technology
Y.J. Du, W. Su, Y. Li, S. Tolunay, M. Kaynak, R. Scholz, Y.-Z. Xiong
Asia-Pacific Microwave Conference (APMC 2015), (2015)
A D-band low loss MEMS switch using BiCMOS process including embedded RF-MEMS structure has been presented in this paper. Both the Mechanical characteristics and RF characteristics of the MEMS switch are analyzed. Through detailed design consideration to reduce the coupling loss, the switch employing match networks of high impedance transmission line exhibits a measured insertion loss of 1.18dB and a measured return loss of 21.69dB at 140GHz. By setting the MEMS switch operated in the resonance state, 23-31dB measured isolation is obtained within the frequency range of 130-170GHz. The monolithic integrated switch occupies 0.47×0.55mm2 chip area including all the pads. The MEMS bridge with tether type anchor is actuated with pull-in voltage of 37V.

(14) 220 GHz Wide-Band MEMS Switch in Standard BiCMOS Technology
Y.J. Du, W. Su, S. Tolunay, L. Zhang, M. Kaynak, R. Scholz, Y.Z. Xiong
Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC 2015), 7-3 (2015)
(Nanotec)
A wideband MEMS switch with the operating
frequency up to 250GHz using standard BiCMOS process
including embedded RF-MEMS structure has been presented in
this paper. Collaborative design and optimization of mechanical
characteristics and RF characteristics are carried out to
guarantee the mechanical reliability. By adopting 􀊌-type circuits
topology with low impedance t-line, the MEMS switch results in a
measured return loss of 24 to 12dB, and an isolation of 54 to 30
dB within the frequency range of 180-250GHz, The MEMS
switch exhibits an insertion loss of 1.9dB at 220GHz with pull-in
voltage of 50V.

(15) A 70 GHz Static Dual-Modulus Frequency Divider in SiGe BiCMOS Technology
A. Ergintav, J. Borngräber, B. Heinemann, H. Rücker, F. Herzel, D. Kissinger
Proc. 11th European Microwave Integrated Circuits Conference (EuMIC 2015), 66 (2015)
(Benchmarking Circuits/Radar Systems)

(16) Ageing and Thermal Recovery of Advanced SiGe Heterojunction Bipolar Transistors under Long-term Mixed Mode and Reverse Stress Conditions
G.G. Fischer, G. Sasso
Microelectronics Reliability 55, 498 (2015)
The main reliability issue in SiGe heterojunction bipolar transistors (HBT) is the cumulative base current degradation which they may experience during circuit operation. This continuous transistor ageing is the result of the interplay between oxide interface trap creation and annihilation. Based upon long-term mixed-mode (up to 1000h) and reverse (up to 100h) stress tests this study discusses in detail the change of ageing rate over time and how this impacts the dependence on stress-voltages and stress-currents. Additionally, investigation of degradation as function of ambient temperature under both stress types reveals stress specific thermal behavior. These results are put together into an ageing function useful for integration into compact models and effectively replacing “life-time” definitions.
At high enough junction temperatures degradation can be reversed, leading to an efficient thermal recovery of the HBTs within one hour independent of previous transistor degradation. Finally, with a simple stress test imitating the switching between mixed-mode ageing and thermal recovering states in HBT duty cycles, it could be demonstrated that DC mixed-mode stress used for standard reliability characterization represents an upper limit for degradation of SiGe HBTs in RF circuits.

(17) Advanced Heterojunction Bipolar Transistor for Half-THz SiGe BiCMOS Technology
A. Fox, B. Heinemann, H. Rücker, R. Barth, G.G. Fischer, Ch. Wipf, St. Marschmeyer, K. Aufinger, J. Böck, S. Boguth, H. Knapp, R. Lachner, W. Liebl, D. Manger, T.F. Meister, A. Pribil, J. Wursthorn
IEEE Electron Device Letters 36, 642 (2015)
(Dotseven)
The high-frequency performance of a novel SiGe HBT module with mono-crystalline base link is investi¬gated in an industrial 0.13 µm BiCMOS environment. The main feature of this new HBT module is a significant reduction of the external base resistance as shown here by direct compari¬son with a conventional double-poly-silicon technology. Peak fT/fmax values of 300 GHz/500 GHz are achieved. A minimum CML ring oscil¬lator gate delay of 1.8 ps and a record operation frequen¬cy for a SiGe static frequency divider of 161 GHz are demonstrated.

(18) A 140-180-GHz Broadband Amplifier with 7 dBm OP1dB and 400 GHz GBW in SiGe BiCMOS
M. Furqan, F. Ahmed, H. Rücker, A. Stelzer
Proc. IEEE Compound Semiconductor IC Symposium (CSICS 2015), 1 (2015)
(Dotseven)

(19) Through Silicon Via Profile Metrology of Bosch Etching Process based on Spectroscopic Reflectometry
O. Fursenko, J. Bauer, St. Marschmeyer, P. Stoll
Microelectronic Engineering 139, 70 (2015)
Through silicon via (TSV) technology is a key feature of new 3D integration of circuits by creation of interconnections using vias, which go through the silicon wafer. Typically, the highly-selective Bosch Si etch process is used which is characterized by a high etch rate and high aspect ratio forming a series of scallops on the sidewall. The large scallops may reduce the reliability of the devices, appearing as leakage currents, thermo-mechanical stress or slow device response. The etch profile which is defined by top and bottom dimensions, depth, scallop size (period and amplitude) need to be both monitored and well controlled. Usually using secondary electron microscopy (SEM) cross-section image analysis is destructive, time consuming and depends on the cutting technique. In this work, the nondestructive 3D metrology of deeply-etched structures with an aspect ratio of more than 10 and patterns with lateral dimensions from 3 to 7 lm was performed by spectroscopic reflectometry. The TSV depths were determined using the interference effect between waves reflected from TSV’s top and bottom surfaces.
The scallop size was estimated from the back diffraction effect of light from the side wall. The rigorous coupled wave analysis (RCWA) has been applied for scallop amplitude and top and bottom dimensions evaluation. By the characterization of the scallop size variation, the etch process (etch depth, rate, and reproducibility) can be controlled.

(20) On the Plasma Chemistry During Plasma Enhanced Chemical Vapor Deposition of Microcrystalline Silicon Oxides
O. Gabriel, S. Kirner, M. Klingsporn, F. Friedrich, B. Stannowski, R. Schlatmann
Plasma Processes and Polymers 12, 82 (2015)
(PVcomB)
The advanced opto-electronic properties of microcrystalline silicon oxide (µc-SiOx:H) thin film layers deposited by means of plasma enhanced chemical vapor deposition (PECVD) resulted in several applications of this material especially in solar cells and modules in the last years. We investigated the plasma chemistry during the PECVD of µc-SiOx:H using in situ plasma diagnostics. Plasma properties are related to the properties of resulting µc-SiOx:H films measured ex situ. Two different deposition regimes were identified. Besides the standard low pressure regime, a high pressure regime was found, which lead to µc-SiOx:H layers with high crystallinities and low refractive

(21) 10 Gb/s5Vpp and 5.6Vpp Drivers Implemented together with Amonolithically Integrated Silicon Modulator in 0.25 μm SiGe:C BiCMOS
B. Goll, D.J. Thomson, L. Zimmermann, H. Porte, F.Y. Gardes, Y. Hub, G.T. Reed, H. Zimmermann
Optics Communications 336, 224 (2015)

(22) Wafer-Level Encapsulation for BiCMOS embedded RF-MEMS Applications
A. Göritz, M. Lisker, S. Tolunay, M. Wietstruck, M. Kaynak
Proc. International Conference on Micro and Nano Engineering (MNE 2015,) (2015)
For cost efficient MEMS packaging, wafer-level encapsulation is the preferred solution. In this work we investigate a wafer-level encapsulation process (SiO2-deposition at T < 250°C) for a HF vapor phase released BiCMOS embedded RF-MEMS switch by FIB-SEM images and C-V measurements.

(23) Impact of Intercell and Intracell Variability on Forming and Switching Parameters in RRAM Arrays
A. Grossi, D. Walczyk, C. Zambelli, E. Miranda, P. Olivo, V. Stikanov, A. Feriani, J. Sune, G. Schoof, R. Kraemer, B. Tillack, A. Fox, T. Schroeder, Ch. Wenger, Ch. Walczyk
IEEE Transactions on Electron Devices 62(8), 2502 (2015)
DOI: 10.1109/TED.2015.2442412, (RRAM (Resistive RAM))
The intercell variability of the initial state and the impact of dc and pulse forming on intercell variability as well as on intracell variability in TiN/HfO2/Ti/TiN 1 transistor – 1 resistor (1T-1R) devices in 4-kb memory arrays were investigated. Nearly 78% of devices on particular arrays were dc formed with a wordline (WL) voltage VWL = 1.4 V and a bitline (BL) voltage VBL = 2.3 V, whereas 22% of devices were not formed due to the combined effect of the extrinsic process-induced intercell variability of the initial state and the intrinsic intercell variability after dc forming. Furthermore, pulse-induced forming with pulsewidths on the order of 10 μs (VWL = 1.4 V and VBL = 3.5 V) caused for 86% of devices a low-resistance state. Using a retry algorithm, we achieve 100% of formed devices. To assess and confirm the nature of the variability during forming operation and during cycling, the quantum point-contact model was considered. The modeling results demonstrate a relationship between the forming and the device performance. The cells requiring high energy for the forming operation, due to impurities in the HfO2 deposition.

(24) Radiation Hard Design of HfO2 based 1T1R Cells and Memory Arrays
A. Grossi, C. Calligaro, E. Perez, F. Teply, Th. Mausolf, C. Zambelli, P. Olivo, Ch. Wenger
Proc. IEEE International Conference on Memristive Systems (MEMRISYS 2015), (2015)
DOI: 10.1109/MEMRISYS.2015.7378390, (R2RAM)

(25) Relationship Among Current Fluctuations during Forming, Cell-to-Cell Variability and Reliability in RRAM Arrays
A. Grossi, C. Zambelli, P. Olivo, E. Miranda, V. Stikanov, T. Schroeder, Ch. Walczyk, Ch. Wenger
Proc. 7th International Memory Workshop (IMW 2015), 93 (2015)
DOI: 10.1109/IMW.2015.7150303, (R2RAM)

(26) A 250 GHz Hetero-Integrated VCO with 0.7 mW Output Power in InP-on-BiCMOS Technology
M. Hossain, N. Weimann, B. Janke, M. Lisker, Ch. Meliani, B. Tillack, O. Krüger, V. Krozer, W. Heinrich
Proc. European Microwave Week (EuMW), 391 (2015)
(SciFab)

(27) A 330 GHz Hetero-Integrated Source in InP-on-BiCMOS Technology
M. Hossain, N. Weimann, M. Lisker, Ch. Meliani, B. Tillack, V. Krozer, W. Heinrich
Proc. IEEE International Microwave Symposium (IMS 2015), (2015)
(SciFab)
This paper presents a 330 GHz hetero-integrated signal source using InP-on-BiCMOS technology. It consists of a fundamental Voltage Controlled Oscillator (VCO) in 0.25 μm BiCMOS technology and a frequency quadrupler in 0.8 μm transferred substrate (TS) InP-HBT technology, which is integrated on top of the BiCMOS MMIC in a wafer-level BCB bonding process. The fundamental VCO operates at 82 GHz and the combined source delivers -12 dBm output power at 328 GHz. To the knowledge of the authors, this is the first hetero-integrated signal source in the frequency range beyond 300 GHz reported so far. It demonstrates the potential of the hetero- integration process for THz frequencies.
Index Terms — InP double heterojunction bipolar transistor (DHBT), monolithic microwave integrated circuit (MMIC) oscillator, millimeter wave (mm-wave) source, terahertz, transferred-substrate process (TS).

(28) A W-Band Power Detector RFIC Design in 0.13 µm SiGe BiCMOS Process
R. Jonsson, S. Bint Reyaz, R. Malmqvist, M. Kaynak
Microwave and Optical Technology Letters 57(2), 414 (2015)

(29) AlN/SiO2/Si3N4/Si(100) based CMOS Compatible Surface Acoustic Wave Filter with -12.8 dB Minimum Insertion Loss
U.Ch. Kaletta, Ch. Wipf, M. Fraschke, D. Wolansky, M.A. Schubert, T. Schroeder, Ch. Wenger
IEEE Transactions on Electron Devices 62(3), 764 (2015)
(Tera-Sens)
A CMOS compatible AlN/SiO2/Si3N4/Si(100) surface acoustic wave (SAW) device has been fabricated and will be compared with standard AlN/SiO2-based devices. The presented filter demonstrates high potential for CMOS integrated high-frequency SAW devices. The filter insertion loss could be improved to −12.8 dB. The device exhibits high crosstalk suppression of −50 dB on a standard Si-substrate (10 cm). X-ray diffraction, (scanning) transmission electron microscopy, and energy dispersive X-ray spectroscopy studies correlate the signal quality with c-axis orientation of aluminum nitride films on interdigitated transducer finger electrodes. Finite-element method simulations are in good agreement with the electric measurements and show typical Rayleigh particle displacement.

(30) Plasma-Assisted Atomic Layer Deposition of Oxide Films for Silicon Doping
B. Kalkofen, A.A. Amusan, M. Lisker, E.P. Burte
Proc. E-MRS Spring Meeting 2015, (2015)
The advanced silicon semiconductor technology requires doping methods for production of ultra-shallow junctions with sufficiently low sheet resistance. Furthermore, advanced 3-dimensional topologies may require damage-free and controlled local doping that cannot be achieved by ion-implantation. Here, the application of the atomic layer deposition method for pre-deposition of dopant sources is presented. Plasma-assisted atomic layer deposition (PALD) was carried for growing thin boron oxide films onto silicon for the formation of dopant sources for shallow boron doping of silicon by rapid thermal annealing. A remote capacitively coupled plasma source powered by GaN microwave oscillators was used for generating oxygen plasma in the PALD process with tris(dimethylamido)borane as boron containing precursor. ALD type growth was obtained; growth per cycle was highest with 0.13 nm at room temperature and decreased with higher temperature. The as-deposited films were highly unstable  in ambient air and could be protected by capping with in-situ PALD grown antimony oxide films. Boron doping of silicon was demonstrated using the uncapped B2O3 films without exposing them to air. The influence of source layer thickness and different annealing conditions during rapid thermal annealing processes on the doping results was investigated as well as the effect of multiple annealings. The dose of active boron in silicon can be controlled by setting the proper film thickness by the PALD process.

(31) Plasma-Assisted Atomic Layer Deposition of Oxide Films for Silicon Doping
B. Kalkofen, A.A. Amusan, H. Gargouri, M. Lisker, E.P. Burte
Proc. AVS Topical Conference on Atomic Layer Deposition (ALD 2015), abstr. book, 311 (2015)

(32) Use of B2O3 Films Grown by Plasma-Assisted Atomic Layer Deposition for Shallow Boron Doping in Silicon
B. Kalkofen, A.A. Amusan, M.S.K. Bukhari, B. Garke, M. Lisker, H. Gargouri, E.P. Burte
Journal of Vacuum Science and Technology A 33, 03152 (2015)
Plasma-assisted atomic layer deposition (PALD) was carried for growing thin boron oxide films
onto silicon aiming at the formation of dopant sources for shallow boron doping of silicon by rapid
thermal annealing (RTA). A remote capacitively coupled plasma source powered by GaN
microwave oscillators was used for generating oxygen plasma in the PALD process with
tris(dimethylamido)borane as boron containing precursor. ALD type growth was obtained; growth
per cycle was highest with 0.13 nm at room temperature and decreased with higher temperature.
The as-deposited films were highly unstable in ambient air and could be protected by capping with
in-situ PALD grown antimony oxide films. After 16 weeks of storage in air, degradation of the film
stack was observed in an electron microscope. The instability of the boron oxide, caused by
moisture uptake, suggests the application of this film for testing moisture barrier properties of
capping materials particularly for those grown by ALD. Boron doping of silicon was demonstrated
using the uncapped PALD B2O3 films for RTA processes without exposing them to air. The boron
concentration in the silicon could be varied depending on the source layer thickness for very thin
films, which favors the application of ALD for semiconductor doping processes.

(33) Silicon Based CMOS Integrated Microfluidic Platform for THz-Sensing Applications
M. Kaynak
Proc. IEEE MTT-S International Microwave Symposium (IMS 2015) WMD, 325 (2015)

(34) A D-Band Micromachined End-Fire Antenna in 130-nm SiGe BiCMOS Technology
W.T. Khan, A.C. Ulusoy, G. Dufour, M. Kaynak, B. Tillack, J.D. Cressler, J. Papapolymerou
IEEE Transactions on Antennas and Propagation 63, 2449 (2015)

(35) Resistive Switching Characteristics of Integrated Polycrystalline Hafnium Oxide Based one Transistor and one Resistor Devices Fabricated by Atomic Vapor Deposition Methods
H.-D. Kim, F. Crupi, M. Lukosius, A. Trusch, Ch. Walczyk, Ch. Wenger
Journal of Vacuum Science and Technology B 33, 052204 (2015)
DOI: 10.1116/1.4928412, (R2RAM)
In this work, bipolar resistive switching (RS) characteristics of polycrystalline hafnium oxide were studied for embedded 1T1R RRAM device applications. The HfO2 films with thickness of 15 nm to 25 nm were grown by the atomic vapor deposition (AVD) method at 400 °C. The HfO2 films were estimated as polycrystalline from the surface topography results by applying atomic force microscopy (AFM) and X-ray diffraction (XRD), and grain size observed in the AFM images increased when increasing thickness of HfO2 films. In addition, current voltage characteristics of the films were investigated to examine the RS characteristics. First, in the forming procedure, we observed the lowest forming voltage for 15 nm thick HfO2 films and the forming voltage gradually increased with increasing the thickness of the HfO2 films. A reproducible resistance switching behavior was observed with resistance ratio of ~20 and dc cycling of 100
times. SET and RESET voltages were measured about 1.2 and 1.6 V, respectively, indicating that the RRAM device can be operated below 2 V. The Current-Voltage characteristics are discussed in the frame of the quantum point contact model.

(36) Investigation of the Copper Gettering Mechanism of Oxide Precipitates in Silicon
G. Kissinger, D. Kot, M. Klingsporn, M.A. Schubert, A. Sattler, T. Müller
ECS Journal of Solid State Science and Technology 4(9), N124 (2015)
(Future Silicon Wafers)
One of the reasons why the principal gettering mechanism of copper at oxide precipitates is not yet clarified is that it was not possible to identify the presence and measure the copper concentration in the vicinity of oxide precipitates. To overcome the problem we used a 14.5 nm thick thermal oxide layer as a model system for an oxide precipitate to localize the place where the copper is collected. We also analyzed a plate-like oxide precipitate by EDX and EELS and compared the results with the analysis carried out on the oxide layer. It is demonstrated that both the interface between the oxide precipitate being SiO2 and the silicon matrix and the interface between the thermal oxide and silicon consist of a 2-3 nm thick SiO layer. As the results of these experiments also show that copper segregates at the SiO interface layer of the thermal oxide it is concluded that gettering of copper by oxide precipitates is based on segregation of copper to the SiO interface layer.

(37) High-Performance Photonic BiCMOS Process for the Fabrication of High-Bandwidth Electronic-Photonic Integrated Circuits
D. Knoll, St. Lischke, R. Barth, L. Zimmermann, B. Heinemann, H. Rücker, Ch. Mai, M. Kroh, A. Peczek, A. Awny, A.C. Ulusoy, A. Trusch, A. Krüger, J. Drews, M. Fraschke, D. Schmidt, M. Lisker, K. Voigt, E. Krune, A. Mai
Proc. IEEE International Electron Devices Meeting (IEDM 2015), 402 (2015)
(RF2THzSiSoC)

(38) High-Performance Photonic BiCMOS Process for the Fabrication of High-Bandwidth Electronic-Photonic Integrated Circuits
D. Knoll, St. Lischke, R. Barth, L. Zimmermann, B. Heinemann, H. Rücker, Ch. Mai, M. Kroh, A. Peczek, A. Awny, A.C. Ulusoy, A. Trusch, A. Krüger, J. Drews, M. Fraschke, D. Schmidt, M. Lisker, K. Voigt, E. Krune, A. Mai
Proc. IEEE International Electron Devices Meeting (IEDM 2015), 402 (2015)
(MOSAIC)

(39) High-Performance Photonic BiCMOS Process for the Fabrication of High-Bandwidth Electronic-Photonic Integrated Circuits
D. Knoll, St. Lischke, R. Barth, L. Zimmermann, B. Heinemann, H. Rücker, Ch. Mai, M. Kroh, A. Peczek, A. Awny, A.C. Ulusoy, A. Trusch, A. Krüger, J. Drews, M. Fraschke, D. Schmidt, M. Lisker, K. Voigt, E. Krune, A. Mai
Proc. IEEE International Electron Devices Meeting (IEDM 2015), 402 (2015)
(SASER)

(40) High-Performance BiCMOS Si Photonics Platform
D. Knoll, St. Lischke, A. Awny, M. Kroh, E. Krune, Ch. Mai, A. Peczek, D. Petousi, S. Simon, K. Voigt, G. Winzer, R. Barth, L. Zimmermann
Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2015), 88 (2015)
(RF2THzSiSoC)

(41) Fabrication of High Bit Rate, Monolithically Integrated Receivers in Photonic BiCMOS Technology
D. Knoll, St. Lischke, L. Zimmermann, A. Awny, M. Kroh, A. Peczek, K. Voigt, K. Petermann
Proc. IEEE International Conference on Group IV Photonics (GFP), ThF5 (2015)
(SASER)

(42) High-Performance BiCMOS Si Photonics Platform
D. Knoll, St. Lischke, A. Awny, M. Kroh, E. Krune, Ch. Mai, A. Peczek, D. Petousi, S. Simon, K. Voigt, G. Winzer, R. Barth, L. Zimmermann
Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2015), 88 (2015)
(SASER)

(43) High-Performance BiCMOS Si Photonics Platform
D. Knoll, St. Lischke, A. Awny, M. Kroh, E. Krune, Ch. Mai, A. Peczek, D. Petousi, S. Simon, K. Voigt, G. Winzer, R. Barth, L. Zimmermann
Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2015), 88 (2015)
(MOSAIC)

(44) Experimental and Theoretical Study of fT for SiGe HBTs with a Scaled Vertical Doping Profile
J. Korn, H. Rücker, B. Heinemann, A. Pawlak, G. Wedel, M. Schröter
Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2015), 117 (2015)
(Dotseven)

(45) Composition of Oxygen Precipitates in Czochralski Silicon Wafers Investigated by STEM with EDX/EELS and FTIR Spectroscopy
D. Kot, G. Kissinger, M.A. Schubert, M. Klingsporn, A. Huber, A. Sattler
Physica Status Solidi RRL 9(7), 405 (2015)
In this work, we investigated the stoichiometry of oxygen precipitates in Czochralski silicon wafers. The thickness dependence of the Cliff–Lorimer sensitivity factor for the silicon/
oxygen system was determined and applied for the investigation of the stoichiometry of oxygen precipitates by EDX. The results show that both plate-like oxygen precipitates and
a transitional form between plate-like and octahedral precipitates consist of SiO2. This was confirmed by EELS low loss spectra where the typical spectrum for amorphous SiO2 was
observed. Moreover, the absorption band of plate-like precipitates at 1227 cm–1 was found in the low temperature FTIR spectrum. It was demonstrated that this band can only be simulated
by the dielectric constants of amorphous SiO2.

(46) A Monolithically Integrated Opto-Electronic Clock Converter in Photonic SiGe-BiCMOS Technology
B. Krüger, R.E. Makon, O. Landolt, E. Krune, D. Knoll, St. Lischke, J. Schulze
Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2015), (2015)
(MOSAIC)

(47) Graded Applications of NQS Theory for Modeling Correlated Noise in SiGe HBTs
K. Kumar, A. Chakravorty, G.G. Fischer, Ch. Wipf
IEEE Transactions on Electron Devices 62(8), 2384 (2015)
In this paper, we develop a correlated noise model for bipolar transistors from an accurate non-quasi-static model. The proposed noise model includes the signal delay through base-collector space-charge-region and is implemented using four extra nodes. We also present a simplified version of the same model that requires only two extra nodes. A further simplified version that uses only one extra node is found to be indentical with a state-of-the-art correlated noise model. Comparison with the experimental data shows comparable accuracy levels of all the models since the external parasitics of the fabricated transistor substantially mask the 1D noise correlation effects. When compared with the device simulation data, our proposed model hows improved accuracy compared to the existing state-of-the-art noise models.

(48) An 8-GHz CMOS-APD Based on Multiple P+/N-Well Junctions With Carrier-Acceleration Technique
M.J. Lee, J.M. Lee, H. Rücker, W.Y. Choi
IEEE Photonics Technology Letters 27(13), 1387 (2015)
(0,25 µm BiCMOS)
We present a silicon avalanche photodetector (APD) based on multiple P+/N-well junctions fabricated in standard complementary metal–oxide–semiconductor (CMOS) technology.
In order to overcome the photodetection-bandwidth limitation of the CMOS-APD based on P+/N-well junction, carrieracceleration technique is proposed. With this technique, the
photogenerated carriers in the charge-neutral N-well region are accelerated by the extrinsic electric field. To induce the extrinsic electric field inside N-well, the CMOS-APD is designed
with multiple junctions to reduce the distance between two different N-well biasing contacts. Its performance is simulated and measured with different bias voltages applied to N-well,
and it is demonstrated that the CMOS-APD with the carrier-acceleration technique provides higher photodetection bandwidth.

(49) High-Bandwidth, Waveguide-Coupled Ge p-i-n Photodiode with High C- and L-Band Responsivity
St. Lischke, D. Knoll, Ch. Mai, A. Peczek, K. Voigt, E. Krune, K. Petermann, L. Zimmermann, A. Mai
Proc. International Conference on Group IV Photonics (GFP), WD4 (2015)
(SASER)
We present a germanium photodiode showing, at -2V bias, responsivity exceeding 0.8A/W across the entire C- and L-band, together with 40GHz zero bias bandwidth, which strongly extends the application range of silicon photonics.

(50) High Bandwidth, High Responsivity Waveguide-Coupled Ge p-i-n Photodiode
St. Lischke, D. Knoll, Ch. Mai, L. Zimmermann, A. Peczek, M. Kroh, A. Trusch, E. Krune, K. Voigt, A. Mai
Optics Express 23(21), 27213 (2015)
(MOSAIC)
A novel waveguide-coupled Ge p-i-n photodiode is demonstrated which combines high responsivity with very high bandwidths at a medium dark current. -3 dB bandwidths are 40 GHz at zero bias and more than 70 GHz at -1 V. Responsivity for 1.55 μm wavelength ranges between 0.84 A/W at zero bias and 1.06 A/W at -2 V while room temperature dark current density at -1 V is about 1 A/cm². The high responsivity mainly results from the use of a new, low-loss contact scheme, which moreover also suppresses the negative effect of photo carrier diffusion on bandwidth.

(51) High Bandwidth, High Responsivity Waveguide-Coupled Ge p-i-n Photodiode
St. Lischke, D. Knoll, Ch. Mai, L. Zimmermann, A. Peczek, M. Kroh, A. Trusch, E. Krune, K. Voigt, A. Mai
Optics Express 23(21), 27213 (2015)
(RF2THzSiSoC)
A novel waveguide-coupled Ge p-i-n photodiode is demonstrated which combines high responsivity with very high bandwidths at a medium dark current. -3 dB bandwidths are 40 GHz at zero bias and more than 70 GHz at -1 V. Responsivity for 1.55 μm wavelength ranges between 0.84 A/W at zero bias and 1.06 A/W at -2 V while room temperature dark current density at -1 V is about 1 A/cm². The high responsivity mainly results from the use of a new, low-loss contact scheme, which moreover also suppresses the negative effect of photo carrier diffusion on bandwidth.

(52) High Bandwidth, High Responsivity Waveguide-Coupled Ge p-i-n Photodiode
St. Lischke, D. Knoll, Ch. Mai, L. Zimmermann, A. Peczek, M. Kroh, A. Trusch, E. Krune, K. Voigt, A. Mai
Optics Express 23(21), 27213 (2015)
(SASER)
A novel waveguide-coupled Ge p-i-n photodiode is demonstrated which combines high responsivity with very high bandwidths at a medium dark current. -3 dB bandwidths are 40 GHz at zero bias and more than 70 GHz at -1 V. Responsivity for 1.55 μm wavelength ranges between 0.84 A/W at zero bias and 1.06 A/W at -2 V while room temperature dark current density at -1 V is about 1 A/cm². The high responsivity mainly results from the use of a new, low-loss contact scheme, which moreover also suppresses the negative effect of photo carrier diffusion on bandwidth.

(53) Monolithic Integration of High Bandwidth Waveguide Coupled Ge Photodiode in a Photonic BiCMOS Process
St. Lischke, D. Knoll, L. Zimmermann
Proc. SPIE Photonics West, 9390, 93900F-1 (2015)
(SASER)
Monolithic integration of photonic functionality in the frontend-of-line (FEOL) of an advanced microelectronics technology is a key step towards future communication applications. This combines photonic components such as waveguides, couplers, modulators, and photo detectors with high-speed electronics plus shortest possible interconnects crucial for high-speed performance. Integration of photonics into CMOS FEOL is therefore in development for quite some time reaching 90nm node recently [1]. However, an alternative to CMOS is high-performance BiCMOS, offering significant advantages for integrated photonics-electronics applications with regard to cost and RF performance. We already presented results of FEOL integration of photonic components in a high-performance SiGe:C BiCMOS baseline to establish a novel, photonic BiCMOS process. Process cornerstone is a local-SOI approach which allows us to fabricate SOI-based, thus low-loss photonic components in a bulk BiCMOS environment [2]. A monolithically integrated 10Gbit/sec Silicon modulator with driver was shown here [3]. A monolithically integrated 25Gbps receiver was presented in [4], consisting of 200GHz bipolar transistors and CMOS devices, low-loss waveguides, couplers, and high-speed Ge photo diodes showing 3-dB bandwidth of 35GHz, internal responsivity of more than 0.6A/W at = 1.55μm, and ~ 50nA dark current at 1V. However, the BiCMOS-given thermal steps cause a significant smearing of the Germanium photo diodes doping profile, limiting the photo diode performance. Therefore, we introduced implantation of non-doping elements to overcome such limiting factors, resulting in photo diode bandwidths of more than 50GHz even under the effect of thermal steps necessary when the diodes are integrated in a high performance BiCMOS process.

(54) Monolithic Integration of High Bandwidth Waveguide Coupled Ge Photodiode in a Photonic BiCMOS Process
St. Lischke, D. Knoll, L. Zimmermann
Proc. SPIE Photonics West, 9390, 93900F-1 (2015)
(RF2THzSiSoC)
Monolithic integration of photonic functionality in the frontend-of-line (FEOL) of an advanced microelectronics technology is a key step towards future communication applications. This combines photonic components such as waveguides, couplers, modulators, and photo detectors with high-speed electronics plus shortest possible interconnects crucial for high-speed performance. Integration of photonics into CMOS FEOL is therefore in development for quite some time reaching 90nm node recently [1]. However, an alternative to CMOS is high-performance BiCMOS, offering significant advantages for integrated photonics-electronics applications with regard to cost and RF performance. We already presented results of FEOL integration of photonic components in a high-performance SiGe:C BiCMOS baseline to establish a novel, photonic BiCMOS process. Process cornerstone is a local-SOI approach which allows us to fabricate SOI-based, thus low-loss photonic components in a bulk BiCMOS environment [2]. A monolithically integrated 10Gbit/sec Silicon modulator with driver was shown here [3]. A monolithically integrated 25Gbps receiver was presented in [4], consisting of 200GHz bipolar transistors and CMOS devices, low-loss waveguides, couplers, and high-speed Ge photo diodes showing 3-dB bandwidth of 35GHz, internal responsivity of more than 0.6A/W at = 1.55μm, and ~ 50nA dark current at 1V. However, the BiCMOS-given thermal steps cause a significant smearing of the Germanium photo diodes doping profile, limiting the photo diode performance. Therefore, we introduced implantation of non-doping elements to overcome such limiting factors, resulting in photo diode bandwidths of more than 50GHz even under the effect of thermal steps necessary when the diodes are integrated in a high performance BiCMOS process.

(55) Monolithic Integration of High Bandwidth Waveguide Coupled Ge Photodiode in a Photonic BiCMOS Process
St. Lischke, D. Knoll, L. Zimmermann
Proc. SPIE Photonics West, 9390, 93900F-1 (2015)
(MOSAIC)
Monolithic integration of photonic functionality in the frontend-of-line (FEOL) of an advanced microelectronics technology is a key step towards future communication applications. This combines photonic components such as waveguides, couplers, modulators, and photo detectors with high-speed electronics plus shortest possible interconnects crucial for high-speed performance. Integration of photonics into CMOS FEOL is therefore in development for quite some time reaching 90nm node recently [1]. However, an alternative to CMOS is high-performance BiCMOS, offering significant advantages for integrated photonics-electronics applications with regard to cost and RF performance. We already presented results of FEOL integration of photonic components in a high-performance SiGe:C BiCMOS baseline to establish a novel, photonic BiCMOS process. Process cornerstone is a local-SOI approach which allows us to fabricate SOI-based, thus low-loss photonic components in a bulk BiCMOS environment [2]. A monolithically integrated 10Gbit/sec Silicon modulator with driver was shown here [3]. A monolithically integrated 25Gbps receiver was presented in [4], consisting of 200GHz bipolar transistors and CMOS devices, low-loss waveguides, couplers, and high-speed Ge photo diodes showing 3-dB bandwidth of 35GHz, internal responsivity of more than 0.6A/W at = 1.55μm, and ~ 50nA dark current at 1V. However, the BiCMOS-given thermal steps cause a significant smearing of the Germanium photo diodes doping profile, limiting the photo diode performance. Therefore, we introduced implantation of non-doping elements to overcome such limiting factors, resulting in photo diode bandwidths of more than 50GHz even under the effect of thermal steps necessary when the diodes are integrated in a high performance BiCMOS process.

(56) High-Bandwidth, Waveguide-Coupled Ge p-i-n Photodiode with High C- and L-Band Responsivity
St. Lischke, D. Knoll, Ch. Mai, A. Peczek, K. Voigt, E. Krune, K. Petermann, L. Zimmermann, A. Mai
Proc. International Conference on Group IV Photonics (GFP), WD4 (2015)
(RF2THzSiSoC)
We present a germanium photodiode showing, at -2V bias, responsivity exceeding 0.8A/W across the entire C- and L-band, together with 40GHz zero bias bandwidth, which strongly extends the application range of silicon photonics.

(57) High-Bandwidth, Waveguide-Coupled Ge p-i-n Photodiode with High C- and L-Band Responsivity
St. Lischke, D. Knoll, Ch. Mai, A. Peczek, K. Voigt, E. Krune, K. Petermann, L. Zimmermann, A. Mai
Proc. International Conference on Group IV Photonics (GFP), WD4 (2015)
(MOSAIC)
We present a germanium photodiode showing, at -2V bias, responsivity exceeding 0.8A/W across the entire C- and L-band, together with 40GHz zero bias bandwidth, which strongly extends the application range of silicon photonics.

(58) Active Dummy Generation for Homogeneity Increase in a 130 nm BiCMOS Process
M. Lisker, A. Krüger, E. Matthus, A. Trusch, A. Mai
Proc. IEEE International Conference on Planarization/CMP Technology (ICPT 2015), 139 (2015)

(59) Direct Growth of HfO2 on Graphene by CVD
M. Lukosius, J. Dabrowski, A. Wolff, D. Kaiser, W. Mehr, G. Lupina
Journal of Vacuum Science and Technology B B33, 01A110 (2015)
(Graphen)
Chemical Vapor Deposition (CVD) was applied to grow dielectric HfO2 layers on graphene/SiO2/Si and graphene/TiN/Si reference substrates directly, i.e., without a seed layer or any other functionalization of graphene. It was found that the presence of bilayer and (generally) multilayer graphene islands on nominally monolayer graphene strongly impacts the nucleation and the growth of HfO2. No damage inflicted by the CVD process on the graphene could be detected by Raman spectroscopy. According to X-Ray Diffraction (XRD), the films grown on graphene at 400 °C and having thickness between 5 and 50 nm were polycrystalline. Electrical measurements were performed for MIM capacitors produced by evaporating Au and TiN top electrodes on the HfO2 film. Leakage currents were in the range of 10- 8 A/cm2 at 1 V for 50 nm HfO2 grown on graphene, exceeding by one order of magnitude the currents measured for the reference HfO2/TiN MIM structures. The films grown on graphene have a dielectric constant of 17 with a quality factor of 50.

(60) Residual Metallic Contamination of Transferred Chemical Vapor Deposited Graphene
G. Lupina, J. Kitzmann, I. Costina, M. Lukosius, Ch. Wenger, A. Wolff, S. Vaziri, M. Östling, I. Pasternak, A. Krajewska, W. Strupinski, S. Kataria, A. Gahoi, M.C. Lemme, G. Ruhl, G. Zoth, O. Luxenhofer, W. Mehr
ACS Nano 9, 4667 (2015)
(Graphen)
Integration of graphene with Si microelectronics is very appealing by offering potentially a broad range of new functionalities. New materials to be integrated with Si platform must conform to stringent purity standards. Here, we investigate graphene layers grown on copper foils by chemical vapor deposition and transferred to silicon wafers by wet etch and electrochemical delamination methods with respect to residual sub-monolayer metallic contaminations. Regardless of the transfer method and associated cleaning scheme, time-of-flight secondary ion mass spectrometry and total reflection x-ray fluorescence measurements indicate that the graphene sheets are contaminated with residual metals (copper, iron) with a concentration exceeding 1013 atoms/cm2. These metal impurities appear to be partly mobile upon thermal treatment as shown by depth profiling and reduction of the minority charge carrier diffusion length in the silicon substrate. As residual metallic impurities can significantly alter electronic and electrochemical properties of graphene and can severely impede the process of integration with silicon microelectronics these results reveal that further progress in synthesis, handling, and cleaning of graphene is required on the way to its advanced electronic and optoelectronic applications.

(61) Synthesis of Graphene-Like Transparent Conductive Films on Dielectric Substrates using a Modified Filtered Vacuum Arc System
H. Lux, P. Siemroth, A. Sgarlata, P. Prosposito, M.A. Schubert, M. Casalboni, S. Schrader
Journal of Applied Physics 117, 195304 (2015)
(Graphen)
Here, we present a reliable process to deposit transparent conductive films on silicon oxide, quartz, and sapphire using a solid carbon source. This layer consists of partially ordered graphene flakes with a lateral dimension of about 5 nm. The process does not require any catalytic metal and exploits a high current arc evaporation (Φ-HCA) to homogeneously deposit a layer of carbon on heated substrates. A gas atmosphere consisting of Argon or Argon/Hydrogen blend acting as a buffer influences the morphology of the growing film. scanning tunneling microscopy, transmission electron microscopy, and Raman spectra were used for a thorough characterization of the samples in order to optimize the growth parameters. The best carbon layers have a surface resistance of 5.7x103Ω whereas the optical transparency of the coatings is 88% with an excellent homogeneity over areas of several cm2. Such results are compatible with most semiconductor fabrication processes and make this method very promising for various industrial applications.

(62) Vertical Optical Ring Resonators Fully Integrated with Nanophotonic Waveguides on Silicon-on-Insulator Substrates
A. Madani, M. Kleinert, D. Stolarek, L. Zimmermann, L. Ma, O.G. Schmidt
Optics Letters (OSA) 40, 3826 (2015)
We demonstrate full integration of vertical optical ring resonators with silicon nanophotonic waveguides on silicon-on-insulator substrates to accomplish a significant step toward 3D photonic integration. The on-chip integration is realized by rolling up 2D differentially strained TiO2 nanomembranes into 3D microtube cavities on a nanophotonic microchip. The integration configuration allows for out-of-plane optical coupling between the in-plane nanowaveguides and the vertical microtube cavities as a compact and mechanically stable optical unit, which could enable refined vertical light transfer in 3D stacks of multiple photonic layers. In this vertical transmission scheme, resonant filtering of optical signals at telecommunication wavelengths
is demonstrated based on subwavelength thickwalled microcavities. Moreover, an array of microtube cavities is prepared, and each microtube cavity is integrated with multiple waveguides, which opens up interesting perspectives toward parallel and multi-routing through a single-cavity device as well as high-throughput optofluidic sensing schemes.

(63) Reliability Aspects of TiSi-Schottky Barrier Diodes in a SiGe-BiCMOS Technology
A. Mai, A. Fox
Proc. European Solid-State Device Research Conference (ESSDERC 2015), 234 (2015)
(MPW)
Schottky barrier diodes (SBD) were integrated in a 0.25um SiGe BiCMOS technology. The SBDs were realized without additional process steps using the titanium silicide (TiSi) phase of the standard contact formation for the anode Schottky barrier. We observe specific parameter degradation after reverse anode voltage operation. Different parameters as series resistance, forward and leakage currents and design parameters like anode area, contact edge lengths and corners were evaluated in order to decrease this degradation. Maximum reverse operating voltages for a ten year life time and a maximum change of 10% for critical parameters were extrapolated for the worst operation conditions.

(64) Multifunctional Technology with Monolithic Integrated THz-, Photonic-and µ-Fluidic Modules
A. Mai, St. Lischke, M. Wietstruck, L. Zimmermann, M. Kaynak, B. Tillack
ECS Transactions 69(10), 47(2015)
In this paper we present a multifunctional technology platform with different monolithic integrated modules like THz devices, i.e. complementary SiGe heterojunction bipolar transistors, silicon
photonics components in particular Ge-PIN photo detectors and finally the wafer-level integration of μ-fluidic channels for sensor applications. Challenges during the monolithic integration of these different modules were reviewed and necessary process adaptations discussed in order to enable a co-integration.

(65) Group-IV CVD Epitaxy – Key Enabler for High Performance BiCMOS and Photonic Technologies
A. Mai, Y. Yamamoto, St. Lischke, A. Fox, B. Tillack
Proc. JSPS International Workshop Core-to-Core Program Atomically Controlled Processing for Ultra-large Scale Integration, abstr. book (2015)

(66) Optische Schnittstelle für photonische Wirebonds in photonischer BiCMOS-Technologie
Ch. Mai, St. Lischke, M. Kroh, T. Hoose, N. Lindenmann, C. Koos, A. Mai, L. Zimmermann
Proc. MikroSystemTechnik Kongress (MST 2015), (2015)
(PHOIBOS)
Es wird ein Prozess zur Freilegung inverser Taper präsentiert, der die Nutzung photonischer Wirebonds (PWB) in PIC- (photonic integrated circuit) und ePIC- (electronic photonic integrated circuit) Umgebungen ermöglicht. Ein effektiver Verlust von zwei freigelegten Tapern (Höhe = 220nm, Breite = 185nm, Länge = 80μm) und dem verbindenden PWB konnte auf 3dB bestimmt werden.

(67) J-Band Amplifier Design using Gain-Enhanced Cascodes in 0.13 µm SiGe
S. Malz, B. Heinemann, R. Lachner, U. Pfeiffer
International Journal of Microwave and Wireless Technologies 7(3/4), 339 (215)
(Dotseven)

(68) Modular Integration of Annular TSV Structures filled with Tungsten in a 0.25 µm BiCMOS Technology
St. Marschmeyer, J. Berthold, A. Krüger, M. Lisker, A. Scheit, S. Schulze, A. Trusch, M. Wietstruck, D. Wolansky
Microelectronic Engineering 137, 153 (2015)
The through silicon via (TSV) technology is a key solution for enhancement of functionality and performance of integrated chips. The replacement of bond wires by TSVs is a new possibility to create a low parasitic ground for high frequency applications. Therefore, we implemented TSVs filled with tungsten in our high frequency 0.25 µm SiGe:C BiCMOS technology. Here, we demonstrate our concept for integration of annular TSVs with a depth of 75 µm and a width of 3 µm. Due to the many additional plasma processes for the TSV fabrication, we controlled the validity of the gate oxide of MOS transistors by measurement of electrical parameters which are sensitive to plasma induced damage (PID). Additionally, we performed hot carrier injection (HCI) test. But we did not found any difference in the performance of the MOS transistors depending on TSV fabrication.

(69) High-Speed Fabry-Pérot Optical Modulator in Silicon with 3 μm Diode
St. Meister, H. Rhee , A. Al-Saadi, B.A. Franke, S. Kupijai, C. Theiss, H.J. Eichler, B. Tillack, L. Zimmermann, H.H. Richter, D. Stolarek, M. Lesny, C. Meuer, C. Schubert, U. Woggon
IEEE Journal of Lightwave Technology 33(4), 878 (2015)

(70) Above 16 % Efficient Sequentially Grown Cu(In,Ga)(Se,S)2-Based Solar Cells with Atomic Layer Deposited Zn(O,S) Buffers
S. Merdes, F. Ziem, T. Lavrenko, T. Walter, I. Lauermann, M. Klingsporn, S. Schmidt,F. Hergert, R. Schlatmann
Progress in Photovoltaics: Research and Applications 23(11), 1493 (2015)
(PVcomB)
We report the development of Cd-free buffers by atomic layer deposition for chalcopyrite-based solar cells. Zn(O,S) buffer layers were prepared by atomic layer deposition on sequentially grown Cu(In,Ga)(Se,S)2 absorbers from Bosch Solar CISTech GmbH. An externally certified efficiency of 16.1% together with an open circuit voltage of 612 mV were achieved on laboratory scale devices. Stability tests show that the behavior of the ALD-Zn(O,S)-buffered devices can be characterized as stable only showing a minor drift of the open circuit voltage and the fill factor.

(71) Atomically Controlled Processing for Germanium-Based CVD Epitaxial Growth
J. Murota, Y. Yamamoto, B. Tillack
ECS Transactions 67(1), 135 (2015)

(72) A Comprehensive Study of the Impact of Dislocation Loops on Leakage Currents in Si Shallow Junction Devices
C. Nyamhere, A. Scheinemann, A. Schenk, A. Scheit, F. Olivie, F. Cristiano
Journal of Applied Physics 118, 184501 (2015)
In this work, the electrical properties of dislocation loops and their role in the generation of
leakage currents in p-n or Schottky junctions were investigated both experimentally and through
simulations. Deep Level Transient Spectroscopy (DLTS) reveals that the implantation of silicon
with 2  1015 Ge cm2 and annealing between 1000 C and 1100 C introduced two broad electron
levels EC  0.38 eV and EC  0.29 eV in n-type samples and a single broad hole trap EV þ
0.25 eV in the p-type samples. These trap levels are related to the extended defects (dislocation
loops) formed during annealing. Dislocation loops are responsible for the significant increase of
leakage currents which are attributed to the same energy levels. The comparison between structural
defect parameters and electrical defect concentrations indicates that atoms located on the
loop perimeter are the likely sources of the measured DLTS signals. The combined use of defect
models and recently developed DLTS simulation allows reducing the number of assumptions and
fitting parameters needed for the simulation of leakage currents, therefore improving their predictability.
It is found that simulations based on the coupled-defect-levels model reproduce well
the measured leakage current values and their field dependence behaviour, indicating that leakage
currents can be successfully simulated on the exclusive basis of the experimentally observed
energy levels.

(73) Fabrication of GeSn-Multiple Quantum Wells by Overgrowth of Sn on Ge by using Molecular Beam Epitaxy
F. Oliveira, I. A. Fischer, A. Benedetti, P. Zaumseil, M. F. Cerqueira, M. I. Vasilevskiy, S. Stefanov, S. Chiussi, J. Schulze
Applied Physics Letters 107, 262102 (2015)
We report on the fabrication and structural characterization of epitaxially grown ultra-thin layers of Sn on Ge virtual substrates (Si buffer layer overgrown by a 50 nm thick Ge epilayer followed by an annealing step). Samples with 1 to 5 monolayers of Sn on Ge virtual substrates were grown using solid source molecular beam epitaxy and characterized by atomic force microscopy. We determined the critical thickness at which the transition from two-dimensional to three-dimensional growth occurs. This transition is due to the large lattice mismatch between Ge and Sn (≈14.7%). By depositing Ge on top of Sn layers, which have thicknesses at or just below the critical thickness, we were able to fabricate ultra-narrow GeSn multi-quantum-well structures that are fully embedded in Ge. We report results on samples with one and ten GeSn wells separated by 5 and 10 nm thick Ge spacer layers that were characterized by high resolution transmission electron microscopy and X-ray diffraction. We discuss the structure and material intermixing observed in the samples.

(74) Ultra-Wideband SiGe BiCMOS LNA for W-band Applications
E. Öztürk, M. Seyyedesfahlan, M. Kaynak, E. Tekin
Microwave and Optical Technology Letters 57(6), 1274 (2015)

(75) Optimized Graphene Growth on Ge(100)/Si(100) Substrates
I. Pasternak, I. Jozwik, M. Lukosius, Y. Yamamoto, A. Przewloka, G. Lupina, W. Strupinski
Proc. Graphita 2015, (2015)

(76) Optimized Graphene Growth on Ge(100)/Si(100) Substrates
I. Pasternak, M. Lukosius, Y. Yamamoto, A. Krajewska, G. Lupina, W. Strupinski
Proc. Graphene 2015, (2015)

(77) Phase-Sensitive Optical Processing in Silicon Waveguides
K. Petermann, A. Gajda, G. Dziallas, M. Jazayerifar, L. Zimmermann, B. Tillack, F. Da Ros, D. Vukovic, K. Dalgaard, M. Galili, C. Peucheret
Proc. Optical Fiber Communications Conference and Exposition (OFC 2015), Tu2F.4 (2015)
(SFB787)
Abstract: Parametric optical signal processing is reviewed for silicon nano-rib-waveguides with a
reverse-biased pin-junction. Phase-sensitive parametric amplification with a phase-sensitive
extinction of more than 20 dB has been utilized for the regeneration of DPSK signals.
OCIS codes: (130.3120) Integrated optics devices; (190.4360) Nonlinear optics devices; (190.4975) Parametric processes;
(230.7405) Wavelength conversion devices

(78) Analysis of Optical and Electrical Trade-Offs for High-Speed Operation of Traveling-Wave Depletion-Type Si Mach-Zehnder Modulators
D. Petousi, L. Zimmermann, A. Gajda, M. Kroh, K. Voigt, G. Winzer, B. Tillack, K. Petermann
IEEE Journal of Selected Topics in Quantum Electronics 21(4), 3400108 (2015)
Fundamental limiting factors regarding high-speed performance of broadband depletion-type silicon (Si) Mach–Zehnder modulators (MZMs) are studied. Optical and electrical measurements of MZMs with traveling wave electrodes (TWE) reveal significant dependences between optoelectrical bandwidth and design parameters. An equivalent circuit model is implemented to fit measured modulator characteristics. Using the model, the limits of TWE depletion-type Si MZM systems are studied under the requirement of specific driving voltage. By comparing phase shifters with different doping concentration or junction position, we explore the fundamental optical and electrical tradeoffs which are limiting high-speed operation.

(79) A Novel Program-Verify Algorithm for Multi-bit Operation in HfO2 RRAM
F.M. Puglisi, Ch. Wenger, P. Pavan
IEEE Electron Device Letters 36(10), 1030 (2015)
(Panache)
In this letter, we propose a dispersion-aware program-verify algorithm to enable reliable multi-bit operations in HfO2-based RRAM. The significant intrinsic dispersion of the resistive states, typically hindering multi-bit operations, is exploited to devise a program-verify scheme which enables the multi-bit operations with unique properties of failure resilience and adaptability to degradation. We show that an appropriate choice of the algorithm parameters can minimize the average
number of cycles needed to program the cell, enabling fast and
reliable multi-bit operation. This maximizes the bit/cell ratio and
minimizes the dispersion of targeted resistive states.

(80) 30 GHz RF-MEMS Dicke Switch Network and a Wideband LNA in a 0.25 µm SiGeBiCMOS Technology
S. Reyaz, C. Samuelsson, A. Gustafsson, R. Malmqvist, R. Jonsson, M. Kaynak, A. Rydberg
Advances in Microelectronic Engineering (AIME) 3, 1 (2015)
(Nanotec)

(81) A 40 Gb/s 4 Vpp IQ Modulator Driver in 0.13 μm SiGe:C BiCMOS Technology for 25 Ω Mach Zehnder Modulators
P. Rito, I. Garcia Lopez, D. Micusik, J. Borngräber, L. Zimmermann, A.C. Ulusoy and D. Kissinger
Proc. IEEE MTT-S International Microwave Symposium (IMS 2015), (2015)
(SASER)
In this work, a modulator driver in 0.13 μm SiGe:C BiCMOS technology for 25 Ω travelling wave electrode (TWE) Mach-Zehnder Modulators (MZM) is presented. The design integrates two channels for differential driving of IQ signals. The driver delivers a differential output signal of 4 Vpp, exhibits a differential gain of 12 dB and has an output return loss of more than 9 dB. It works from a 4.7 V supply and dissipates 1.1 W/channel. Data rate of 40 Gb/s is demonstrated through measurements. To the best knowledge of the authors, this is the first time a design of a driver suitable for 25 Ω TWE MZMs is presented.

(82) A 246 GHz Fundamental Source with a Peak output Power of 2.8 dBm
N. Sarmah, B. Heinemann, U.R. Pfeiffer
Proc. 10th European Microwave Integrated Circuits Conference (EuMIC 2015), 186 (2015)
(Dotseven)

(83) 500 GHz Sensor System in SiGe for Gas Spectroscopy
K. Schmalz, P. Neumaier, R. Wang, J. Borngräber, W. Debski, M. Kaynak, D. Kissinger, H.-W. Hübers
Proc. 40th International Conference on Infrared, Millimeter and Terahertz Waves (IRMMW-THz 2015), (2015)
(Telediagnostics)
A 500 GHz sensor system for gas spectroscopy is presented, which includes a SiGe transmitter (TX) array and a SiGe receiver (RX). The integrated local oscillators of the TX-array and RX chips are controlled by two external phase-locked loops (PLL). The reference frequency of the TX-array PLL is modulated for 2f absorption spectroscopy (second harmonic detection). The performance of the sensor system is demonstrated by the 2f absorption spectra of methanol and acetonitrile.

(84) Turning Sample into (Re)solution: Focused Ion Beam shaped Solid Immersion Lenses
P. Scholz, M. Sadowski, S. Kupijai, M. Henniges, Ch. Theiss, St. Meister, D. Stolarek, H.H. Richter, M. Boostandoost, Ch. Boit
Proc. International Symposium for Testing and Failure Analysis (ISTFA 2015), 66 (2015)
(SILIMOD)

(85) CMOS-Compatible Purely Capacitive Interfaces for High-Density In-Vivo Recording from Neural Tissue
S. Schröder, C. Cecchetto, S. Keil, M. Mahmud, E. Brose, Ö. Dogan, G. Bertotti, D. Wolansky, B. Tillack, J. Schneidewind, H. Gargouri, M. Arens, J. Bruns, B. Szyszka, S. Vassanelli, R. Thewes
Proc. IEEE Biomedical Circuits and Systems Conference (BioCas 2015), (2015)

(86) Three Dimensional ALD of TiO2 for In-Vivo Biomedical Sensor Applications
S. Schröder, Ö. Dogan, J. Schneidewind, G. Bertotti, St. Keil, H. Gargouri, M. Arens, E. Brose, J. Bruns, D. Wolansky, B. Tillack, St. Vassanelli, B. Szyzka, R. Thewes
Proc. 2015 6th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), 21 (2015)

(87) A PEDA Approach for Monolithic Photonic BiCMOS Technologies
S. Simon, G. Winzer, H. Roßmann, M. Kroh, L. Zimmermann, Th. Mausolf
Proc. SPIE Microtechnologies - Integrated Photonics: Materials, Devices, and Applications III, 9520, 95200F-1 (2015)
(MERMIG)
The paper describes a novel approach to photonic electronic design automation (PEDA) based on the commercial design suite Laytools for circuit and physical layout design and simulation. The goal of this work is the integration of an electronic-photonic design flow into an existing electronic design automation (EDA) tool. Contrary to other solutions, with this approach, it is possible to minimize the required interfaces to other third party tools. In addition to existing electronic device models, photonic components are described with behavioral models. The mask layout has been extended to the needs of the electronic photonic integrated circuit (ePIC) designer and the verification flow was adapted to the photonic structures.

(88) A PEDA Approach for Monolithic Photonic BiCMOS Technologies
S. Simon, G. Winzer, H. Roßmann, M. Kroh, L. Zimmermann, Th. Mausolf
Proc. SPIE Microtechnologies - Integrated Photonics: Materials, Devices, and Applications III, 9520, 95200F-1 (2015)
(SITOGA)
The paper describes a novel approach to photonic electronic design automation (PEDA) based on the commercial design suite Laytools for circuit and physical layout design and simulation. The goal of this work is the integration of an electronic-photonic design flow into an existing electronic design automation (EDA) tool. Contrary to other solutions, with this approach, it is possible to minimize the required interfaces to other third party tools. In addition to existing electronic device models, photonic components are described with behavioral models. The mask layout has been extended to the needs of the electronic photonic integrated circuit (ePIC) designer and the verification flow was adapted to the photonic structures.

(89) A PEDA Approach for Monolithic Photonic BiCMOS Technologies
S. Simon, G. Winzer, H. Roßmann, M. Kroh, L. Zimmermann, Th. Mausolf
Proc. SPIE Microtechnologies - Integrated Photonics: Materials, Devices, and Applications III, 9520, 95200F-1 (2015)
(SASER)
The paper describes a novel approach to photonic electronic design automation (PEDA) based on the commercial design suite Laytools for circuit and physical layout design and simulation. The goal of this work is the integration of an electronic-photonic design flow into an existing electronic design automation (EDA) tool. Contrary to other solutions, with this approach, it is possible to minimize the required interfaces to other third party tools. In addition to existing electronic device models, photonic components are described with behavioral models. The mask layout has been extended to the needs of the electronic photonic integrated circuit (ePIC) designer and the verification flow was adapted to the photonic structures.

(90) A PEDA Approach for Monolithic Photonic BiCMOS Technologies
S. Simon, G. Winzer, H. Roßmann, M. Kroh, L. Zimmermann, Th. Mausolf
Proc. SPIE Microtechnologies - Integrated Photonics: Materials, Devices, and Applications III, 9520, 95200F-1 (2015)
(RF2THzSiSoC)
The paper describes a novel approach to photonic electronic design automation (PEDA) based on the commercial design suite Laytools for circuit and physical layout design and simulation. The goal of this work is the integration of an electronic-photonic design flow into an existing electronic design automation (EDA) tool. Contrary to other solutions, with this approach, it is possible to minimize the required interfaces to other third party tools. In addition to existing electronic device models, photonic components are described with behavioral models. The mask layout has been extended to the needs of the electronic photonic integrated circuit (ePIC) designer and the verification flow was adapted to the photonic structures.

(91) A PEDA Approach for Monolithic Photonic BiCMOS Technologies
S. Simon, G. Winzer, H. Roßmann, M. Kroh, L. Zimmermann, Th. Mausolf
Proc. SPIE Microtechnologies - Integrated Photonics: Materials, Devices, and Applications III, 9520, 95200F-1 (2015)
(MOSAIC)
The paper describes a novel approach to photonic electronic design automation (PEDA) based on the commercial design suite Laytools for circuit and physical layout design and simulation. The goal of this work is the integration of an electronic-photonic design flow into an existing electronic design automation (EDA) tool. Contrary to other solutions, with this approach, it is possible to minimize the required interfaces to other third party tools. In addition to existing electronic device models, photonic components are described with behavioral models. The mask layout has been extended to the needs of the electronic photonic integrated circuit (ePIC) designer and the verification flow was adapted to the photonic structures.

(92) Lateral Solid Phase Epitaxy of Amorphously Grown Si1 − xGex Layers on SiO2/Si(100) Substrates using In-Situ RPCVD Postannealing
O. Skibitzki, Y. Yamamoto, M.A. Schubert, B. Tillack
Thin Solid Films 593, 91(2015)
Lateral solid phase epitaxy (L-SPE) of non-doped or in-situ B-doped amorphous- (a-) SiGe with a-Si buffer deposited on SiO2 patterned Si(100) wafers by H2 postannealing in reduced pressure chemical vapor deposition system was investigated for possible heterojunction bipolar transistor (HBT) base link resistivity improvement. By using Si2H6 as Si precursor, epitaxial layer and amorphous layer were grown in mask window and on SiO2, respectively. By inserting a-Si buffer, the deposited a-SiGe surface became smoother. After L-SPE process, improved L-SPE length was observed due to suppressed random nucleation on SiO2. The L-SPE length increased with increasing postannealing time and saturated due to random poly-grain formation on the SiO2. At the same L-SPE time, increased L-SPE length was observed at higher temperature and at higher Ge concentration. With increasing B concentration in the a-SiGe, the L-SPE length increased until B concentration of 2x1019 atom/cm3, then deteriorated. These results of L-SPE process might have potential to improve dynamic performance of SiGe HBT by reducing base link resistivity by widening the monocrystalline region around bipolar window.

(93) A Class-E Tuned W-Band SiGe Power Amplifier With 40.4% Power-Added Efficiency at 93 GHz
P. Song, M.A. Oakley, A.C. Ulusoy, M. Kaynak, B. Tillack, G.A. Sadowy, J.D. Cressler
IEEE Microwave and Wireless Components Letters 25(10), 663 (2015)
A W-band power amplifier with Class-E tuning in a 0.13 µm SiGe BiCMOS technology is presented. Voltage swing beyond is enabled by the cascode topology, low upper base
resistance, and minimally overlapping current-voltage waveforms. At 93 GHz with 4.0 V bias, the peak power-added efficiency and saturated output power are measured to be 40.4% and 17.7 dBm, respectively. With the bias increased to 5.2 V, the peak poweradded efficiency and saturated output power at 93 GHz are measured to be 37.6% and 19.3 dBm, respectively.

(94) A Lens-Coupled 210-270 GHz Circularly Polarized FMCW Radar Transceiver Module in SiGe Technology
K. Statnikov, J. Grzyb, N. Sarmah, B. Heinemann, U.R. Pfeiffer
Proc. 10th European Microwave Integrated Circuits Conference (EuMIC 2015), 530 (2015)
(Dotseven)

(95) 160-GHz to 1-THz Multi-Color Active Imaging with a Lens-Coupled SiGe HBT Chip-Set
K. Statnikov, J. Grzyb, B. Heinemann, U.R. Pfeiffer
IEEE Transactions on Microwave Theory and Techniques 63(2), 520 (2015)
(Dotseven)
A 240-GHz monostatic circular polarized SiGe frequency-modulated continuous wave radar system based on a transceiver chip with a single on-chip antenna is presented. The radar transceiver front-end is implemented in a low-cost 0.13 mm SiGe HBT technology version with cut-off frequencies fT/fmax of 300/450 GHz. The transmit block comprises a wideband ×16 frequency multiplier chain, a three-stage PA, while the receive block consists of a low-noise amplifier, a fundamental quadrature down-conversion mixer, and a three-stage PA to drive the mixer. A differential branch-line coupler and a differential dualpolarized on-chip antenna are added on-chip to realize a fully integrated radar transceiver. All building blocks are implemented
fully differential. The use of a single antenna in the circular polarized radar transceiver leads to compact size and high sensitivity. The measured peak-radiated power from the Si-lens equipped radar module is +11 dBm (equivalent isotropically radiated power) at 246 GHz and noise figure is 21 dB. The characterization bandwidth of the radar transceiver is 60 GHz around the center frequency of 240 GHz, and the simulated Tx-to-Rx leakage is below 220 dB from 230 to 260 GHz.
After system calibration the resolution of the system to distinguish between two targets at different distance of 3.65 mm is
achieved, which is only 21% above the theoretical limit.

(96) Partially Slotted Ring Resonator with Ultra-High Quality Factor
P. Steglich, Ch. Mai, D. Stolarek, St. Lischke, S. Kupijai, C. Villringer, S. Pulwer, F. Heinrich, J. Bauer, D. Knoll, St. Meister, M. Casalboni, S. Schrader
IEEE Photonics Technology Letters 27(20), 2197 (2015)
(DELTA (TH Wildau))
Optical ring resonators based on slot waveguides are promising for several applications where an high device
tunability and and hence low power consumption are required. Slot waveguide ring resonators suffer, however,
from rather low optical quality factors due to optical losses mainly caused by sidewall roughness. This letter
proposes and experimentally demonstrates a novel ring resonator concept based on a partially slotted ring
including strip-to-slot mode-converter. An exceptional high quality factor of  105 was measured. The
proposed partially slotted ring resonator is expected to have various applications like integrated modulators,
switches, tunable lters, and on-chip photonic sensors.

(97) Novel Ring Resonator Concept Combining Strong Field Confinement with High Optical Quality Factor
P. Steglich, Ch. Mai, D. Stolarek, St. Lischke, S. Kupijai, C. Villringer, S. Pulwer, F. Heinrich, J. Bauer, D. Knoll, St. Meister, M. Casalboni, S. Schrader
IEEE Photonics Technology Letters 27(20), 2197 (2015)
(DELTA (TH Wildau))
Slot waveguide ring resonators appear promising candidates for several applications in silicon photonics. Strong field confinement, high device tunability, and low power consumption are beneficial properties compared to strip waveguides. Slot waveguide ring resonators suffer, however, from rather low optical quality factors due to optical losses. This letter proposes and experimentally demonstrates a novel concept based on a partially slotted ring and strip-to-slot mode-converter. An exceptional high quality factor of ~ 105 has been measured.

(98) RF-MEMS Switched W-Band mm-Wave Passive Imaging System in a 0.13 μm SiGe BiCMOS Technology
A. Strodl, S. Tolunay, V. Valenta, M. Kaynak, S. Reyaz, R. Johnson, W. Winkler, R. Malmqvist, H. Schumacher
Proc. International Symposium on RF MEMS and RF Microsystems (MEMSWAVE 2015), 64 (2015)
(Nanotec)

(99) 0.25 μm BiCMOS System-on-Chip with Four Transceivers for Ka-Band Active Reflectarrays
F. Tabarani, T. Chaloun, T. Purtova, M. Kaynak, H. Schumacher
Proc. SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC 2015), (2015)

(100) High Quality GeSn Layer Formation Due to Well-controlled Sn Migration at High Temperature
N. Taoka, G. Capellini, P. Zaumseil, I. Costina, M.A. Schubert, T. Schroeder
Proc. International Conference on Solid State Devices and Materials (SSDM 2015), 896 (2015)

(101) Non-Uniform Depth Distributions of Sn Concentration Induced by Sn Migration and Desorption during GeSnSi Layer Formation
N. Taoka, T. Asano, T. Yamaha, T. Terashima, O. Nakatsuka, I. Costina, P. Zaumseil, G. Capellini, S. Zaima, T. Schroeder
Applied Physics Letters 106, 061107 (2015)
The distributions of Sn concentration in GeSnSi layers formed on Ge substrate at various
temperatures were investigated. High deposition temperature (Td) induces significant Sn migration and desorption, which have activation energies of 0.75 eV and 0.27 eV, respectively. A model quantitatively clarified the Sn migration fluxes during the deposition, which increase not only with increasing Td but also with the layer thickness. A non-negligible Sn flux compared with the supplied flux was found at 350 °C at the surface of the 200-nm-thick layer. Consequently, designs of layer thickness and Td taking into account the appropriate Sn flux are important to form a GeSnSi layer with uniform Sn content for future optoelectronics.

(102) Sn Migration Control Based on Quantitative Prediction Using Simple Model for Aiming Sn-related Crystal Formation with Device Quality
N. Taoka, T. Asano, T. Yamaha, T. Terashima, O. Nakatsuka, I. Costina, G. Capellini, S. Zaima, T. Schroeder
Proc. JSPS International Workshop Core-to-Core Program Atomically Controlled Processing for Ultra-large Scale Integration, abstr. book (2015)

(103) 94 GHz RF–MEMS SPDT Switch in a 0.13 µm SiGe BiCMOS Technology
S. Tolunay, A. Göritz, M. Wietstruck, Ch. Wipf, B. Tillack, M. Kaynak
Proc. International Symposium on RF MEMS and RF Microsystems (MEMSWAVE 2015), 85 (2015)
(Nanotec)
A 94 GHz RF–MEMS based Single–Pole Double–Throw (SPDT) switch is fabricated in a 0.13 μm SiGe BiCMOS technology. The RF–MEMS SPDT shows excellent RF performance of 1.7 dB insertion loss and beyond state of the art isolation of 37 dB at 94 GHz. The RF-MEMS SPDT switch consists of two RF-MEMS Single–Pole Single–Throw (SPST) switches which has been developed and fabricated based on 3D electromagnetic (EM) simulations. The RF-MEMS SPST switch gives 0.87 dB insertion loss and 33 dB isolation at 94 GHz. The on–wafer S–parameter measurements at D–band (110–170 GHz) of both RF–MEMS SPST and SPDT switches are in very good agreement with EM simulations.

(104) High-Performance W-band LNA and SPDT Switch in 0.13 µm SiGe HBT Technology
A.C. Ulusoy, R.L. Schmid, M. Kaynak, B. Tillack, J.D. Cressler
Proc. of the Radio Wireless Symposium, 162 (2015)

(105) A SiGe D-Band Low-Noise Amplifier Utilizing Gain-Boosting Technique
A.C. Ulusoy, P. Song, W.T. Khan, M. Kaynak, B. Tillack, J. Papapolymerou, J.D. Cressler
IEEE Microwave and Wireless Components Letters 25(1), 61 (2015)
A D-band low-noise amplifier with gain boosting
is implemented in a 0.13 SiGe BiCMOS technology, occupying
0.4 mm of IC area. The circuit consists of two stages of
cascode amplifiers with inductive common-base termination,
which improves the gain by increasing the output impedance. The
measurements show more than 20 dB gain from 110 to 140 GHz,
consuming 12 mW of total dc power from a single voltage supply
of 2.0 V. The measured noise figure is within 5.5 to 6.5 dB in the
same frequency range. To the authors’ knowledge, these results
demonstrate the best silicon low-noise amplifier performance up
to date in this frequency range.

(106) Single-Chip Transmit-Receive Module with a Fully Integrated Differential RF-MEMS Antenna Switch and a High-Voltage Generator for F-Band Radars
V. Valenta, H. Schumacher, S. Tolunay Wipf, M. Wietstruck, A. Göritz, M. Kaynak, W. Winkler
Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2015), 40 (2015)
(Nanotec)
A single-chip solution for short-range F-band radar systems is presented. It is based on a Transmit-Receive (TR) module realized in a 130 nm BiCMOS process, with a fully integrated chain of Gilbert-cell frequency multipliers generating the required F-band carrier for both  transmit and receive paths, a differential Single-Pole-Double-Throw (SPDT) switch that relies on novel differential RF Micro-Electro-Mechanical (RFMEMS) switches and a High-Voltage (HV) generator providing the required charging and discharging 50 V signals for the RFMEMS switches. Thanks to a dedicated compensation strategy, the radar module can be packaged using low-cost techniques and wire-bonded to an off-chip antenna without compromising the
performance in the band of interest. To boost the link budget by 30 dB, dielectric lenses are used. Full functionality of the realized TR module has been experimentally confirmed, and
characterizations of the SPDT switch components, such as RFMEMS switch and balanced transmission lines were completed.
Keywords—SPDT, Frequency Multipliers, Radar, RF-MEMS, Dielectric Lense

(107) SciFab – a Wafer Level Heterointegrated InP DHBT/SiGe BiCMOS Process for mm-Wave Applications
N. Weimann, S. Hochheim, D. Rentner, D. Stoppel, M. Hossain, T. Al-Sawaf, V. Krozer, B. Janke, M. Lisker, A. Krüger, Ch. Meliani, B. Tillack
Proc. Compound Semiconductor Week (CSW 2015), (2015)
(SciFab)

(108) Graphene Based Electron Field Emitter
Ch. Wenger, J. Kitzmann, A. Wolff, M. Fraschke, Ch. Walczyk, G. Lupina, W. Mehr, M. Junige, M. Albert, J.W. Bartha
Journal of Vacuum Science and Technology B 33, 01A109 (2015)
(DFG-Graphen)
Graphene based electron field emitter arrays consisting of cone-shaped silicon tips, a thin Al2O3 tunnel barrier and Graphene top electrode are fabricated. Due to the monolayered Graphene top electrode, the electrons are able to tunnel through the Al2O3 layer and emit into the vacuum. The temperature behaviour of the tunnel leakage current as well as the emission current is characterized.

(109) Reliability of BiCMOS embedded MEMS Varactors for Wideband RF VCO Applications
M. Wietstruck, G. Kahmen, A. Göritz, S. Tolunay, B. Tillack, M. Kaynak
Proc. International Symposium on RF MEMS and RF Microsystems (MEMSWAVE 2015), 108 (2015)
(MEMS Integration)

(110) Monolithic Photonic-Electronic QPSK Receiver for 28 Gbaud
G. Winzer, M. Kroh, St. Lischke, D. Knoll, K. Voigt, H. Tian, Ch. Mai, D. Petousi, D. Micusik, L. Zimmermann, B. Tillack, K. Petermann
Proc. Optical Fiber Communications Conference and Exhibition 2015, M3C.4 (2015)
(SASER)
The paper presents the first fully monolithic photonic-electronic single-polarization
QPSK receiver for 56Gbps (28Gbaud). The receiver sub-system was realized in photonic
BiCMOS technology and demonstrates integration capabilities for state-of-the-art coherent
systems.

(111) Monolithic Photonic-Electronic QPSK Receiver for 28 Gbaud
G. Winzer, M. Kroh, St. Lischke, D. Knoll, K. Voigt, H. Tian, Ch. Mai, D. Petousi, D. Micusik, L. Zimmermann, B. Tillack, K. Petermann
Proc. Optical Fiber Communications Conference and Exhibition 2015, M3C.4 (2015)
(RF2THzSiSoC)
The paper presents the first fully monolithic photonic-electronic single-polarization
QPSK receiver for 56Gbps (28Gbaud). The receiver sub-system was realized in photonic
BiCMOS technology and demonstrates integration capabilities for state-of-the-art coherent
systems.

(112) Monolithic Photonic-Electronic QPSK Receiver for 28 Gbaud
G. Winzer, M. Kroh, St. Lischke, D. Knoll, K. Voigt, H. Tian, Ch. Mai, D. Petousi, D. Micusik, L. Zimmermann, B. Tillack, K. Petermann
Proc. Optical Fiber Communications Conference and Exhibition 2015, M3C.4 (2015)
(MERMIG)
The paper presents the first fully monolithic photonic-electronic single-polarization
QPSK receiver for 56Gbps (28Gbaud). The receiver sub-system was realized in photonic
BiCMOS technology and demonstrates integration capabilities for state-of-the-art coherent
systems.

(113) Monolithic Photonic-Electronic QPSK Receiver for 28 Gbaud
G. Winzer, M. Kroh, St. Lischke, D. Knoll, K. Voigt, H. Tian, Ch. Mai, D. Petousi, D. Micusik, L. Zimmermann, B. Tillack, K. Petermann
Proc. Optical Fiber Communications Conference and Exhibition 2015, M3C.4 (2015)
(SITOGA)
The paper presents the first fully monolithic photonic-electronic single-polarization
QPSK receiver for 56Gbps (28Gbaud). The receiver sub-system was realized in photonic
BiCMOS technology and demonstrates integration capabilities for state-of-the-art coherent
systems.

(114) Ternary and Quaternary Ni(Si)Ge(Sn) Contact Formation for Highly Strained Ge p- and n-MOSFETs
S. Wirths, R. Troitsch, G. Mussler, J.-M. Hartmann, P. Zaumseil, T. Schroeder, S. Mantl, D. Buca
Semiconductor Science and Technology 30, 055003 (2015)
The formation of new ternary NiGeSn and quaternary NiSiGeSn alloys has been investigated to
fabricate metallic contacts on high Sn content, potentially direct bandgap group IV
semiconductors. (Si)GeSn layers were pseudomorphically grown on Ge buffered Si(001) by
reduced pressure chemical vapor deposition. Ni, i.e. the metal of choice for source/drain
metallization in Si nanoelectronics, is employed for the stano-(silicon)-germanidation of highly
strained (Si)GeSn alloys. We show that NiGeSn on GeSn layers change phase from welloriented
Ni5(GeSn)3 to poly-crystalline Ni1(GeSn)1 at very low annealing temperatures. A large
range of GeSn compositions with Sn concentrations up to 12 at.%, and SiGeSn ternaries with
large Si and Sn compositions from 18%/3% to 4%/11% are investigated. In addition, the sheet
resistance, of importance for electronic or optoelectronic device contacts, is quantified. The
incorporation of Si extends the thermal stability of the resulting low resistive quaternary phase
compared to their NiGeSn counterparts.

(115) Advanced Germanium Epitaxy for Photonics Application
Y. Yamamoto, St. Lischke, L. Zimmermann, D. Knoll, J. Murota, B. Tillack
ECS Transactions 67(1), 123 (2015)
Investigations of low threading dislocation density (TDD) Ge growth
using reduced pressure chemical vapor deposition for photonics
application are reviewed. By interrupting the Ge growth process and
annealing for several times during Ge epitaxy (cyclic annealing),
TDD of below 1×106 cm42 is achieved for 4.7 μm thick Ge. Root
mean square of roughness below 0.5 nm is realized. Thin and low
TDD Ge layer fabrication is demonstrated by depositing thick Ge
with cyclic annealing process followed by HCl etching. Dislocation4
free area of local Ge on insulator is formed between [110] and [1410]
direction by lateral selective Ge growth in cavity between SiO2 cap
and buried oxide, which is formed by sacrificial Si etching. Using an
atomic4layer4doping approach, self4limitation of incorporated P dose
at ~1/4 monolayer is obtained offering heavy n4doping in Ge. P
diffusion suppression by delta4doped Si in Ge is observed. By Ge
growth followed by HCl etching process, photodiode with one order
of magnitude lower dark current compared to standard Ge growth
with cyclic annealing is fabricated.

(116) C and Si Delta Layer Formation in Ge by CH3SiH3 using RPCVD
Y. Yamamoto, N. Ueno, M. Sakuraba, J. Murota, B. Tillack
Proc. JSPS International Workshop Core-to-Core Program, Atomically Controlled Processing for Ultralarge Scale Integration, abstr. book (2015)

(117) C and Si Delta Doping in Ge by CH3SiH3 using RPCVD
Y. Yamamoto, J. Murota, B. Tillack
Proc. 9th International Conference on Silicon Epitaxy and Heterostructures (ICSI 2015), 147 (2015)

(118) Arsenic Atomic Layer Doping in Si Using AsH3
Y. Yamamoto, R. Kurps, J. Murota, B. Tillack
Solid State Electronics 110, 29 (2015)
Atomic layer doping of arsenic (As-ALD) in Si is investigated using a single wafer reduced pressure chemical vapor deposition tool. Hydrogen-free and hydrogen-terminated Si surfaces are exposed to AsH3 in the temperature range between 300 °C and 700 °C followed by Si capping using H2–SiH4 or H2–Si2H6 gas mixture at 450–700 °C. After exposing to AsH3 below 400 °C, no As spike formation is observed on both hydrogen-free and hydrogen-terminated Si surface. The incorporated As dose is increasing with increasing AsH3 exposure time and saturates. Before saturation, a higher As dose is observed at higher AsH3 partial pressure for the same AsH3 exposure time. As incorporation is not influenced by the precursor
(SiH4 or Si2H6) used for Si buffer deposition. By increasing SiH4 or Si2H6 partial pressure, a higher amount of As is incorporated at AsH3 exposed surface and a higher background doping of segregated As in the Si cap is observed. The slope of the segregated As is not influenced by the growth rate at 600 °C, which means that the As segregation seems to be under thermal equilibrium. Lower segregation of As in the Si cap is observed at lower Si cap growth temperature. The results shown here may offer a precise location and dose control of As into Si.

(119) Advanced Germanium Epitaxy for Photonics Application
Y. Yamamoto, St. Lischke, L. Zimmermann, D. Knoll, J. Murota, B. Tillack
Proc. ULSIC vs. TFT5 International Conference on Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors, (2015)

(120) High Quality Local GeOI Fabrication by Lateral Selective Growth of Germanium
Y. Yamamoto, M.A. Schubert, Ch. Reich, B. Tillack
Proc. 8th International Workshop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to-Core Program Joint Seminar "Atomically Controlled Processing for Ultralarge Scale Integration", (2015)

(121) Deposition of Iridium Thin Films on Three-Dimensional Structures with Plasma Enhanced Metalorganic Chemical Vapor Deposition
C.P. Yeh, M. Lisker, J. Bläsing, B. Kalkofen, O. Khorkhordin, E.P. Burte
Chemical Vapor Deposition 20, 1 (2015)
Iridium thin films are deposited on sub-micrometer three-dimensional trench structures by plasma-enhanced metal-organic chemical vapor deposition (PE-MOCVD). The iridium precursor used in this study is (ethylcyclopentadienyl)(1,5-cyclooctadiene)iridium [Ir (EtCp)(1,5-COD)]. Various process conditions at substrate temperatures from 300 °C to 450 °C, with and without plasma enhancement, are investigated and compared. Crystal structure of the deposited iridium films is analyzed by X-ray diffraction (XRD). Step coverage of the deposited iridium films on three-dimensional trench structures is analyzed by scanning electron microscopy (SEM). Surface morphology is quantitatively evaluated by atomic force microscopy (AFM) and the electrical resistivity of the deposited Ir films is measured by the four-point probe method.

(122) An Oscillator and a Mixer for 140-GHz Heterodyne Receiver Front-End based on SiGe HBT Technology
D. Yoon, K. Song, M. Kaynak, B. Tillack, J.-S. Rieh
Journal of Semiconductor Technology and Science 15(1) (2015)

(123) A D-Band Active Imager in a SiGe HBT Technology
D. Yoon, K. Song, J. Kim, M. Kaynak, B. Tillack, J.-S. Rieh
International Journal of Infrared and Millimeter Waves 36(4), 335 (2015)

(124) A Wideband H-Band Image Detector Based on SiGe HBT Technology
D. Yoon, M. Kaynak, B. Tillack, J.-S. Rieh
Journal of Electromagnetic Engineering and Science 15(1), 59 (2015)

(125) 3-D THz Tomography with an InP HBT Signal Source and a SiGe HBT Imaging Receiver Operating near 300 GHz
D. Yoon, J. Yun, J. Kim, K. Song, M. Kaynak, B. Tillack J.-S. Rieh
Proc. 40th International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz 2015), (2015)

(126) Engineering Interface-Type Resistive Switching in BiFeO3 Thin Film Switches by Ti Implantation of Bottom Electrodes
T. You, X. Ou, G. Niu, F. Bärwolf, G. Li, N. Du, D. Bürger, I. Skorupa, W. Yu, X. Wang, O.G. Schmidt, H. Schmidt
Scientific Reports 5, 18623 (2015)
BiFeO3 based MIM structures with Ti-implanted Pt bottom electrodes and Au top electrodes have been fabricated on Sapphire substrates. The resulting metal-insulator-metal (MIM) structures show bipolar resistive switching without an electroforming process. It is evidenced that during the BiFeO3 thin film growth Ti diffuses into the BiFeO3 layer. The diffused Ti effectively traps and releases oxygen vacancies and consequently stabilizes the resistive switching in BiFeO3 MIM structures. Therefore, using Ti implantation of the bottom electrode, the retention performance can be greatly improved with increasing Ti fluence. For the used raster-scanned Ti implantation the lateral Ti distribution is not homogeneous enough and endurance slightly degrades with Ti fluence. The local resistive switching investigated by current sensing atomic force microscopy suggests the capability of down-scaling the resistive switching cell to one BiFeO3 grain size by local Ti implantation of the bottom electrode.

(127) Two 320 GHz Signal Sources based on SiGe HBT Technology
J. Yun, D. Yoon, S. Jung, M. Kaynak, B. Tillack, J.-S. Rieh
IEEE Microwave and Wireless Components Letters 25(3), 178 (2015)

(128) SiGe Mediated Misfit Dislocation Free Epitaxial Growth of Ge on Nano-Structured Si Pillars
P. Zaumseil, Y. Yamamoto, M.A. Schubert, G. Capellini, M.H. Zoellner, O. Skibitzki, T. Schroeder
Proc. 9th International Conference on Silicon Epitaxy and Heterostructures (ICSI 9), 23 (2015)
(Ge Nanoheteroepitaxy)

(129) Tailoring the Strain in Si Nano-Structures for Defect-Free Epitaxial Ge over Growth
P. Zaumseil, Y. Yamamoto, M.A. Schubert, G. Capellini, O. Skibitzki, M.H. Zoellner, T. Schroeder
Nanotechnology 26(35), 355707 (2015)
(Ge Nanoheteroepitaxy)
We investigate the structural properties and strain state of Ge nano-structures selectively grown on Si pillars of about 60 nm diameter with different SiGe buffer layers. A matrix of TEOS SiO2 surrounding the Si nano-pillars causes a tensile strain in the top part at growth temperature of the buffer that reduces the misfit and supports a defect-free initial growth. Elastic relaxation plays the dominating role in the further increase of buffer thickness and following Ge deposition. This method leads to Ge nanostructures on Si that are free of misfit dislocations and other structural defects, which is not the case for direct Ge deposition on these pillar structures. The Ge content of the SiGe buffer is thereby not a critical parameter; it may vary over a relatively wide range.

(130) High-Resolution Characterization of the Forbidden Si (200) and (222) Reflection
P. Zaumseil
Journal of Applied Crystallography 48, 528 (2015)

(131) S-Parameter Characterization and Lumped-Element Modelling of mm-Wave Single-Drift IMPATT Diode
W. Zhang, Y. Yamamoto, M. Oheme, K. Matties, B. Tillack, E. Kasper, J. Schulze
Proc. International Conference on Solid State Devices and Materials (SSDM 2015), 802 (2015)

(132) BiCMOS Silicon Photonics Platform
L. Zimmermann, D. Knoll, M. Kroh, St. Lischke, D. Petousi, G. Winzer, Y. Yamamoto
Proc. Optical Fiber Communication Conference and Exposition/National Fiber Optic Engineers Conference (OFC/NFOEC 2015), TH4E.5 (2015)
(RF2THzSiSoC)

(133) FEOL Integration of Silicon- and Germanium-Based Photonics in Bulk-Silicon, High-Performance SiGe: C-BiCMOS Processes
L. Zimmermann, D. Knoll, B. Tillack
Photonics and Electronics with Germanium, Wiley Verlag, 5, 101 (2015)

(134) BiCMOS Silicon Photonics Platform
L. Zimmermann, D. Knoll, M. Kroh, St. Lischke, D. Petousi, G. Winzer, Y. Yamamoto
Proc. Optical Fiber Communication Conference and Exposition/National Fiber Optic Engineers Conference (OFC/NFOEC 2015), TH4E.5 (2015)
(SASER)

(135) Imaging Structure and Composition Homogeneity of 300 mm SiGe Virtual Substrates for Advanced CMOS Applications by Scanning X-ray Diffraction Microscopy
M.H. Zoellner, M.-I. Richard, G. Chahine, P. Zaumseil, Ch. Reich, G. Capellini, F. Montalenti, A. Marzegalli, Y.H. Xie, T.U. Schülli, M. Häberlen, P. Storck, T. Schroeder
ACS Applied Materials & Interfaces 7, 9031 (2015)
Advanced semiconductor heterostructures are at the very heart of many modern
technologies, including aggressively scaled complementary metal oxide semiconductor transistors for high performance computing and laser diodes for low power solid state lighting applications. The control of structural and compositional homogeneity of these semiconductor heterostructures is the key to success to further develop these state-of-the-art technologies. In this article, we report on the lateral distribution of tilt, composition, and strain across step-graded SiGe strain relaxed buffer layers on 300 mm Si(001) wafers treated with and without chemical−mechanical polishing. By using the advanced synchrotron based scanning X-ray diffraction microscopy technique K-Map together with micro-Raman spectroscopy
and Atomic Force Microscopy, we are able to establish a partial correlation between real space morphology and structural properties of the sample resolved at the micrometer scale. In particular, we demonstrate that the lattice plane bending of the commonly observed cross-hatch pattern is caused by dislocations. Our results show a strong local correlation between the strain
field and composition distribution, indicating that the adatom surface diffusion during growth is driven by strain field fluctuations induced by the underlying dislocation network. Finally, it is revealed that a superficial chemical−mechanical polishing of crosshatched
surfaces does not lead to any significant change of tilt, composition, and strain variation compared to that of as-grown samples.

(136) Accessing the Structural and Compositional Homogeneity of Strained Ge on SiGe Virtual Substrates by Scanning X-Ray Diffraction Microscopy
M.H. Zoellner, G. Chahine, M.-I. Richard, P. Zaumseil, Ch. Reich, M. Häberlen, G. Capellini, P. Storck, T.U. Schülli, T. Schroeder
Proc. International Conference on Silicon Epitaxy and Heterostructures (ICSI-2015), 37 (2015)

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.