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  • Publications 2019

Publications 2019

since January 2019

(1) Development and Mechanical Modeling of Si1-xGex/Si MQW Based Uncooled Microbolometers in a 130 nm BiCMOS
C. Baristiran Kaynak, A. Göritz, Y. Yamamoto, M. Wietstruck, M. Stocchi, K.E. Unal, M.B. Ozdemir, Y. Ozsoy, Y. Gurbuz, M. Kaynak
Proc. 20th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SIRF 2019), (2019)
(IHP-Sabanci Joint Lab)

(2) Contactless Parametric Characterization of Bandgap Engineering in FinFETs using Spectral Photon Emission
A. Beyreuther, I. Vogt, N. Herfurth, T. Nakamura, G.G. Fischer, B. Motamedi, C. Boit
Microelectronics Reliability 92, 143 (2019)
In the last decade it has become increasingly popular to use germanium enriched silicon in modern field effect transistors (FET) due to the higher intrinsic mobility of both holes and electrons in SiGe as compared to Si. Whether used in the source/drain region (S/D) as compressive stressor, which is an efficient mobility booster on Si channel devices, or as channel material, the SiGe increases channel carrier mobility and thus enhancing device performance. Because the germanium content modifies the effective bandgap energy EG, this material characteristic is an important technology performance parameter. The bandgap energy can be determined in an LED-like operation of electronic devices, requiring forward biased p-n junctions. P-n junctions in FETs are source or drain to body diodes, usually grounded or reversely biased. This investigation applies a bias to the body that can trigger parasitic forward operation of the source/drain to body p-n junction in any FET. Spectral photon emission (SPE) is used here as a non-destructive method to characterize engineered bandgaps in operative transistor devices, while the device remains fully functional.
Before applying the presented technique to a p-type FinFET device, it is put to the proof by verifying the nominal silicon bandgap on an (unstrained) 120nm technology FET. Subsequently the characterization capability for bandgap engineering is then successfully demonstrated on a SiGe:C heterojunction bipolar transistor (HBT). In a final step, the bandgap energy EG of a 14/16nm p-type FinFET was determined to be 0.84eV, which corresponds to a Si0.7Ge0.3 mixture. The presented characterization technique is a contactless fault isolation method that allows for quantitative local investigation of engineered bandgaps in p-type FinFETs.

(3) Comparative Study of Nano-Slot Silicon Waveguides Covered by Dye Doped and Undoped Polymer Cladding
S. Bondarenko, C. Villringer, P. Steglich
Applied Sciences 9(1), 89 (2019)
(HOPBIT)

(4) Finite-Element Modelling of Stress Induced Wafer Warpage for a Full BiCMOS Process
Z. Cao, A. Göritz, S. Tolunay Wipf, A. Trusch, M. Kaynak
Proc. 20th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2019), (2019)
(Bend-IT)
A finite element method (FEM) wafer scale model considering all the process details, e.g. metal patterning, via etching, etc., is built for a state-of-the-art 0.13-µm SiGe BiCMOS fully processed 8-inch wafer. Associated layer residual stress and wafer warpage are extracted and compared with hand calculation and experimental results. The comparison results show that the wafer warpage predicted by FEM model demonstrates only about 10 µm maximum deviation over an 80 µm-bowed wafer. An accurate stress model for an 8-inch wafer including full BiCMOS process is successfully developed and validated.

(5) Optical Phase Conjugation in a Silicon Waveguide with Lateral p-i-n Diode for Nonlinearity Compensation
F. Da Ros, A. Gajda, E.P. da Silva, A. Peczek, A. Mai, K. Petermann, E. Liebig, L. Zimmermann, L.K. Oxenlowe, M. Galili
IEEE Journal of Lightwave Technology 37(2), 323 (2019)
(SOPA ZI 1283/3-1)
In-line optical phase conjugation is a well-known technique to enhance the received signal quality through nonlinearity compensation. Being able to implement the conjugation in cm-scale highly nonlinear devices, which can be integrated on a silicon chip, could potentially lead to several benefits in terms of small footprint and cointegration with linear signal processing functionalities, as well as lower power consumption. Here, we focus on silicon waveguides to implement the optical phase conjugation through four-wave mixing. The challenges in terms of conversion efficiency imposed by the presence of nonlinear loss are tackled by using a lateral p-i-n diode along the waveguide. When the diode is reverse biased, the conversion efficiency can be effectively enhanced by the decrease in free-carrier absorption. Low-penalty conversion can therefore be achieved for wavelength-division multiplexing (WDM) signals and the high quality of the generated idlers is critical in demonstrating a 1-dB Q-factor improvement through optical phase conjugation in a 5-WDM channel 16-QAM transmission system after 644 km of dispersion-compensated transmission.
 

(6) Automated Extraction of Silicon Dioxide Thermal Conductivity Values Based on Electro-Thermal Simulations
A. Datsuk, F. Korndörfer, M. Kaynak, Z. Cao, K. Dhawan, V. Timoshenkov
Proc. IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus 2019), 1909 (2019)
(Design Kit)
Abstract — An approach to extract the silicon dioxide thermal conductivity values is presented. A variety of metal resistor test structures are produced using a 0.25 um SiGe BiCMOS technology. Based on the measured temperature rise values an automated extraction method to optimize the thermal conductivity of silicon dioxide is developed. Electrical and thermal co-simulations were performed for the optimization using the aforementioned test structures. The optimized thermal conductivity values were added to the material stack-up file and embedded in the process design kit. The updated material stack-up file allows designers to perform accurate computation of the metal structures and flip-chips. The maximum deviation of 8% between the electro-thermal simulations and the measurements is achieved.

(7) A Temperature Controller IC for Maximizing Si Micro-Ring Modulator Optical-Modulation-Amplitude
M.-H. Kim, L. Zimmermann, W.-Y. Choi
IEEE Journal of Lightwave Technology 37(4), 1200 (2019)
(Photonics)
We present a custom-designed integrated circuit (IC) implemented in 0.25-μm BiCMOS technology that can automatically control the Si micro-ring modulator (MRM) temperature for optimal modulation characteristics. The IC monitors the optical modulation amplitude (OMA) of a Si MRM and provides the optimal heater setting for the maximum OMA. The IC consists of trans-impedance amplifier, power detector, track-and-hold circuit, comparator, digital-to analog converter, and digital controller, all of which are integrated in a single chip. We demonstrate that, with this IC, a Si MRM can provide the maximum OMA for 25-Gb/s operation despite changes in temperature and input optical power.

(8) Processing and Integration of Graphene in a 200 mm Wafer Si Technology Environment
M. Lisker, M. Lukosius, M. Fraschke, J. Kitzmann, J. Dabrowski, O. Fursenko, P. Kulse, K. Schulz, A. Krüger, J. Drews, S. Schulze, D. Wolansky, A.M. Schubert, J. Katzer, D. Stolarek, I. Costina, A. Wolff, G. Dziallas, F. Coccetti, A. Mai
Microelectronic Engineering 205, 44 (2019)
(Graphen)
We present insights into processes of cleaning, patterning, encapsulation, and contacting graphene in a 200mm wafer pilot line routinely used for the fabrication of integrated circuits in Si technologies. We demonstrate key process steps and discuss challenges and roadblocks which need to be overcome to enable integration of this material with Si technologies.

(9) 64-GBd DP-Bipolar-8ASK Transmission over 120 km SSMF Employing a Monolithically Integrated Driver and MZM in 0.25-µm SiGe BiCMOS Technology
G.R. Mehrpoor, C. Schmidt-Langhorst, B. Wohlfeil, R. Elschner, D. Rafique, R. Emmerich, A. Dochhan, I. Lopez, P. Rito, D. Petousi, D. Kissinger, L. Zimmermann, C. Schubert, B. Schmauss, M. Eiselt, J.-P. Elbers
Proc. Optical Fiber Communications Conference and Exposition (OFC 2019), Tu2A.5 (2019)
(SPEED)
We demonstrate 64-GBd signal generation up to bipolar-8-ASK utilizing a single MZM,monolithically integrated with segmented drivers in SiGe. Using polarization multiplexing, 300-Gb/s net data rate transmission over 120 km SSMF is shown.

(10) Operando Diagnostic Detection of Interfacial Oxygen “Breathing” of Resistive Random Access Memory by Bulk-Sensitive Hard X-Ray Photoelectron Spectroscopy
G. Niu, P. Calka, P. Huang, S.U. Sharath, S. Petzold, A. Gloskovskii, K. Fröhlich, Y. Zhao, J. Kang, M.A. Schubert, F. Bärwolf, W. Ren, Z.-G. Ye,, E. Perez, C. Wenger, L. Alff, T. Schoeder
Materials Research Letters 7(3), 117 (2019)

(11) Test Beam Measurement of the First Prototype of the Fast Silicon Pixel Monolithic Detector for the TT-PET Project
L. Paolozzi, Y. Bandi, M. Benoit, R. Cardarelli, S. Debieux, D. Forshaw, D. Hayakawa, G. Iacobucci, M. Kaynak, A. Miucci, M. Nessi, O. Ratib, E. Ripiccini, H. Rücker, P. Valerio, M. Weber
Journal of Instrumentation 14(2), P02009 (2019)
The TT-PET collaboration is developing a PET scanner for small animals with 30 ps time-of flight resolution and sub-millimetre 3D detection granularity. The sensitive element of the scanner is a monolithic silicon pixel detector based on state-of-the-art SiGe BiCMOS technology. The first ASIC prototype for the TT-PET was produced and tested in the laboratory and with minimum ionizing particles. The electronics exhibit an equivalent noise charge below 600 e- RMS and a pulse rise time of less than 2 ns, in accordance with the simulations. The pixels with a capacitance of 0:8 pF were measured to have a detection efficiency greater than 99% and, although in the absence of the post-processing, a time resolution of approximately 200 ps.

(12) Shallow and Undoped Germanium Quantum Wells: A Playground for Spin and Hybrid Quantum Technology
A. Sammak, D. Sabbagh, N.W. Hendrickx, M. Lodari, B.P. Wuetz, A. Tosato, L. Yeoh, M. Bollani, M. Virgilio, M.A. Schubert, P. Zaumseil, G. Capellini,, M. Veldhorst, G. Scappucci
Advanced Functional Materials 1807613 (2019)

(13) Optical Biosensors Based on Silicon-On-Insulator Ring Resonator: A Review
P. Steglich, M. Hülsemann, B. Dietzel, A. Mai
Molecules 24(3), 519 (2019)
(HOPBIT)

(14) Inherent Stochastic Learning in CMOS Integrated HfO2 Arrays for Neuromorphic Computing
Ch. Wenger, F. Zahari, M.K. Mahadevaiah, E. Perez, I. Beckers, H. Kohlstedt, M. Ziegler
IEEE Electron Device Letters 40(4), 639 (2019)
(NeuroMem)

(15) RF-MEMS Based V-Band Impedance Tuner Driven by Integrated High-Voltage LDMOS Switch Matrix and Charge Pump
Ch. Wipf, R. Sorge, S. Tolunay Wipf, A. Göritz, A. Scheit, D. Kissinger, M. Kaynak
Proc. 20th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2019), (2019)
(LDMOS)
To demonstrate a fully integrated RF-MEMS based system including HV generation and switching circuitry, a V-Band (40 – 75 GHz) single-stub impedance tuner comprising four RF-MEMS switches, a 40V charge pump, and LDMOS based HV switches is developed in a 0.25μm SiGe-BiCMOS technology. The chip size of the designed impedance tuning circuit enables the integration into an on-wafer RF-probe used for noise parameter and load-pull measurements. With the embedded high-voltage generation and switching circuitry the wiring effort, which is necessary to control the integrated RF-MEMS based impedance tuning chip, can be drastically reduced. The operation of the on-chip high-voltage generation and switching circuitry is demonstrated by the measured S-parameters for various combinations of activated RF-MEMS switches. The four integrated RF-MEMS switches enable 16 impedance states in the frequency range between 40 GHz and 60 GHz.

(16) RF-MEMS Based V-Band Impedance Tuner Driven by Integrated High-Voltage LDMOS Switch Matrix and Charge Pump
Ch. Wipf, R. Sorge, S. Tolunay Wipf, A. Göritz, A. Scheit, D. Kissinger, M. Kaynak
Proc. 20th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2019), (2019)
(MEMS Integration)
To demonstrate a fully integrated RF-MEMS based system including HV generation and switching circuitry, a V-Band (40 – 75 GHz) single-stub impedance tuner comprising four RF-MEMS switches, a 40V charge pump, and LDMOS based HV switches is developed in a 0.25μm SiGe-BiCMOS technology. The chip size of the designed impedance tuning circuit enables the integration into an on-wafer RF-probe used for noise parameter and load-pull measurements. With the embedded high-voltage generation and switching circuitry the wiring effort, which is necessary to control the integrated RF-MEMS based impedance tuning chip, can be drastically reduced. The operation of the on-chip high-voltage generation and switching circuitry is demonstrated by the measured S-parameters for various combinations of activated RF-MEMS switches. The four integrated RF-MEMS switches enable 16 impedance states in the frequency range between 40 GHz and 60 GHz.

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.