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GALs interfAce for compleX digital sYstem integration


We propose to provide an integrated GALS (Globally Asynchronous, Locally Synchronous) design flow, together with novel Network-on-Chip capabilities, that will materially aid embedded system design for a significant class of problems. We aim to remove existing barriers to the adoption of the technology by providing an interoperability framework between the existing open and commercial CAD tools that will support development of heterogeneous systems at the different levels of abstraction.

The project will evaluate the ability of the GALS approach to solve system integration issues and, by implementing a complex wireless communication system on an advanced 45 nm CMOS process, explore the low EMI properties, inherent low-power features and robustness to process variability problems in nanoscale geometries.

IHP`s Contribution

  • Technical and administrative management of the project
  • Specifications and optimizations of GALS interfaces
  • Extension of our standard cell library for 130 nm CMOS process for asynchronous cells (mutex, C-element, etc.). Offering this extension over Europractice for research institutions working on asynchronous design
  • Investigating EMI in GALS-based systems. Evaluate the proposed EMI reduction algorithms theoretically and in practice. Fabrication of simple test chip in IHP 0.13 um CMOS process for evaluation of the developed techniques and algorithms.
  • Design, fabrication, testing and measurement of the GALS and synchronous version of the hardware accelerator for the state-of-the-art communication system developed in IHP. Fabrication will be done in 45 nm CMOS process provided from Infineon Technologies.


The project is founded by EU FP7.

Selected Publications

  • M. Krstic, Panel: Is networking the solution for interconnect design closure?, Panel membership and presentation at IP 07 IP/SoC Conference & Exhibition, Grenoble / France, December 2007.
  • M. Krstic, M.Piz, M. Ehrig, E. Grass: OFDM Datapath Baseband Processor for 1 Gbps Datarate; accepted paper to IFIP/IEEE VLSI-SoC Conference, Rhodes Island / Greece, October 2008.

External Links

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.