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TAMPRES

TAMper Resistant Sensor node

Objective

Design of a tamper resistant sensor nodes = resistance against physical attacks. ==> Improved trustworthiness OF THE FUTURE INTERNET OF THINGS due to protection of weakest link, I.E. THE SENSOR NODES.

  • Prevention of side-channel and fault-injection attacks: evaluation and development of appropriate counter measures considering the severe constraints of energy and silicon area.
  • Provision of flawless implementation of lightweight cryptographic cores: development of secure and properly implemented light-weight crypto cores to provide uncompromised cryptographic strength to higher layers.
  • Attack resistant system architecture: secure integration and partitioning of the whole system including hardware components and secure low level services.

IHP`s Contribution

  • Project Coordination
  • Crypto cores and trusted sensor node
  • Protection of debug and test interfaces (scan chain, JTAG) – patents pending
  • System Design, layout, integration and test of components
  • Fully working secure sensor node was fabricated in IHP technology

Funding

The project was funded by EU FP7 (258754).

 

 

External Links

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.