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Wireless Systems and Applications

Our Projects

The realization of the research programs is accomplished utilizing a project portfolio based on a medium-term roadmap. The project portfolio is regularly updated according to content requirements as well as through opportunities for cooperation and external funding.

Projects Overview

This program investigates and develops complex systems for wireless communication and their applications. The objective is finding solutions for hardware/ software systems on highly integrated single chips, Systems on a Chip (SoC) or Systems in a Package (SiP).


The target of high performance WLAN research is to achieve a data rate of up to 100 Gbps at carrier frequencies of up to 300 GHz. Additional important fields of research include the improvement of Quality of Service in the high load region as well as investigations to increase the reliability of WLANs for security-sensitive applications such as car-to-car communication.


The research on systems with low energy consumption is directed towards sensor networks on single chips or SoC. In this context new network architectures, distributed low resource middleware concepts, new energy efficient protocols for media access as well as energy-efficient transceivers are investigated and realized. UWB technologies based on IEEE 802.15.4a are examples of short-range wireless communication with an additional high spatial resolution. Research in context-sensitive middleware systems especially addresses privacy and security matters in using mobile devices. In this context, modular crypto processors for AES (Advanced Encryption Standard) as well as for different ECC (Elliptic Curve Cryptography) techniques are investigated and developed. Additionally, techniques for digital signature with different authenticity checks of wireless messages are investigated.


CMOS libraries for higher radiation hardness are investigated and realized in the context of higher reliability and testability of circuits. For digital designs different procedures for obtaining higher redundancy in critical paths are investigated. Furthermore, memory generators for different memory types are developed. Additional tasks are EDAC (Error Detection And Correction) techniques for data correction in memories and testing of all digital IHP-circuits as a service.


Prof. Rolf Kraemer


Im Technologiepark 25
15236 Frankfurt (Oder)


Heike Wasgien
Phone: +49 335 5625 342
Fax: +49 335 5625 671

Department System Design

Learn more about the Research Program`s associated Department.

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.