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  • Publications 2018

Publications 2018

since January 2018

(1) Robust and Low-Complexity Space Time Code for Industrial Automation
M. Abouzeid, M. Ehrig , N. Odhah , E. Grass, R, Kraemer
Proc. 10th International Conference on Advanced Infocomm Technology (ICAIT 2018), 105 (2018)

(2) Impact of Resistive Open and Bridge Defects on the SET Robustness of CMOS Combinational Logic
M. Andjelkovic, Z. Stamenkovic, M. Krstic, R. Kraemer
Proc. IEEE East-West Design & Test Symposium (EWDTS 2018), 28 (2018)
The robustness of standard CMOS combinational logic gates to Single Event Transients (SETs), in the presence of resistive open and resistive bridge defects, was studied. Analysis was performed with SPICE simulations, using the resistors for modeling the resistive defects, and a standard double-exponential current source for modeling the SET effects. Two circuits based on NAND gate, designed in IHP’s 130 nm CMOS process, were used as a case study. It was demonstrated that, for certain input logic levels, the intra- and inter-gate resistive open and bridge defects may lead to significant decrease of the logic gate’s critical charge, and hence to the increase of its soft error rate (SER) by more than one order of magnitude. Accordingly, the resistive defects result in wider SET pulses. Simulation results indicate that the intra- and inter-gate resistive open defects represent a more serious threat to the SET robustness of combinational logic than the resistive bridge defects.

(3) Study of the Operation and SET Robustness of a CMOS Pulse Stretching Circuit
M. Andjelkovic, M. Krstic, R. Kraemer
Microelectronics Reliability 82, 100 (2018)
This paper analyzes the normal response and the sensitivity to Single Event Transients (SETs) of a CMOS pulse
stretching circuit used for the SET pulse width measurement. The pulse stretcher based on two cascaded
asymmetrically sized inverters, designed in IHP's 130 and 250 nm bulk CMOS technologies, has been studied.
Results from SPICE simulations have confirmed that both the normal response (pulse stretching) and the SET
robustness (critical charge) of the pulse stretcher are dominantly influenced by the PMOS-to-NMOS sizing ratio.
In addition, the operation and SET robustness of the pulse stretcher are influenced by the load, operating
temperature, supply voltage variations, process corners and parasitic capacitances of interconnections. The typical
process-induced mismatch in transistors' sizes is not a critical issue in this case. It was demonstrated that
the multi-stage pulse stretching configuration is more suitable for obtaining wider pulses, but on the other hand
is more susceptible to SETs than the single-stage (two-inverter) pulse stretcher. Based on the acquired results, a
general approach for the design of a CMOS pulse stretcher, taking into consideration the impact of all analyzed
parameters on its normal response and SET robustness, has been proposed.

(4) Low-Complexity Framework for Movement Classification Using Body-Worn Sensors
D. Biswas, K. Maharatna, G. Panic, E.B. Mazomenos, J. Achner, J. Klemke, M. Jöbges, St. Ortmann
Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2018), (2018)
We present a low-complexity framework for classifying elementary arm-movements (reach-retrieve, lift-cup-tomouth, rotate-arm) using wrist-worn, inertial sensors. We propose
that this methodology could be used as a clinical tool to assess rehabilitation progress in neurodegenerative pathologies tracking occurrence of specific movements performed by patients with their paretic arm. Movements performed in a controlled training-phase are processed to form unique clusters in a multi-dimensional feature-space. Subsequent movements performed in an uncontrolled testing-phase are associated to the proximal cluster
using a minimum distance classifier (MDC). The framework involves performing the compute-intensive clustering of the training-dataset offline (Matlab) whereas the computation of
selected features on the testing-dataset and the minimum distance (Euclidean) from pre-computed cluster centroids are done in hardware with an aim of low-power execution on sensor nodes. The architecture for feature-extraction and MDC are realized using Coordinate Rotation Digital Computer based design which classifies a movement in (9n+31) clock cycles, n being number of data samples. The design synthesized in STMicroelectronics 130nm technology consumed 5.3 nW @50 HZ, besides being functionally verified upto 20 MHz, making it applicable for realtime high-speed operations within sensor node. Our experimental
results show that the system can recognize all three armmovements with average accuracies of 86% and 72% for healthy subjects using accelerometer and gyroscope data respectively,
whereas for stroke survivors the average accuracies were 62% and 57%. The framework was further demonstrated as a FPGA-based real-time system, interfacing with a streaming sensor unit.

(5) Engineering of Cross-Layer Fault Tolerance In Multiprocessing Systems
J.-C. Chen, M. Krstic
Proc. 8th Biannual European - Latin American Summer School on Design, Test and Reliability, (2018)
The increased design complexity and appearance of emerging embedded systems are leading to more pronounced challenges related to errors. Traditional approaches for addressing faults include the redundancy approaches in hardware, time, software, and /or information. But the overhead of these methods is not acceptable for many mixed-criticality applications, and consequently, we need some means to achieve the dynamical trade-off in safety, reliability, performance and power consumption. This paper presents the initial steps of a PhD work focusing on exploring the adaptive use of the fault tolerance mechanisms in multiprocessing architectures and development methods for adaptive cross-layer optimization approaches.

(6) Effects of Consecutive Irradiation and Bias Temperature Stress in p-channel Power Vertical Double-Diffused Metal Oxide Semiconductor Transistors
V. Davidovic, D. Dankovic, A. Ilic, I. Manic, S. Golubovic, S. Djoric-Veljkovic, Z.Prijic, A. Prijic, N. Stojadinovic
Japanese Journal of Applied Physics Pt. 1 57(4), 044101 (2018)
The mechanisms responsible for the effects of consecutive irradiation and NBT stress in p-channel power VDMOS transistors are presented in this paper. This investigation was performed in order to clarify the mechanisms responsible for the effects of specific kind of stress in devices previously subjected to the other kind of stress. In addition, it may help in assessing the behaviour of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to additional build-up of oxide trapped charge and interface traps, while NBT stress effects in previously irradiated devices depend on gate bias applied during irradiation and on the total dose received. In the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress leads to slight further device degradation. On the other hand, in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress may have a positive role, as it actually anneals a part of radiation-induced degradation.

(7) Design of Low-Bit Robust Analog-to-Digital Converters for Signals with Gaussian Distribution
M. Dincic, Z. Peric, D. Denic, Z. Stamenkovic
Proc. 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2018), 123 (2018)
This paper considers the design of robust logarithmic µ-law companding quantizers for the use in analog-to-digital converters in communication system receivers. Quantizers are designed for signals with the Gaussian distribution, since signals at the receivers of communication systems can be very well modeled by this type of distribution. In order to reduce energy consumption, low-resolution quantizers are considered (up to 5 bits per sample). The main advantage of these quantizers is high robustness - they can provide approximately constant SNR in a wide range of signal power (this is very important since the signal power at receivers can vary in wide range, due to fading and other transmission effects). Using the logarithmic µ-law companding quantizers there is no need for using AGC (automatic gain control), which reduces the implementation complexity and increases the speed of the analog-to-digital converters (ADC) due to the absence of AGC delay. Numerical results show that the proposed model achieves good performances, better than a uniform quantizer, especially in a wide range of signal power.

(8) Implementation and Analysis of Methods for Error Detection and Correction on FPGA
M. Dug, M. Krstic, D. Jokic
Proc. IFAC Conference on Programmable Devices and Embedded Systems (PDeS), (2018)

(9) Modular Wideband 1-15 GHz Transmitter Channelizer for High Data Rate Communication
M.H. Eissa, A. Malignaggi, G. Panic, L. Lopacinski, R. Kraemer, D. Kissinger
Proc. Global Symposium on Millimeter-Waves (GSMM 2018), (2018)
This work presents a modular wideband transmitter channelizer for THz-communications, manufactured in a 130nm SiGe:C BiCMOS technology with fT / fmax = 300 / 500 GHz. Three independent I/Q baseband signals are upconverted to different intermediate frequencies and then bonded in current domain. A local oscillator leakage cancellation functionality is implemented on chip within the input stage to enhance the dynamic range. Single ended inputs were utilized in order to reduce the pin count, for a more practical realization and higher potential toward future system scaling. The transmitter channelizer achieves an output 3-dB bandwidth of 15 GHz. LO rejection of 74 dBc at the center frequency was measured after calibration. It dissipates 355mW and occupies 1.5mm2. With these specifications the presented circuitry suits well as a practical solution for wideband channelization for THz-communications applications, with a potential scaling-up to higher number of channels.

(10) A Novel Adaptive Golay Correlator Synchronizer for IEEE 802.11ad Indoor mmWave Systems
A. El-Yamany, M. Petri
Proc. URSI International Symposium on Signals, Systems and Electronics (ISSSE 2018), (2018)

(11) An Adaptive IEEE 802.11ad Indoor mmWave Inner-Receiver Architecture
A. El-Yamany, M. Petri
Proc. URSI International Symposium on Signals, Systems and Electronics (ISSSE 2018), (2018)

(12) Statistical Properties and Variations of LOS MIMO Channels at Millimeter Wave Frequencies
T. Hälsig, D. Cvetkovski, E. Grass, B. Lankl
Proc. 22nd International ITG Workshop on Smart Antennas (WSA 2018), 1 (2018)
Measurement results for millimeter wave LOS MIMO systems are presented with a focus on time variation and multipath propagation. Different system setups are used, including 2x2 and 3x3 MIMO, and involving different synchronization procedures and front-ends. Furthermore, different propagation scenarios are evaluated, covering a wide area of applications. The results show that the LOS component carries significantly more power than the NLOS components, and that frequency selectivity from front-ends should be taken into account when designing these high bandwidth systems. Frequency offsets and other phase variations due to transmit and receive oscillator differences are treated as part of the channel and thus, depending on the synchronization setup, the MIMO system exhibits different time variations, particularly in the case of independent local oscillators. It is also observed that these systems experience significant non-trivial long-term variations in terms of amplitude and phase.

(13) Unified Field Multiplier for ECC: Inherent Resistance against Horizontal SCA Attacks
I. Kabin, Z. Dyka, D. Kreiser, P. Langendörfer
Proc. 13th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2018), (2018)

(14) Low-Cost and High Efficient Horizontal Attacks against ECDSA
I. Kabin, Z. Dyka, D. Kreiser, P. Langendörfer
Proc. 27th Crypto-Day, (2018)

(15) Horizontal Address-Bit DEMA against ECDSA
I. Kabin, Z. Dyka, D. Kreiser, P. Langendörfer
Proc. 9th IFIP International Conference on New Technologies, Mobility & Security (NTMS 2018), (2018)
With the advent of the Internet of Things security features become more and more important. Especially data integrity and authentication of its origin are of utmost importance. Digital signatures are a well-known means to provide these features. In this paper we detail our horizontal DEMA attack against a hardware implementation of the Montgomery kP algorithm for the NIST elliptic curve B-233. We apply the attack successfully against the ECDSA algorithm. In the past vertical attacks exploiting the key dependable activity of the bus and addressing of registers have been published. In contrast to those attacks we performed a horizontal attack exploiting the same phenomena using a single trace of electromagnetic emanations.

(16) Methods for Increasing the Resistance of Cryptographic Designs against Horizontal DPA Attacks
I. Kabin, Z. Dyka, D. Kreiser, P. Langendörfer
Proc. 19th International Conference on Information and Communications Security (ICICS 2017), Springer, LNCS 10631, 225 (2018)

(17) Improving DEMA Attack Results using Different Compression Methods
I. Kabin, Z. Dyka, D. Kreiser, P. Langendörfer
Proc. 27th Crypto-Day, 1 (2018)

(18) Disruptive Events in High-Density Cellular Networks
H.P. Keeler, B. Jahnel, O. Maye, D. Aschenbach, M. Brzozowski
Proc. Workshop on Spatial Stochastic Models for Wireless Networks (SpaSWiN'18), (2018)
Stochastic geometry models are used to study wireless networks, particularly cellular phone networks, but most of the research focuses on the typical user, often ignoring atypical events, which can be highly disruptive and of interest to network operators. We examine atypical events when an unexpected large proportion of users are disconnected or connected by proposing a hybrid approach based on ray launching simulation and point process theory. This work is motivated by recent results using large deviations theory applied to the signal-to-interference ratio. This theory provides a tool for the stochastic analysis of atypical but disruptive events, particularly when the density of transmitters is high. For a section of a European city, we introduce a new stochastic model of a single network cell that uses ray
launching data generated with the open source RaLaNS package, giving deterministic path loss values. We collect statistics on the fraction of (dis)connected users in the uplink, and observe that the probability of an unexpected large proportion of disconnected users decreases exponentially when the transmitter density increases. This observation implies that denser networks become more stable in the sense that the probability of the fraction of
(dis)connected users deviating from its mean, is exponentially small. We also empirically obtain and illustrate the density of users for network configurations in the disruptive event, which highlights the fact that such bottleneck behaviour not only stems from too many users at the cell boundary, but also from the near-far effect of many users in the immediate vicinity of the base station. We discuss the implications of these findings and outline possible future research directions.

(19) Low-Energy Key Exchange for Automation Systems
D. Kreiser, Z. Dyka, I. Kabin, P. Langendörfer
Proc. 13th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2018), (2018)
There is a clear trend towards the use of wireless communication in automation systems (AS). To make wireless communication systems usable for automation systems, it is crucial that they fulfil the strong requirements with respect to latency and security. For ensuring security features such as confidentiality and data integrity cipher algorithms are used. In this paper we focus on the most important operation in crypto-systems i.e. the key distribution. As the major part of the devices is resource constraint, energy efficiency is of utmost importance. In this paper we propose to combine the EC ElGamal encryption approach corresponding to [1] with the Montgomery kP algorithm using projective Lopez-Dahab coordinates [4] for realizing the key exchange. The proposed combination helps to reduce the energy needed for exchanging a shared secret key by 30 per cent. This is mainly achieved by reducing the number of bits to be transmitted.

(20) Implementation of a Latency Optimized ECC-Design
D. Kreiser, I. Kabin, Z. Dyka, C. Wittke, P. Langendörfer
Proc. 27th Crypto-Day 2017, (2018)

(21) Analysis of PSSS Modulation for Optimization of DAC Bit Resolution for 100 Gbps Systems
K. Krishnegowda, L. Wimmer, A. R. Javed, A. Wolf, C. Scheytt, R. Kraemer
Proc. 15th International Symposium on Wireless Communication Systems (ISWCS 2018), (2018)
The terahertz frequency range provides abundant
bandwidth (25GHz ~ 50 GHz) to achieve ultra-high-speed wireless
communication and enables data rates up to and above 100 Gbps.
We choose Parallel Sequence Spread Spectrum (PSSS) as an
analog friendly modulation and coding scheme that allows for an
efficient mixed-signal implementation of a 100 Gbps wireless
communication system. In our system design, we require a DAC
(Digital to Analog converters) running at 1.67 G symbols/sec. The
optimization of the bit resolution of this DAC will considerably
reduce the hardware implementation efforts. In this work, we
presented the analytical model for PSSS modulation and deduced
a mathematical formula to calculate the number of discrete level
amplitudes along with their probability distribution appearing at
the output of the PSSS modulated signal. The analytical analysis
assists in predicting the number of the quantization level of the
DAC needed at the PSSS transmitter. The theoretical analysis
shows that there are in total 225 discrete levels at the output of the
PSSS encoder which leads to an 8-bit resolution of DAC. In this
paper, we analyzed the variation of BER (Bit Error Rate) to the
clipping of low probability amplitude levels and found that there
is an only slight increase of the BER when we clip off the low
probability amplitude levels. Thus, there is a tradeoff involved in
a minor growth of BER concerning the reduction of the DAC bit
resolution. Finally, we can reduce the DAC bit resolution from 8
bits to 7 bits and thus simplify the hardware implementation
efforts of DAC operating at 1.67 Gbps

(22) High-Speed Channel Equalization Scheme for 100 Gbps System
K. KrishneGowda, R. Kraemer, A.C.Wolf, E.R.Bammidi
Proc. 19th International Conference on Industrial Technology (ICIT 2018), (2018)
In the terahertz frequency range, there is an abundance of bandwidth (25GHz ~ 50 GHz) available to achieve ultra-high-speed wireless communication and enabling data rates up to 100 Gbps. We choose Parallel Sequence Spread Spectrum (PSSS) as an analog friendly modulation and coding scheme that allows for an efficient mixed-signal implementation of a 100 Gbps wireless communication system. We have completed measurements using a 240 GHz RF Millilink front end combined with PSSS as baseband modulation scheme and evaluated channel estimates. In this paper, a high-speed channel equalization algorithm was designed and implemented on an FPGA as well as an ASIC. One of the main operations in performing channel equalization is to evaluate discrete Fourier transform (DFT) of channel estimates. This report examines the multidimensional DFT decomposition theory which is the transformation of a one dimensional DFT into two-dimensional DFT, whereby the index mapping is done using the Chinese remainder theorem. We have modified the prime factor algorithm (PFA) to perform a complex DFT on channel estimate samples. PFA decomposes a long transform DFT into several short transform DFTs which are implemented using a minimal amount of multiplications. By skipping the cumbersome process of evaluating twiddle factors, the result is a very suitable architecture for high-speed design. We have designed and implemented a high-speed channel equalization on a Vitrex Ultrascale FPGA running at 166.67 MHz with a low latency of only one clock cycle. We have also synthesized our design using the Synopsis DC Ultra tool with 40 nm NanGate open cell libraries. The design required 0.28 mm2 area, 21 mW power and runs with a clock frequency of 158 MHz.

(23) Evaluierung einer strahlungsharten Bibliothek in 0.13µm BiCMOS
M. Krstic, J. Schmidt, A. Breitenreiter, F. Teply, R. Sorge
Proc. DLR-Bauteilekonferenz 2018

(24) Power/Area-Optimized Fault Tolerance for Safety Critical Applications
M. Krstic, A. Simevski, M. Ulbricht, S. Weidling
Proc. IEEE International On-Line Testing Symposium (IOLTS 2018), 123 (2018)

(25) Heuristics for Page-based Incremental Reprogramming of Wireless Sensor Nodes
K. Lehniger, S. Weidling, M. Schölzel
Proc. 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2018), 61 (2018)
Wireless sensor nodes may need code updates for a variety of reasons. These updates are costly in terms of energy and can lead to early battery failure. Incremental reprogramming
can save energy by reusing the existing code image on the node and transmitting only a delta file. It can not be assumed that the flash memory is randomly erasable and programmable.
When updating the flash page by page, usable data could be unintentionally overwritten, which increases the size of the delta. This paper proposes heuristics for page-based incremental
reprogramming of wireless sensor nodes, to find a good sequence for pages in the flash memory to be updated that lead to an overall smaller delta file. A graph model for page dependencies is presented, graph-based algorithms are proposed and page dependency weights are estimated. Results show that the page update sequence can have a significant impact on the size of the delta file.

(26) Modeling and Analysis of Single-Event Transient Sensitivity of a 65 nm Clock Tree
Y.-Q. Li, L. Chen, I. Nofal, M. Chen, Q.-Y. Chen, H.-B. Wang, M. Krstic, S.-T. Shi, G. Guo, S.H. Baeg, S.-J. Wen, R. Wong
Microelectronics Reliability 87, 24 (2018)
The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS
technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.

(27) Flip-Flop SEUs Mitigation Through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle
Y.-Q. Li, A. Breitenreiter, M. Andjelkovic, O. Schrape, M. Krstic
Proc. 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2018), (2018)

(28) Implementation of a Multi-Core Data Link Layer Processor for THz Communication
L. Lopacinski, M.H. Eissa, G. Panic, M. Brzozowski, A. Hasani, R. Kraemer
Proc. 2018 IEEE 87th Vehicular Technology Conference (VTC 2018), (2018)
In this paper, we discuss the main challenges and our solutions proposed for implementation of a high-speed data link layer processor. Our target is to achieve processing throughput faster than 20 Gbps. Meanwhile a single core of our implementation achieves ‘only’ ~28 Gbps, we propose a multi-core solution that can run up to ~110 Gbps. For this purpose, we use baseband signal splitters and combiners. Alternatively, we come up with Parallel Sequence Spread Spectrum (PSSS). After splitting the input signal, we divide the required processing-effort among a set of parallel baseband and data link layer processors. The discussed data link layer processor uses hybrid-automatic-repeat-request-I (HARQ-I) with link adaptation and selective fragment repetitions. Such solution significantly improves the efficiency of the method and allows to reduce the implementation complexity when compared to HARQ-III. The main issue discussed in the article is power and energy consumption. Our solution consumes maximally 300 mW at 27.9 Gbps, including forward error correction (FEC) engine.

(29) Device Localization using mmWave Ranging with Sub-6-assisted Angle of Arrival Estimation
N. Maletic, V. Sark, J. Gutierrez, E. Grass
Proc. 13th IEEE International Symposium on Broadband Multimedia Systems and Broadcasting 2018, 128 (2018)
Millimeter wave (mmWave) communication is a promising solution for achieving high data rates and low latency in future wireless networks. 5G systems are expected to fulfill these strict requirements using, among others, mmWaves. The nature of the communication in these bands considering human mobility make the challenges even complex for reasons like high beam training overhead. Features like ranging and localization are becoming key to overcome these limitations. In this paper, we address the problem of device localization in the mmWave band. We propose a solution that leverages the co-existence of Sub-6 GHz and mmWave connectivity at access and mobile nodes. Our solution relies on the Angle of Arrival estimation using Sub-6 signal at the access node. This information is provided to the mmWave part for subsequent beam training phase and high-resolution ranging. To validate the proposed solution, number of measurements are performed showing its feasibility.

(30) A Methodology to Verify Digital IP’s Within Mixed-Signal Systems
N. Manjappa, A. Breitenreiter, M. Ulbricht, M. Krstic
Proc. 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2018), (2018)

(31) Improving Transistor Sizing for Asynchronous Circuits
F. Meinel, N. Kluge, R. Wollowski
Proc. 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2018), 1 (2018)

(32) A Fault Tolerant Dynamically Scheduled Processor with Partial Permanent Fault Handling
F. Mühlbauer, L. Schröder, M. Schölzel
Proc. 19th IEEE Latin-American Test Symposium (LATS 2018), (2018)

(33) Handling of Transient and Permanent Faults in Dynamically Scheduled Super-Scalar Processors
F. Mühlbauer, L. Schröder, M. Schölzel
Microelectronics Reliability 80, 176 (2018)
This article describes architectural extensions for a dynamically scheduled processor to enable three different operation modes, ranging from high-performance, to high-reliability. With minor extensions of the control path, the resources of the super-scalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. Furthermore, the online error-correction capabilities are combined with reconfiguration
techniques for permanent fault handling. This reconfiguration can take defective components out of operation permanently, and can be triggered on-demand during runtime, depending on the frequency of online corrected faults. A comprehensive fault simulation was carried out in order to evaluate hardware overhead, fault coverage and performance penalties of the proposed approach. Moreover, the impact of the permanent reconfiguration regarding the reliability and performance is investigated.

(34) Protection of Forests against Environmental Risks – the SCHUWA-Project
M. Natkhin, J. Müller, K. Piotrowski, Ch. Pistorius, K. Kronfeld
Proc. 19. ITG-/GMA-Fachtagung Sensoren und Messsysteme 2018, 30 (2018)
The presented sensor system shall detect and avert risks for the forest using existing monitoring and forecast systems. The aim of the sensor system is the supplementation and improvement of the existing monitoring networks in forestry. Main focus is on the prevention of forest fire, monitoring and anticipative forest management regarding extreme weather events. The system consists of a wireless sensor network and a control centre. The nodes are based on the IHPNode and communicate with each other on the 868 MHz band. The sensors in the network are low costs, low power consumption and robust.

(35) Adaptive Per-spatial stream Power Allocation Algorithms for Single-User MIMO-OFDM Systems
N.A. Odhah, E.S. Hassan, M.I. Dessouky, W.E. Al-Hanafy, S.A. Alshebeili, F.E. Abd El-Samie
Wireless Personal Communications 98, 1 (2018)

(36) A Radiation Hardened 16 GS/s Arbitrary Waveform Generator IC for THz-Range Chirp-Transform Spectrometer
P. Ostrovskyy, O. Schrape, K. Tittelbach-Helmrich, F. Herzel, G. Fischer, D. Hellmann, P. Börner, A.Loose, P. Hartogh, D. Kissinger
Proc. IEEE Nordic Circuits and Systems Conference (NORCAS 2018), (2018)
This paper describes a radiation hardening  design approach of a dual channel 16 GSps single chip arbitrary waveform generator - a complex mixed-signal ASIC - that consists of a low phase noise 16 GHz PLL, two 1.6 Mbit SRAM blocks, two multiplexing chains, and two 4-bit DACs. The ASIC is dedicated to be a part of a THz-range spectrometer that shall operate in a deep-space environment. Under stringent power budget conditions, a selective radiation protection of the ASIC has been applied. The arbitrary waveform generator fabricated in 130 nm SiGe BiCMOS process demonstrates the required functionality and can be further tested in an irradiation facility.

(37) Verification of an Embedded Sensor Node System-on-Chip
G. Panic
Proc. 7th Small Systems Simulation Symposium (SSSS 2018), 9 (2018)
In this paper the verification methodology for an embedded low power sensor node system-on-chip design has been presented. A mixed-signal, power-gated, processor-based sensor node microcontroller has been implemented and verified. The chip implements a number of peripherals, several analog components and a flash memory for program storage. The paper describes applied verification methodology including simulation steps, power analysis and chip measurements.

(38) Balancing Energy Production and Consumption in Energy Efficient Neighborhoods
K. Piotrowski, M.P.A. Geers, D. Garrido, J. Chen, A. Casaca, J.J. Peralta, M.E.T. Gerards
Proc. IEEE International Energy Conference (EnergyCon 2018) (2018)
This paper introduces a new energy management system for Smart Grids, designed in the European 7th framework program project e-balance. The architecture of the system is hierarchical and fractal-like, which results in better scalability and reusability of algorithms and programming code for energy management. The system is structured into two main parts – the communication platform and the energy management platform. The former provides a common data exchange layer, while the latter provides the local energy management logic, currently supporting energy balancing. The application of the system to balance production and consumption of electricity was evaluated in a pilot deployed in the Netherlands.

(39) The e-Balance Platform for Managing Energy in Smart Grids
K. Piotrowski, D. Garrido, J. Chen
Proc. 12th Conference on Measurment Systems in Research and Industry (SP2018), 119 (2018)
This paper presents an innovative energy management system for Smart Grids, designed in the European project e-balance. The architecture is hierarchical and fractal-like, what results in better scalability and reuse of algorithms for energy management. The flexible service concept allows implementing secure and future-proof energy management systems.

(40) Emulating Energy Grids using the e-balance Emulator
K. Piotrowski, P. Powroznik, W. Miczulski, R. Szulim
Proc. 12th Conference on Measurement Systems in Research and Industry (SP2018), 115 (2018)
Developing energy management algorithms faces a serious problem of a realistic test scenario. Emulating the energy grid is one of the possible ways to achieve that. This paper presents the e-balance smart grid emulator. It explains the idea behind, the current development status and the planned future steps.

(41) NLOS Identification for Indoor Localization using Random Forest Algorithm
M. Ramadan, V. Sark, J. Gutierrez Teran, E. Grass
Proc. 22nd International ITG Workshop on Smart Antennas (WSA 2018), (2018)

(42) Master-Clone Placement with Individual Clock Tree Implementation – a Case on Physical Chip Design
O. Schrape, A. Balashov, A. Simevski, C. Benito, M. Krstic
Proc. IEEE Nordic Circuits and Systems Conference (NorCAS 2018), (2018)

(43) D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop
O. Schrape, A. Breitenreiter, M. Andjelkovic, M. Krstic
Proc. Euromicro Conference on Digital System Design (DSD 2018), 201 (2018)

(44) Kombination von on-line und off-line Fehlerbehandlung in dynamisch geplanten Prozessoren
L. Schröder, F. Mühlbauer, M. Schölzel
Proc. 30. GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018), 36 (2018)

(45) Hardware/Software Co-verification Platform for Embedded Multiprocessors
A. Simevski
Proc. International Conference on Electronics, Telecommunications, Automation and Informatics (ETAI 2018), (2018)
A strategy and a platform for design and verification of embedded multiprocessor systems is presented. The hardware/software co-verification strategy significantly increases the confidence in the design of both hardware and software. Software verification can start very early in the design phase of the system, even when minimum functionality is achieved at the RTL (Register-Transfer Level), which besides significant reduction of the time-to-market of the final product, reduces efforts and costs since the platform enables early detection of bugs, bottlenecks and problems both in hardware and software, before any silicon is produced. Furthermore, the platform automatically indicates design errors and compliance to specifications of the multiprocessor. It also generates various types of reports such as the number of cache hits or misses, number of taken or correctly predicted branches, interrupts and other statistic data. Thus, system properties, performance, bottlenecks, stalls due to interconnection or data/instruction interdependencies, or unavailable parallelism could be analyzed. A case study of the design and co-verification processes of an 8-core multiprocessor is presented. It shows a time-to-market improvement of 30% when the co-verification approach is used vs. the traditional approach.

(46) Comparative Analyses of Low-Power IC Design Techniques based on Chip Measurements
A. Simevski, O. Schrape, C. Benito
The 16th Biennial Baltic Electronics Conference (BEC 2018)
Vast number of analyses of the mainstream low-power techniques like power gating, clock gating, Dynamic Frequency and Voltage Scaling (DVFS) and Adaptive Voltage Scaling (AVS) are presented. Direct on-chip measurements were performed on a small test chip produced in IHP 130 nm technology which are to be used for building the power strategy of a complex multiprocessor chip. Results showed that for a marginal performance loss, power reduction of 3,5x is possible by downscaling voltage and frequency, while downscaling only voltage leads to power reduction of up to 67%. They further showed that voltage regulators may actually lead to increased power consumption in some cases if care is not taken. In the same time, the paper presents a design strategy for the power architectures of complex Systems-on-Chip.

(47) Reliable Electronic Devices, Circuits, and Systems
Z. Stamenkovic
Proc. 62nd Meeting of the Society for Electronics, Telecommunications, Computers, Automatic Control and Nuclear Engineering (ETRAN 2018), (2018)
The paper describes a comprehensive approach (at the device, circuit, and system levels) to design, implementation, integration, and verification of reliable wireless communication systems on chips. The approach will be illustrated on three examples: a middleware (MW) switch processor for reliable internal satellite communications, an RF-MIMO wireless LAN transceiver, and a high-reliability ultra-low-latency wireless MAC processor for industry automation applications. A high reliability of the MW switch processor which translates the communication protocols of sattelite components into a universal middleware protocol is achieved exploiting radiation-hard technology, hardware redundancy (TMR and DMR), latchup protection swithes, and power gating. The RF-MIMO transceiver based on an innovative spatial multiplexing in the analogue domain offers a bigger capacity, higher reliability, and a large number of supported users in modern communication infrastructures. The proposed MAC processor supports the flexibility, mobility, and scalability of the wireless industrial LAN, approaching the reliability and latency performance of the recent wired industrial LAN.

(48) Decision Support System for Plant and Crop Protection
Z. Stamenkovic, S. Randjic, I. Santamaria, U. Pesovic, D. Markovic
Proc. 41st International Spring Seminar on Electronics Technology (ISSE 2018), (2018)
Wireless sensor networks (WSN) have been extensively applied in agriculture. Thanks to the deployment of sensor nodes on a large area, farmers can receive comprehensive information on the condition of environment and crops. At the same time, the data is obtained in real time and the decisions are made on the basis of real field measurements, not statistical values. By measuring critical parameters like temperature, humidity, insolation, moisture, carbon-dioxide and nitrogen concentration, or detecting economically important pests, farmers are able to (1) anticipate plant health risks, and, when necessary (2) to follow a suitable course of action, including timely pesticide application. Gathered data of deployed WSN is transmitted by a gateway to a central computer, which can store, analyse, and, if necessary, process it. By linking the central computer to the Internet (by a web server or cloud system), the processed data is accepted and distributed to all concerned stakeholders (farmers, technicians, specialists, manufacturers, and retailers). This data is used to increase the yield and quality of feed and food. Agrometeorological sensor network nodes are deployed in a crop field as shown in Figure 1. A network gateway is used to transfer collected field data via Internet to the field database server. A decision support system (DSS), besides input from WSN deployed in the field, can receive input from farmers about some events that cannot be detected by sensors. In addition, farmers can select the type of production they expect (high yield, low input, or organic), which will affect decision-making process. Farmers requests and observations are stored in the needs database server. The system is also accessible to agricultural and referent laboratory experts, who will, based on the inputs obtained by WSN and farmers, shape the decision-making process, observe results, and make the required changes. Furthermore, if a DSS is linked to pesticide suppliers, they can offer the most suitable pesticide to prevent pest outbreak, and instructions how to get it in the nearest agricultural pharmacy.
In this way, a DSS will be developed into a cloud computing system (Figure 1) consisting of several servers which provide different user services in a single package. This system will be able to control the course of agricultural production, protect healthy and treat diseased plants and crops, in particular, taking into account the temporal and spatial variability of environmental parameters.
Over the past two decades, the application of data processing and machine learning techniques in agriculture and crop protection has evolved rapidly along two main directions: i) the deployment of more and more sensors providing multiple sources of information, which goes beyond collecting just environmental and climate data and ii) the use of more advanced machine learning techniques. State-of-the-art knowledge extraction techniques in agriculture process a wide variety of information sources acquired by environmental and chemical sensors, robots, unmanned aerial vehicles, cameras, optical sensors, and even hyperspectral/multispectral sounding sensors. In particular, classical image processing algorithms and computer vision techniques are used in agriculture for the detection of pests and the recognition of plant diseases.

(49) Evaluation of Heterogeneous Tool Chains for Building Complex FPGA-based MPSoCs
R.T. Syed, M. Ulbricht , M. Schölzel
Proc. CDNLive Cadence User Conference (2018)
Modern complex MPSoCs integrate components from many vendors. This typically requires the usage of tools from these different vendors for the design process and for evaluating and programming the system. Therefore there are many options for how these tools can be combined in order to achieve the desired goal. In this paper we consider the implementation of a very typical and complex multi-core system based on Xtensa soft-cores on Xilinx FPGA with dedicated hardware accelerators. Tool chains from different vendors must be used to setup, build and simulate the system. The available tools are used in different combination for performing these tasks. Advantages and disadvantages of these options are presented and discussed in this paper. Moreover, a quantitative comparison in terms of simulation time, accuracy, design effort, optimum simulation flow capabilities is provided for these options. 

(50) Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment
M. Tala, O. Schrape, M. Krstic, D. Bertozzi
Proc. ACM Great Lakes Symposium on VLSI (GLSVLSI 2018), 81 (2018)

(51) Noise Performance of Orthogonal RF Beamforming for Millimetre Wave Massive MIMO Communication Systems
K.K. Tiwari, J.S. Thompson, E. Grass
Proc. of the Tenth International Conference on Wireless Communications and Signal Processing (WCSP 2018), (2018)
Millimeter wave (mmwave) bands offer enormous untapped spectrum for broadband radio communications. For high dimensional and sparse multiple input multiple output (MIMO) channels, analog beamforming (ABF) and digital multi-stream beamforming (DBF), collectively known as hybrid beamforming (HBF), enable low cost and low power-consumption radio architectures with near-optimal performance. It is easier and more efficient to learn such channels in beamspace than in spatial signal space. For radio frequency (RF) beam training, the Tx-Rx beam combination yielding maximum receiver output is selected. Noise can cause false beam selections manifesting in communication rate loss. In this paper, analytically derived closed-form expressions and simulation results for such noise performance evaluation have been presented.

(52) Ein Ansatz für fehlertolerante Radarmessungen durch den Austausch von Messwerten für hochautomatisiertes Fahren
M Ulbricht, M. Schölzel, R. Syed, M. Krstic
Proc. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018), 42 (2018)
Im Bereich des autonomen Fahrens müssen Sensoren und die dazugehörige Datenverabreitung höchste Ansprüche an Zuverlässigkeit und Fehlertoleranz erfüllen. Gleichzeitig sind jedoch auch möglichst geringe Leistungsaufnahme und minimale Herstellungskosten Ziele des Designs. In diesem Abstract stellen wir einen Ansatz vor, der diese Ziele, basierend auf einer von uns entwickelten Sensorplattform (Smart reconfigurable Sensor - SRS), sowie verschiedenen Testarten und dem Austausch von Messwerten, erfüllen kann.

(53) Fehlertolerante Radarmessungen durch Austausch von Messwerten für hochautomatisiertes Fahren
M. Ulbricht, M. Schölzel, R. Tariq Syed, H. Jalli Ng, M. Krstic
Anwendungen und Konzepte der Wirtschaftsinformatik (7), 89 (2018)
Im Bereich des autonomen Fahrens müssen Sensoren und die dazugehörige Datenverarbeitung höchste Ansprüche an Zuverlässigkeit und Fehlertoleranz erfüllen. Gleichzeitig sind jedoch auch möglichst geringe Leistungsaufnahme und minimale Herstellungskosten Ziele des Designs. In diesem Beitrag stellen wir einen Ansatz vor, der diese Ziele, basierend auf einer von uns entwickelten Sensorplattform, sowie verschiedenen Testarten und dem Austausch von Messwerten, erfüllen kann.

(54) Cost-Effective Sensors and Sensor Nodes for Monitoring Environmental Parameters
D. Vasiljevic, C. Zlebic, G. Stojanovic, M. Simic, L. Manjakkal, Z. Stamenkovic
Facta Universitatis, Series: Electronics and Energetics 31(1), 11 (2018)
This paper reviews the design and characterization of humidity and pH sensors manufactured in the printed circuit board (PCB), ink-jet, and screen printing technologies. The first one (PCB technology) provides robust sensors with PET film which can be exposed to harsh environment. The second (ink-jet technology) can manufacture sensors on flexible substrates (foils and papers). The third (screen printing technology) has been used to implement a thick-film sensor. In addition to this, a multi-sensor cloud-based electronic system with autonomous power supply (solar panels) for air and water quality monitoring has been described. Finally, a flexible and modular hardware platform for remote and reliable sensing of environmental parameters has been presented.

(55) Secure Programming and Debug Interface
F. Vater
Proc. 27th Crypto-Day (2018)

(56) The Effects of Voltage Scaling on Reliability and Power Consumption in Multiprocessor Systems
M. Veleski, R. Kraemer, M. Krstic
Proc. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018), 38 (2018)

(57) Localized EMA as a Mean to Find Spatial and Time SCA Leakage Sources
E. Vogel, I. Kabin, Z. Dyka, P. Langendörfer
Proc. 27th Crypto-Day, (2018)

(58) A Reusable Triple Core 12-bit Current Steering Digital-to-Analog Converter for High Performance Transceivers in Industry 4.0 Applications
R. Wittmann, J. Steinkamp, F. Henkel, K. Tittelbach-Helmrich, A. Wolf
Proc. 16. GMM/ITG-Fachtagung (ANALOG 2018), 51 (2018)
This work presents a novel 12-bit 60 MHz triple core concept for a current-steering CMOS digital-to-analog converter (DAC) for use in high performance wireless transmitter circuits. The main core focuses on the 12 bit baseband signal conversion with a sampling rate of 60 MHz.  An assisting second core forms a configurable attenuator circuit, which allows gain adjustments down to 0.025 % FSR (linear) or down to 0.25 dB (logarithmic) steps. The implemented multi-plying architecture utilizes dynamic LSB current scaling, which remarkably improves the signal-to-noise performance for attenuated baseband signals. A third core enables real time linearization during full speed operation. The linearity performance of the main core depends on the matching characteristics of the segmented current source arrays. The presented correction technique is able to burst open the traditional trade-off between area requirements and achievable linearity performance. The implemented additive approach is designed to introduce corrections of up to 4 LSB with a step size of 0.5 LSB for any point of the DAC 4096-step transfer function. The presented architecture is configurable for a wide set of applications. For the targeted Industry 4.0 radio system an oversampling ratio of 3 is applied. The main core is organized into a 8-3-1 segmented structure, which minimizes area for the specified dynamic performance. The basic current cell has been optimized for low glitch operation. The full circuit operates with a single 1.5 V supply and the total power consumption is 35 mW. SINAD value stays close to 70 dB for attenuator settings from 0 to 12 dB. The worst case glitch energy is less than 2.8 pVs. The active area of the fully differential DAC with three cores is 0.25 mm² in a 130 nm standard CMOS technology.

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.