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  • Publications 2020

Publications 2020

since January 2020

(1) Myoelectric Pattern Recognition of Hand Motions for Stroke Rehabilitation
J.C. Castiblanco, St. Ortmann, I.F. Mondragon, C. Alvarado-Rojas, M. Jöbges, J.D. Colorado
Biomedical Signal Processing and Control 57, 101737 (2020)
DOI: 10.1016/j.bspc.2019.101737
Pattern recognition techniques of myoelectric signals have been widely used to identify hand motions and gestures. These techniques have demonstrated that significant motor control information can be extracted and have been implemented in robotic-assistance like prosthesis control. Nevertheless, few investigations have been carried on subjects after a stroke event. In this study, a series of pattern recognition parameters were investigated in the classification of 4 hand exercises (open-close hand, flexion-extension wrist, spread fingers, and pinch grip) involving the affected limb of 4 stroke subjects. Features from EMG data in the time and frequency domains are extracted for training three different classification methods (svm, knn, lda). The classifiers are trained for each exercise individually. Also, it compares 3 methods of feature selection to maintain high levels of classification accuracy: Two-sample T-test with feature variances, Separability Index, and Davies-Boulding Index. The knn classifier obtained the best performance in average for all cases with 87:4% of accuracy, followed by SVM with 82:2% and LDA with 74:5%. The average classifier performances for each exercise were 90:9%, 84:6%, 83:5%, 66:2% for open-close hand, flexion-extension wrist, spread fingers, and pinch grip respectively.

(2) Frequency Interleaving IF Transmitter and Receiver for 240-GHz Communication in SiGe:C BiCMOS
M.H. Eissa, N. Maletic, L. Lopacinski, A. Malignaggi, G. Panic, R. Kraemer, G. Fischer, D. Kissinger
IEEE Transactions on Microwave Theory and Techniques 68(1), 239 (2020)
DOI: 10.1109/TMTT.2019.2940018, (fast spot)
This work presents fully-integrated modular wideband frequency interleaving (FI) transmitter and receiver for high data rate communication applications. At the transmitter side three independent I/Q baseband channels are up-converted to different intermediate frequencies (IF) and then interleaved. At the receiver side the interleaved signals are down-converted and separated back to each independent channel. Single-ended inputs and outputs are utilized in order to reduce the pin count, for a more practical realization and higher potential toward future system scaling. Special design techniques are followed to minimize cross-talk and inter-modulation products between the channels. All circuits are manufactured and measured in a 130nm SiGe:C BiCMOS technology with fT / fmax = 300 / 500 GHz. The FI transmitter achieves a channel bandwidth of 2.5 GHz with less than 3 dB difference across the different channels till 15 GHz IF. It consumes 560mW from 2.5V and 3.3V supplies, and occupies a silicon area of 1.9mm2. The FI receiver achieves a baseband channel bandwidth of 2.5GHz with a 1 dB difference between the channels till the same IF. It consumes 890mW from 2.5V and 3.3V supplies, and has a chip area of 1.55mm2. The circuits are deployed in a communication experiment, firstly in a back-to-back test with direct cable connection, demonstrating a data rate of 15.6 Gb/s across the three IQ channels with a 16- QAM modulation scheme and worst case transmitter-to-receiver (Tx-to-Rx) error vector magnitude (EVM) of -18.6 dB. Then a wireless experiment is performed with a 240 GHz front-end with on-chip antenna, demonstrating a data rate of 7.8 Gb/s with QPSK modulation and worst case EVM of -8.3 dB across a wireless link of 15 cm. To the best of the authors’ knowledge this is the first work that demonstrates a wireless transmission at sub-THz carrier frequencies utilizing frequency interleaving architectures.

(3) RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design
M. Jenihhin, S. Hamdioui, M. Sonza Reorda, M. Krstic, P. Langendörfer, C. Sauer, A. Klotz, M. Huebner, J. Nolte, H.T. Vierhaus, G. Selimis, D. Alexandrescu, M. Taouil, G.-J. Schrijen, J. Raik, L. Sterpone, G. Squillero, Z. Dyka
Proc. Design, Automation & Test in Europe (DATE 2020), (2020)
(RESCUE)

(4) Resistance of the Montgomery kP Algorithm against Simple SCA: Theory and Practice
I. Kabin, Z. Dyka, M. Aftowicz, D. Klann, P. Langendörfer
Proc. 21st IEEE Latin-American Test Symposium (LATS 2020), (2020)
(Total Resilience)

(5) Horizontal Attacks Against ECC: From Simulations to ASIC
I. Kabin, Z. Dyka, D. Klann, P. Langendörfer
Proc. International Workshop on Information & Operational Technology (IT & OT) Security Systems (IOSec 2019), in: Computer Security, Springer, LNCS 11981, 64 (2020)
DOI: 10.1007/978-3-030-42051-2_5, (Total Resilience)

(6) Methods Increasing Inherent Resistance of ECC Designs Against Horizontal Attacks
I. Kabin, Z. Dyka, D. Klann, P. Langendörfer
Integration, the VLSI Journal 73, 50 (2020)
DOI: 10.1016/j.vlsi.2020.03.001, (Total Resilience)
Due to the nature of applications such as critical infrastructure and the Internet of Things etc. side channel analysis attacks are becoming a serious threat. Side channel analysis attacks take advantage from the fact that the behaviour of crypto implementations can be observed and provides hints that simplify revealing keys. A new type of SCA is the so called horizontal differential SCA. In this paper we investigate two different approaches to increase the inherent resistance of our hardware accelerator for the kP operation. The first approach aims at reducing the impact of the addressing in our design by realizing a regular schedule of the addressing. In the second approach, we investigated how the formula used to implement the multiplication of GF(2n)-elements influences the results of horizontal DPA attacks against a Montgomery kP-implementation. We implemented 5 designs with different partial multipliers, i.e. based on different multiplication formulae. We used two different technologies, i.e. a 130 and a 250 nm technology, to simulate power traces for our analysis. We show that the implemented multiplication formula influences the success of horizontal attacks significantly. The combination of these two approaches leads to the most resistant design. For the 250 nm technology only 2 key candidates could be revealed with a correctness of about 70% which is a huge improvement given the fact that for the original design 7 key candidates achieved a correctness of more than 90%. For our 130 nm technology no key candidate was revealed with a correctness of more than 60%.

(7) On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal Attack
I. Kabin, A. Sosa, Z. Dyka, D. Klann, P. Langendörfer
Proc. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2019), (2020)
(Total Resilience)

(8) Integration and Implementation of Four Different Elliptic Curves in a Single High-Speed Design Considering SCA
D. Klann, M. Aftowicz, I. Kabin, Z. Dyka, P. Langendörfer
Proc. 15th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2020), (2020)
DOI: 10.1109/DTIS48698.2020.9081300, (fast sign)
Modern communication systems rely heavily on cryptography to ensure authenticity, confidentiality and integrity of exchanged messages. Elliptic Curve Cryptography (ECC) is one of the common used standard methods for encrypting and signing messages. In this paper we present our implementation of a design supporting four different NIST Elliptic Curves. The design supports two B-curves (B-233, B-283) and two P-curves (P-224, P-256). The implemented designs are sharing the following hardware components bus, multiplier, alu and registers. By implementing the 4 curves in a single design and reusing some resources we reduced the area by 14% compared to a design without resource sharing. Compared to a pure software solution running on an Arm Cortex A9 operating at 1GHz, our design ported to a FPGA is 1.2 to 6 times faster.

(9) High-Resolution Net Load Forecasting for Micro-Neighbourhoods with High Penetration of Renewable Energy Sources
P. Kobylinski, M. Wierzbowski, K. Piotrowski
International Journal of Electrical Power & Energy Systems 117, 105635 (2020)
DOI: 10.1016/j.ijepes.2019.105635, (SmartGrid Plattform)
Though extensive, the literature on electrical load forecasting lacks reports on studies focused on existing residential micro-neighbourhoods comprising small numbers of single-family houses equipped with solar panels. This paper provides a full description of an ANN-based model designed to predict short-term high-resolution (15-minute intervals) micro-scale residential net load profiles. Since it seems especially relevant due to the specificity of local autocorrelations in load signal, in this paper we put stress on the systematic approach to feature selection in the context of lagged signal. We performed a case study of a real micro-neighbourhood comprising only 75 single-family houses. The obtained average prediction error was equivalent to 5.4 per cent of the maximal measured net load. Both issues, i.e.: 1) the feasibility of micro-scale residential load forecasting taking into account renewable energy penetration, and 2) the feature selection problem, could be of interest to engineers designing energy balancing systems for local smart grids.

(10) High-Resolution Net Load Forecasting for Micro-Neighbourhoods with High Penetration of Renewable Energy Sources
P. Kobylinski, M. Wierzbowski, K. Piotrowski
International Journal of Electrical Power & Energy Systems 117, 105635 (2020)
DOI: 10.1016/j.ijepes.2019.105635, (e-balance)
Though extensive, the literature on electrical load forecasting lacks reports on studies focused on existing residential micro-neighbourhoods comprising small numbers of single-family houses equipped with solar panels. This paper provides a full description of an ANN-based model designed to predict short-term high-resolution (15-minute intervals) micro-scale residential net load profiles. Since it seems especially relevant due to the specificity of local autocorrelations in load signal, in this paper we put stress on the systematic approach to feature selection in the context of lagged signal. We performed a case study of a real micro-neighbourhood comprising only 75 single-family houses. The obtained average prediction error was equivalent to 5.4 per cent of the maximal measured net load. Both issues, i.e.: 1) the feasibility of micro-scale residential load forecasting taking into account renewable energy penetration, and 2) the feature selection problem, could be of interest to engineers designing energy balancing systems for local smart grids.

(11) Testing the Blade Resilient Asynchronous Template
F.A. Kuentzer, L. Juracy, M. Moreira, A. Amory
Analog Integrated Circuits and Signal Processing (2020)
DOI: 10.1007/s10470-020-01651-8
As VLSI design moves into ultra-deep-submicron technologies, timing margins added to the clock period are mandatory, to ensure correct circuit behavior under worst-case conditions. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. This paper demonstrates that scan chains can be prohibitive for Blade due to their high silicon costs, which can reach more than 100%. Then, it proposes an alternative test approach that allows concurrent testing, stuck-at, and delay testing. The test approach is based on the reuse of the Blade features to provide testability, with silicon area overheads between 4% and 7%. Also, the proposed test methodology demonstrated that Blade could be tested in different phases, such as manufacturing, for stuck-at and delay faults, with adequate fault coverage between 70% and 100%.

(12) Double Cell Upsets Mitigation Through Triple Modular Redundancy
Y.-Q. Li, A. Breitenreiter, M. Andjelkovic, J.-C. Chen, M. Babic, M. Krstic
Microelectronics Journal 96, 104683 (2020)
DOI: 10.1016/j.mejo.2019.104683, (SEPHY)

(13) Performance Evaluation of LoS Round-Trip ToF Localization: A 60GHz Band Case Study
N. Maletic, V. Sark, M. Ehrig, J. Gutierrez Teran, E. Grass
Proc. 24th International ITG Workshop on Smart Antennas (WSA 2020), 1 (2020)
(WORTECS)

(14) IoT Based Occupancy Detection System with Data Stream Processing and Artificial Neural Networks
D. Markovic, D. Vujicic, Z. Stamenkovic, S. Randjic
Proc. 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2020), (2020)

(15) Modular Baseband Processing for mm-Wave and THz Communication
G. Panic, M.H. Eissa, L. Lopacinski, N. Maletic, R. Kraemer
Proc. 8th Small Systems Simulation Symposium (SSSS 2020), 49 (2020)
(6GKom)

(16) New Solutions for the Support Region Calculation of Logarithmic Quantizers for the Laplacian Source
Z. Peric, M. Dincic, M. Tancic, Z. Stamenkovic
Proc. 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2020), (2020)

(17) Performance Evaluation of a Time-of-Arrival Based Indoor Localization
V. Sark, N. Maletic, J. Gutiérrez, E. Grass
Proc. 8th Small Systems Simulation Symposium (SSSS 2020), 79 (2020)
(WORTECS)

(18) Hardware/Software Co-Verifizierungsplattform für eingebettete Multiprozessoren
A. Simevski, M. Krstic
Proc. 32. GI/GMM/ITG - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2020), (2020)

(19) Using Yield to Predict Long-Term Reliability of Integrated Circuits: Application of Boltzmann-Arrhenius-Zhurkov Model
E. Suhir, Z. Stamenkovic
Solid State Electronics 164, 107746 (2020)
DOI: 10.1016/j.sse.2019.107746
The physically meaningful Boltzmann-Arrhenius-Zhurkov (BAZ) model has been applied to predict the integrated circuit reliability. The model has been modified taking into account the impact of physical defects and process variations (and, consequently, integrated circuit yield) on the stress-free failure activation energy. The probability of non-failure (reliability) and corresponding mean-time-to-failure (MTTF) can be estimated from the failure-oriented-accelerated-testing (FOAT) geared by the modified BAZ model. The concept has been elaborated and illustrated on an application example.

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.