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MPW Schedule 2019 & 2020 and Price Information 2019

General Technology Description

SG25 is the basic 0.25 μm CMOS process. It provides NMOS, PMOS, isolated NMOS and passive components such as poly resistors and MIM capacitors. In addition to the basic CMOS process different front-end-of-line options are offered. The standard backend offers 3 thin metal layers a MIM layer and two TopMetal layers (TopMetal1 - fourth 2 μm thick metal layer, TopMetal2 – fifth 3 μm thick metal layer). Together with a high dielectric stack this enables increased RF passive component performance.

SiGe:C BiCMOS Technologies for MPW & Prototyping

SG25H3 is a 0.25 μm technology with a set of npn-HBTs ranging from a higher RF performance (fT/fmax = 110/180 GHz) to higher breakdown voltages up to 7 V.

 

SG25H4 is a high performance BiCMOS technology. Process is identical to former SG25H1 technology, only Process Design Kit is new. The bipolar module is based on H1 SiGe:C npn HBT’s with up to 190 GHz transit frequencies and up to 220 GHz oscillation frequencies.

 

SGB25V is a cost-effective technology with a set of npn-HBTs up to a breakdown voltage of 7 V.

 

SGB25RH is a special variant of SGB25V which includes radiation hard IP for space applications. Access is available together with our industrial partner Arquimea GmbH. It is not allowed to use Process Design Kit IP together with SGB25V technology.

 

The backend for 0.25 µm process offers 3 thin and 2 thick metal layers (TM1: 2 μm TM2: 3 μm).

 

SG13S is a high-performance 0.13 μm BiCMOS with npn-HBTs up to fT/fmax = 250/300 GHz, with 3.3 V I/O CMOS and 1.2 V logic CMOS.

 

SG13G2 is a 0.13 μm BiCMOS technology with same device portfolio as SG13S but much higher bipolar performance with fT/fmax = 300/500 GHz.

 

SG13SCu and SG13G2Cu FEOL process SG13S and SG13G2 together with Cu BEOL option from XFAB containing 4 thin Cu layer, 2 3μm Cu layer, a thin Al layer with 2fF/μm MIM capacitor and a 2.8μm Aluminum top layer.

 

SG25H5_EPIC technology is a high performance BiCMOS technology with integrated Silicon Photonic devices. It combines a BiCMOS process with very high bipolar performance 250 GHz transit frequencies and up to 300 GHz maximum oscillation frequencies and photonic devices from SG25_PIC.

 

The backend for 0.13 µm process offers 5 thin and 2 thick metal layers (TM1: 2 μm TM2: 3 μm).

Cadence-based mixed signal Design Kit is available. For high frequency designs an analog Design Kit in ADS can be used. IHP's reusable blocks and IPs for wireless and broadband are offered to support your designs.

 

For details about the offered PDKs and supported software please check the design kit website:

The following Modules are available

LBE: The Localized Backside Etching module is offered to remove silicon locally to improve passive performance (available in all technologies).

 

PIC: Additional photonic design layers together with BiCMOS BEOL layers on SOI wafers.

 

TSV: Module is an additional option in SG13S and SG13G2 technology which offers RF grounding by vias through silicon to improve RF performance.

2.1 MPW Price Information 2019

Non Commercial Access

 

For European non profit and educational institutions special discounts are offered for research projects via Europractice. Further costs for using LBE module in all technologies and TSV module in SG25H4 are reduced.

2.1.1 Prices for Technologies 

Process             Area Price / mm2
SGB25V€ 2500
SGB25RH€ 3050
SG25H3€ 3800
SG25H4€ 4600
SG25H5_EPIC€ 8000
SG13S€ 6300
SG13C€ 4500
SG13G2€ 7300
SG13SCu€ 6100
SG13G2Cu€ 7000

2.1.2 Prices for Modules

  

Module (Process)Price
LBE (all)5000 € per order and technology
BEOL (only) 0.13µm (SG13)€ 1000 (per mm2)
SG25_PIC€ 3800 (per mm2)
TSV (S, G2)€ 5000 per order

2.2 MPW Schedule 2019

There is a minimum area requirement of only 0.8 mm2 for all runs with bold shipment times. For all technologies or modules marked in brackets, minimum area order is required. For details see chapter 2.4. TAPE IN time is given in a column “TAPE IN”, while the shipment time in the corresponding table cells.

 

2.2.1 Schedule for complete technologies

TAPE INSGB25SG25SG13
VRH**H3H4EPICS (C)***SCu***G2CuG2
Nov 05, 18(Mar 08)*(Mar 29)*Mar 08*(Apr 01)*May 26
Dec 10, 18Apr 23
May 06
Feb 04, 19May 17*(Jun 07)*May 01
Mar 11, 19
Jul 26*Jul 13
May 06, 19Sep 13
Sep 20
Apr 29, 19Nov 22
Jul 01, 19Nov 01Nov 08
Aug 12, 19Nov 06
Dec 13
Nov 06
(Dec 13)*
Sep 16, 19Feb 23*
Jan 17
 Jan 22
Mar 03*
Nov 04, 19(Mar 06)*(Mar 27)*(Mar 06)*(Mar 28)*May 24

* Runs with lower priority

** TAPE IN for digital blocks is 1 month before standard TAPE IN

*** Schedule is not fixed yet, final approval in Q1 2019

 

Local Backside Etching (LBE) is not offered for EPIC runs and RF_MEMS switch. For all the other runs LBE is available and shipment will be 21 days later than the standard shipment. TSV module is available for SG13S and SG13G2 technologies it leads to a 55 days longer cycle time. Please inform IHP at least 40 days before TAPE IN if you want to use TSV module.


2.2.2 BEOL (only)/
SG25_PIC runs

 

Aluminum Backend of Line Runs are offered in SG13 for testing of passive structures only. Produced
are Metal1 and all layers above. On request Local Backside Etching (LBE) is offered for SG13 BEOL run. SG25_PIC run is offered on photonic substrates and includes active and passive photonic devices.

 

TAPE INSG13SG25_PICTSV
Jun 10, 19Nov 30
Mar 25, 19Jun 12
Sep 03

 

There might be internal BEOL or SG25_PIC runs, without confirmed schedule. Ask customer support for more details if you are interested to join such a run.

2.3 MPW Schedule 2020

Changes are possible till November 1st 2019.

There is a minimum area requirement of only 0.8 mm2 for all runs with bold shipment times. For all technologies or modules marked in brackets, minimum area order is required. For details see chapter 2.4. TAPE IN time is given in a column “TAPE IN”, shipment time in corresponding table cells.

 

Schedule for complete technologies

 

TAPE INSGB25SG25SG13
VRH**H3H4EPICS (C)SCuG2CuG2
Nov 04, 19(Mar 27)*(Mar 06*)(Mar 28)*May 24
Jan 27, 20



Jun 14*May 29Jun 03Jun 23*
Feb 03, 20May 15*(Jun 05)*Apr 29
(Jun 06)*
Apr 06, 20(Sep 20)*Aug 07
Aug 14(Sep 25)*
May 04, 20 Nov 27
Jul 06, 20 Oct 27
(Nov 06)(Nov 11)Nov 13
Aug 10, 20Nov 04
Dec 11
Nov 04
(Dec 11)*
Sep 21, 20Feb 02
Jan 22
Jan 27
Mar 09*
Nov 09, 20(Mar 12)*(Apr 02)*(Mar 12)*May 30

* Runs with lower priority

** TAPE IN for digital blocks is 1 month before standard TAPE IN

 

Local Backside Etching (LBE) is not offered for EPIC runs and RF_MEMS switch. For all the other runs LBE is available and shipment will be 21 days later than the standard shipment. TSV module is available for SG13S and SG13G2 technologies it leads to a 55 days longer cycle time. Please inform IHP at least 40 days before TAPE IN if you want to use TSV module.

2.4 Information on Minimum Area per MPW Run 2019

There is a minimum area requirement of only 0.8 mm² for selected technologies or module in

schedule tables in chapter 2.2 and 2.3. This is valid for all technologies or modules marked with bold shipment times. For all technologies or modules marked with grey italic shipment times in brackets, minimum area order as given in the following table is required. A registration 4 weeks before TAPE out, followed by the confirmation from the foundry, is necessary in this case. By default these additional runs are without priority. A combination of 0.25 μm based runs and 0.13 μm based runs is not possible.

 

Process

Min Area [mm²]

Min Area1 for Discount

                SG25H3

12

15

SG25H410-
SG25H5_EPIC1010

SGB25V

17

17

SGB25RH17-

SG13S

10

7

SG13C

-

-

SG13G21010
SG13SCu1010
SG13G2Cu1010
SG25_PIC1212

1 Ask for special price if you need more than this area for one MPW run.


Delivery

 

As default 40 diced samples will be delivered. Exceptions are designs using TSV module and SG25_PIC. Here 25 samples will be delivered by default. The delivery includes E-test data and RF measurements.

 

Back lapping options:

  • 200 µm (no additional fee)
  • 300 µm (no additional fee)
  • 250 µm (additional fee)
  • 150 µm (additional fee)
  • 100 µm (additional fee)
  • 75 µm (for TSV module only)

 

Hot lots and additional dies are available upon request.


Engineering Runs

An engineering run consists of a separate mask set and the delivery of six wafers. The minimum lot size for an engineering run is 18 wafers. Some of them will be stopped before BEOL as a backup to allow mask-fix (for example). Additional wafers can be purchased upon request.

Total test field area is 10.32 mm times 25.88 mm = 267 mm2. To calculate the usable area for customers you have to subtract test structure area.


For further information please contact:

Dr. René Scholz

IHP GmbH 
Im Technologiepark 25 
15236 Frankfurt (Oder) 
Germany 

Phone: +49 335 5625 647
Fax: +49 335 5625 327

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.