[51]

Hardware Efficient Receiver for Low-Cost Ultra-High Rate 60GHz Wireless Communications

A. Cagri Ulusoy, Gang Liu, Andreas Trasser, Hermann Schumacher

This paper is submitted to the EuMA special issue on 60GHz communications.

Abstract: This paper presents a hardware efficient receiver architecture, to be used in low-cost, ultra-high rate 60GHz wireless communication systems. The receiver utilizes a simple, feed-forward carrier recovery concept, performing phase and frequency synchronization in the analog domain. This enables 1-bit baseband processing without a need of ultra-high speed and high precision analog to digital conversion, offering a strong simplification of the system architecture and comparatively low power consumption. In a first prototype implementation, the receiver is realized in a low cost SiGe technology as two separate ICs: the 60GHz/5GHz downconverter, and the intermediate frequency synchronous demodulator. The simple synchronous reception concept is experimentally validated for up to 3.5GBit/s data rate, which constituted the limit of the existing experimental setup. Furthermore, the downconverter demonstrates that low-cost technologies (fop/fmax ~ 0.75) can be used to realize short range data links at 60 GHz, with low-noise amplifiers in a more performant technology as needed.

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Publications Publications, alphabetical order Publications 2008 Publications 2009 Publications 2010 Publications 2011 ICC 2009 PR 01/2009 Final Presentation	[51] Hardware Efficient Receiver for Low-Cost Ultra-High Rate 60GHz Wireless Communications A. Cagri Ulusoy, Gang Liu, Andreas Trasser, Hermann Schumacher This paper is submitted to the EuMA special issue on 60GHz communications. Abstract: This paper presents a hardware efficient receiver architecture, to be used in low-cost, ultra-high rate 60GHz wireless communication systems. The receiver utilizes a simple, feed-forward carrier recovery concept, performing phase and frequency synchronization in the analog domain. This enables 1-bit baseband processing without a need of ultra-high speed and high precision analog to digital conversion, offering a strong simplification of the system architecture and comparatively low power consumption. In a first prototype implementation, the receiver is realized in a low cost SiGe technology as two separate ICs: the 60GHz/5GHz downconverter, and the intermediate frequency synchronous demodulator. The simple synchronous reception concept is experimentally validated for up to 3.5GBit/s data rate, which constituted the limit of the existing experimental setup. Furthermore, the downconverter demonstrates that low-cost technologies (fop/fmax ~ 0.75) can be used to realize short range data links at 60 GHz, with low-noise amplifiers in a more performant technology as needed.