Certificate Course (in-person): Analog Design with IHP SG13G2 Open-Source PDK

This 4-day onsite course focuses on using open-source tools for analog design rather than designing circuits from scratch. Basic knowledge of analog electronics is required. Participants will gain hands-on experience with an open-source toolchain for IC design, simulation, and layout, using the IHP SG13G2 PDK.

Start Date: 23-Feb-2026
End Date:   27-Feb-2026

Time: Monday Start 13:00
        Tuesday to Thursday 09:30 to 17:30 each day (local time)
        Friday End at 13:00

Location: Fraunhofer-Institut (FhG-IIS), Am Wolfsmantel 33, 91058 Erlangen, Germany

Cost: EU Academics 300.00 EURO
        Others 900.00 EURO

Registration Closing Date: 31-Jan-2026 or earlier when places are filled

Course Details: https://github.com/IHP-GmbH/IHP-AnalogAcademy

Prerequisites: Basic knowledge of analog electronics is required. Familiarity with UNIX environment would be helpful but is not essential.

• Introduction: Setup and familiarize yourself with open-source design tools.
• Bandgap Reference Design: Learn DC and transient simulation, mismatch analysis, and layout techniques.
• RF Workflow: Design a 50 GHz MPA with emphasis on exploring the RF work-flow in Open Source.
• 8-Bit SAR-ADC: Perform mixed-signal analysis and Monte Carlo scripting.

Course schedule:

• Module 0: Foundations 
  This introductory module sets up the essential tools and methodologies for working with the IHP Open PDK in analog IC design. You'll begin by installing and verifying key tools like Xschem and KLayout, guided by the official documentation. Once installed, you’ll explore basic simulations—including DC, transient, AC, Monte Carlo, and S-parameter analyses—through example test cases provided within the PDK.
  
   
• Module 1: Bandgap Reference 
  In this module, you'll begin your first analog design: an all-CMOS bandgap reference. The module is divided into three parts, guiding you from OTA design to full schematic simulation and layout considerations.
  • Part 1 – Designing the OTA
  • Part 2 – Building the Bandgap Reference

  • Part 3 – Layout Introduction

     

• Module 2: 50 GHz Medium Power Amplifier
  In this module, we take our first steps into the world of RF design by developing a 50 GHz Medium Power Amplifier (MPA) using QUCS-S as the schematic editor.
  • Part 1 – Biasing & Familiarization with QUCS-S
  • Part 2 – Input Matching with Smith Chart
  • Part 3 – Nonlinear Simulations with Xyce

  • BONUS: As an extra, we will provide an in-depth presentation on EM simulation, using a fully open source Python interface for OpenEMS, utilizing the IHP SG13G2 stackup. This is a supplement to the last part of the tutorial.

     

• Module 3: 8-bit SAR ADC
  In the final module, we shift focus to mixed-signal design by building a simple yet functional 8-bit Successive Approximation Register (SAR) ADC. The chosen architecture is a synchronous SAR.
  • Part 1 – Dynamic Comparator Design & Analysis
  • Part 2 – Auxiliary Circuit Blocks
  • Part 3 – SAR Logic and Mixed-Signal Integration
  • Part 4 – Final ADC Testbench and Output Analysis