Script list Publications
(1) Characterization and Optimization of the Heat Dissipation Capability of a Chip-on-Board Package using Finite Element Methods
Z. Cao, M. Stocchi, M. Wietstruck, T. Mausolf, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 13(3), 346 (2023)
DOI: 10.1109/TCPMT.2023.3259199, (Hytech)
The present study endeavors to investigate the thermal dissipation capability of a chip-on-board package by means of a comprehensive experimental and numerical analysis. For this purpose, a BiCMOS chip is designed and fabricated in conjunction with three different printed circuit board (PCB) configurations, including a single-sided board, a thermal via board, and a copper frame board. Transient thermal measurements are carried out on all three packages, and the results are subsequently transformed into cumulative structure functions. Then the finite element models are established for each package configuration, and their validity is confirmed through comparison with the experimental structure functions. The models are then characterized in accordance with the Joint Electron Device Engineering Council (JEDEC) 38-set boundary conditions, followed by a series of optimizations targeted toward the PCB, including the board stack-up and the board sizes. Parametric studies are performed to quantitatively assess the impact of these parameters on the thermal performance. Finally, the present study provides a comprehensive discussion of the optimal application scenarios for each board configuration, with a view to achieving good thermal performance. The findings of this study will contribute to the development of more thermally effective chip-on-board packages for high-performance electronic systems.
(2) Characterization and Optimization of the Heat Dissipation Capability of a Chip-on-Board Package using Finite Element Methods
Z. Cao, M. Stocchi, M. Wietstruck, T. Mausolf, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 13(3), 346 (2023)
DOI: 10.1109/TCPMT.2023.3259199, (FLEXCOM)
The present study endeavors to investigate the thermal dissipation capability of a chip-on-board package by means of a comprehensive experimental and numerical analysis. For this purpose, a BiCMOS chip is designed and fabricated in conjunction with three different printed circuit board (PCB) configurations, including a single-sided board, a thermal via board, and a copper frame board. Transient thermal measurements are carried out on all three packages, and the results are subsequently transformed into cumulative structure functions. Then the finite element models are established for each package configuration, and their validity is confirmed through comparison with the experimental structure functions. The models are then characterized in accordance with the Joint Electron Device Engineering Council (JEDEC) 38-set boundary conditions, followed by a series of optimizations targeted toward the PCB, including the board stack-up and the board sizes. Parametric studies are performed to quantitatively assess the impact of these parameters on the thermal performance. Finally, the present study provides a comprehensive discussion of the optimal application scenarios for each board configuration, with a view to achieving good thermal performance. The findings of this study will contribute to the development of more thermally effective chip-on-board packages for high-performance electronic systems.
(3) An Advanced Finite Element Model of the Cu Pillar Solder Reflow Assembly
Z. Cao, B. Pekkolay, A. Okur, B. Heusdens, C. Carta, M. Kaynak
Proc. 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2023), (2023)
DOI: 10.1109/EuroSimE56861.2023.10100808, (SMARTWAVE)
(4) An Advanced Finite Element Model of the Cu Pillar Solder Reflow Assembly
Z. Cao, B. Pekkolay, A. Okur, B. Heusdens, C. Carta, M. Kaynak
Proc. 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2023), (2023)
DOI: 10.1109/EuroSimE56861.2023.10100808, (FLEXCOM)
(5) Image-Rejection Up-/Down-Converter LO Distribution Chain for 5G mm-Wave Phased-Array Systems
A. Franzese, N. Maletic, R. Negra, A. Malignaggi
Proc. IEEE Radio & Wireless Symposium (RWS 2023), 14 (2023)
DOI: 10.1109/RWS55624.2023.10046204, (Taranto)
(6) Wideband and Efficient 256-GHz Subharmonic-Based FMCW Radar Transceiver in 130-nm SiGe BiCMOS Technology
R. Hasan, M.H. Eissa, W.A. Ahmad, H.J. Ng, D. Kissinger
IEEE Transactions on Microwave Theory and Techniques 71(1), 59 (2023)
DOI: 10.1109/TMTT.2022.3207995, (T-KOS)
This article proposes a fully integrated single-channel bistatic frequency-modulated continuous-wave (FMCW) radar transceiver (TRX) that operates at a center frequency of 256 GHz. The main focus of this work is to realize a wideband and efficient radar transceiver that offers high resolution of target detection in the short-range FMCW radar sensing application. The radar transceiver chip is designed and manufactured using 130 nm SiGe BiCMOS technology which offers heterojunction bipolar transistors (HBTs) with fT/fMAX of 300/500 GHz. The transmitter (TX) of the radar transceiver is based on a fundamentally operated multiplier - by - 8 chain architecture that offers a 3 - dB bandwidth of around 65 GHz with a saturated output power of -5.4 dBm. On the other hand, the receiver (RX) is based on a sub-harmonic architecture that provides a conversion gain (CG) of 10.4 dB with an average noise figure (NF) of 23.5 dB. This transceiver is realized with two integrated on-chip folded dipole antennas. The antenna offers high antenna gain and radiation efficiency due to the use of the selective localized backside etching (LBE) technique. This chip consumes 305 mW of power from a 3.3 V supply and occupies a silicon area of 3.3 mm2. The radar range measurement is performed in the anechoic chamber, and it shows the maximum dynamic range of around 32 dB at the 1m range of the target.
(7) A 128 Gb/s 7-Tap FIR Filter in 130 nm SiGe:C BiCMOS for High-Speed Channel Equalization
M. Inac, A. Peczek, F. Gerfers, A. Malignaggi
IEEE Microwave and Wireless Components Letters 33(2), 169 (2023)
DOI: 10.1109/LMWC.2022.3212277
In this letter, a fully analog differential 7-tap 128 Gb/s finite impulse response (FIR) filter using IHP’s 130 nm SG13G2 SiGe:C BiCMOS process is presented. The design includes microstrip transmission line (TL) delay structures for introducing 3 ps tap delay, which corresponds to a third-bit period at 112 Gb/s. Detailed measurements show that the filter is capable of eye diagram improvements up to 128 Gb/s while consuming 693 mW, demonstrating its suitability for new generation 400 Gb/s communication channels. To the best of the authors’ knowledge, this is the fastest NRZ equalization by a fully analog FIR filter, to be found in the literature.
(8) Tunable and Highly Power Efficient Traveling Wave Amplifier in SiGe BiCMOS for Optical Modulators
M. Inac, F. Korndörfer, F. Gerfers, A. Malignaggi
Proc. Radio Wireless Week (RWW 2023), 58 (2023)
DOI: 10.1109/SiRF56960.2023.10046248
(9) DC-Coupled Ultra Broadband Differential to Single-Ended Active Balun in 130-nm SiGe BiCMOS Technology
F. Iseini, A. Malignaggi, F. Korndörfer, G. Kahmen
IEEE Microwave and Wireless Components Letters 33(3), 307 (2023)
DOI: 10.1109/LMWC.2022.3216347, (100G)
The dc-coupled (DCC) broadband operation is a fundamental requirement in many applications, especially in optical communication systems. However, circuits allowing differential to single-ended conversion in a DCC fashion are very rare to be found in the literature. In this letter, a novel differential to single-ended ultrabroadband DCC balun in a 130-nm SiGe BiCMOS technology featuring ft/fmax of 300/500 GHz is presented. A circuit analysis and a performance comparison between the proposed balun and two other configurations which are commonly used to convert a differential signal to a single-ended one is carried out. The design of the mentioned balun is described focusing on the trade-offs between gain, bandwidth (BW) and linearity. Measurement results show how the presented topology can achieve a low-frequency power gain of −7 dB and a 1 dB BW of 80 GHz, along with a total harmonic distortion (THD) of 7%.
(10) Monolithically Integrated Optoelectronic Transmitter based on Segmented Mach-Zehnder Modulator in EPIC 250 nm BiCMOS Technology
F. Iseini, M. Inac, A. Malignaggi, A. Peczek, G. Kahmen
Proc. 23rd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2023), 51 (2023)
DOI: 10.1109/SiRF56960.2023.10046278, (PEARLS)
(11) HBT Power Detector Utilizing an Ultra-Compact Transformer-based Coupler for 5G BIST
E. Jimenez Tuero, A. Franzese, A. Malignaggi
Proc. IEEE Radio and Wireless Week (RWW 2023), 91 (2023)
DOI: 10.1109/RWS55624.2023.10046321, (100G)
(12) A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology
A. Karakuzulu, W. Ahmad, D. Kissinger, A. Malignaggi
IEEE Journal of Solid-State Circuits 58(5), 1310 (2023)
DOI: 10.1109/JSSC.2022.3232948, (6GKom)
This article demonstrates a fully integrated broadband four-channel phased array transceiver, capable of wireless data rates up to 200 Gb/s covering the entire D -band (110–170 GHz). The circuit is developed in a 130-nm SiGe BiCMOS technology, featuring ft/fmax of 300/500 GHz, and includes localized back-side etching-based ON-chip patch antennas. In both transmit and receive modes, direct up- and down-conversions are performed by in-phase and quadrature mixers driven by a multiplier-by-four local oscillator chain. A bidirectional true time delay circuit, with a resolution of 0.446 ps, which is equivalent to the accuracy of a 4-bit phase shifter, provides the squint-free beam-steering capability. Beam-steering measurements show how the beam can be steered from −45° to 45° in a 7° step. The transceiver achieves a 3-dB baseband bandwidth of 30 and 27 GHz in the transmit and receive modes, respectively. A wireless link demonstration is performed by mounting two chips on printed circuit boards, one in the transmit and one in the receive mode, together with plastic lenses on both sides, at a distance of 15 cm. Hardware-in-the-loop measurements show record data rates of 180 Gb/s with EVM of 12.2% using 16-QAM and 200 Gb/s with 8.3% EVM using 32-QAM. The four-channel transceiver consumes 1.95 and 2.5 W in the receive and transmit modes, respectively, which correspond to power efficiencies of 9.75 pJ/bit in the receiver mode and 12.5 pJ/bit in the transmitter mode.
(13) A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology
A. Karakuzulu, W. Ahmad, D. Kissinger, A. Malignaggi
IEEE Journal of Solid-State Circuits 58(5), 1310 (2023)
DOI: 10.1109/JSSC.2022.3232948, (Taranto)
This article demonstrates a fully integrated broadband four-channel phased array transceiver, capable of wireless data rates up to 200 Gb/s covering the entire D -band (110–170 GHz). The circuit is developed in a 130-nm SiGe BiCMOS technology, featuring ft/fmax of 300/500 GHz, and includes localized back-side etching-based ON-chip patch antennas. In both transmit and receive modes, direct up- and down-conversions are performed by in-phase and quadrature mixers driven by a multiplier-by-four local oscillator chain. A bidirectional true time delay circuit, with a resolution of 0.446 ps, which is equivalent to the accuracy of a 4-bit phase shifter, provides the squint-free beam-steering capability. Beam-steering measurements show how the beam can be steered from −45° to 45° in a 7° step. The transceiver achieves a 3-dB baseband bandwidth of 30 and 27 GHz in the transmit and receive modes, respectively. A wireless link demonstration is performed by mounting two chips on printed circuit boards, one in the transmit and one in the receive mode, together with plastic lenses on both sides, at a distance of 15 cm. Hardware-in-the-loop measurements show record data rates of 180 Gb/s with EVM of 12.2% using 16-QAM and 200 Gb/s with 8.3% EVM using 32-QAM. The four-channel transceiver consumes 1.95 and 2.5 W in the receive and transmit modes, respectively, which correspond to power efficiencies of 9.75 pJ/bit in the receiver mode and 12.5 pJ/bit in the transmitter mode.
(14) A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology
A. Karakuzulu, W. Ahmad, D. Kissinger, A. Malignaggi
IEEE Journal of Solid-State Circuits 58(5), 1310 (2023)
DOI: 10.1109/JSSC.2022.3232948, (Open 6G Hub)
This article demonstrates a fully integrated broadband four-channel phased array transceiver, capable of wireless data rates up to 200 Gb/s covering the entire D -band (110–170 GHz). The circuit is developed in a 130-nm SiGe BiCMOS technology, featuring ft/fmax of 300/500 GHz, and includes localized back-side etching-based ON-chip patch antennas. In both transmit and receive modes, direct up- and down-conversions are performed by in-phase and quadrature mixers driven by a multiplier-by-four local oscillator chain. A bidirectional true time delay circuit, with a resolution of 0.446 ps, which is equivalent to the accuracy of a 4-bit phase shifter, provides the squint-free beam-steering capability. Beam-steering measurements show how the beam can be steered from −45° to 45° in a 7° step. The transceiver achieves a 3-dB baseband bandwidth of 30 and 27 GHz in the transmit and receive modes, respectively. A wireless link demonstration is performed by mounting two chips on printed circuit boards, one in the transmit and one in the receive mode, together with plastic lenses on both sides, at a distance of 15 cm. Hardware-in-the-loop measurements show record data rates of 180 Gb/s with EVM of 12.2% using 16-QAM and 200 Gb/s with 8.3% EVM using 32-QAM. The four-channel transceiver consumes 1.95 and 2.5 W in the receive and transmit modes, respectively, which correspond to power efficiencies of 9.75 pJ/bit in the receiver mode and 12.5 pJ/bit in the transmitter mode.
(15) First 100 Gb/s Monolithically Integrated Electronic-Photonic Coherent Receiver with Direct Edge Coupling to Standard Single Mode Fiber Array
A. Osman, G. Winzer, Ch. Mai, A. Peczek, K. Voigt, W. Dorward, St. Lischke, M. Inac, A. Malignaggi, L. Zimmermann, I. Sourikopoulos, L. Stampoulidis
Proc. Optical Fiber Communication Conference (OFC 2023), M3I.3 (2023)
(16) Monolithically Integrated O-Band Coherent ROSA Featuring 2D Grating Couplers for Self-Homodyne Intra Data Center Links
P.M. Seiler, G. Georgieva, A. Peczek, M. Oberon, Ch. Mai, St. Lischke, A. Malignaggi, L. Zimmermann
IEEE Photonics Journal 15(3), 6601306 (2023)
DOI: 10.1109/JPHOT.2023.3272476
In this work, we present an O-band dual-polarization coherent receiver optical sub-assembly (cROSA), monolithically integrated in a 0.25 μ m BiCMOS technology. The receiver features 248 nm deep ultra violet compatible 2-dimensional grating couplers (2D-GRCs), and an adaptive polarization controller, suitable for mitigation of local oscillator induced power fading in self-homodyne transmission systems. The cROSA is evaluated in system experiments at 64 GBd quadrature-phase shift-keying. Experimental results are related to grating coupler induced polarization crosstalk through Monte-Carlo simulations. Second generation 2D-GRCs are proposed.
(17) Vector Modulator Based Leakage Cancellation Technique for CW Radar Transceiver Frontends
B. Sütbas, M.H. Eissa, G. Kahmen
Proc. IEEE Radio and Wireless Symposium (RWS 2023), 88 (2023)
DOI: 10.1109/RWS55624.2023.10046307, (iCampus)
(18) COCHISA Approach: European Core-Chip for Space Applications
F. Vargas, C. Corrado, A. Malignaggi, M. Krstic, D. Verploegen, G. Mannocchi, M.Petri, P. Fontana, U. Lewark, R. Follmann, S. Rochette
Proc. 1st ESA/ESTEC Space Microwave Week (2023), (2023)
(COCHISA)
Z. Cao, M. Stocchi, M. Wietstruck, T. Mausolf, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 13(3), 346 (2023)
DOI: 10.1109/TCPMT.2023.3259199, (Hytech)
The present study endeavors to investigate the thermal dissipation capability of a chip-on-board package by means of a comprehensive experimental and numerical analysis. For this purpose, a BiCMOS chip is designed and fabricated in conjunction with three different printed circuit board (PCB) configurations, including a single-sided board, a thermal via board, and a copper frame board. Transient thermal measurements are carried out on all three packages, and the results are subsequently transformed into cumulative structure functions. Then the finite element models are established for each package configuration, and their validity is confirmed through comparison with the experimental structure functions. The models are then characterized in accordance with the Joint Electron Device Engineering Council (JEDEC) 38-set boundary conditions, followed by a series of optimizations targeted toward the PCB, including the board stack-up and the board sizes. Parametric studies are performed to quantitatively assess the impact of these parameters on the thermal performance. Finally, the present study provides a comprehensive discussion of the optimal application scenarios for each board configuration, with a view to achieving good thermal performance. The findings of this study will contribute to the development of more thermally effective chip-on-board packages for high-performance electronic systems.
(2) Characterization and Optimization of the Heat Dissipation Capability of a Chip-on-Board Package using Finite Element Methods
Z. Cao, M. Stocchi, M. Wietstruck, T. Mausolf, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 13(3), 346 (2023)
DOI: 10.1109/TCPMT.2023.3259199, (FLEXCOM)
The present study endeavors to investigate the thermal dissipation capability of a chip-on-board package by means of a comprehensive experimental and numerical analysis. For this purpose, a BiCMOS chip is designed and fabricated in conjunction with three different printed circuit board (PCB) configurations, including a single-sided board, a thermal via board, and a copper frame board. Transient thermal measurements are carried out on all three packages, and the results are subsequently transformed into cumulative structure functions. Then the finite element models are established for each package configuration, and their validity is confirmed through comparison with the experimental structure functions. The models are then characterized in accordance with the Joint Electron Device Engineering Council (JEDEC) 38-set boundary conditions, followed by a series of optimizations targeted toward the PCB, including the board stack-up and the board sizes. Parametric studies are performed to quantitatively assess the impact of these parameters on the thermal performance. Finally, the present study provides a comprehensive discussion of the optimal application scenarios for each board configuration, with a view to achieving good thermal performance. The findings of this study will contribute to the development of more thermally effective chip-on-board packages for high-performance electronic systems.
(3) An Advanced Finite Element Model of the Cu Pillar Solder Reflow Assembly
Z. Cao, B. Pekkolay, A. Okur, B. Heusdens, C. Carta, M. Kaynak
Proc. 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2023), (2023)
DOI: 10.1109/EuroSimE56861.2023.10100808, (SMARTWAVE)
(4) An Advanced Finite Element Model of the Cu Pillar Solder Reflow Assembly
Z. Cao, B. Pekkolay, A. Okur, B. Heusdens, C. Carta, M. Kaynak
Proc. 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2023), (2023)
DOI: 10.1109/EuroSimE56861.2023.10100808, (FLEXCOM)
(5) Image-Rejection Up-/Down-Converter LO Distribution Chain for 5G mm-Wave Phased-Array Systems
A. Franzese, N. Maletic, R. Negra, A. Malignaggi
Proc. IEEE Radio & Wireless Symposium (RWS 2023), 14 (2023)
DOI: 10.1109/RWS55624.2023.10046204, (Taranto)
(6) Wideband and Efficient 256-GHz Subharmonic-Based FMCW Radar Transceiver in 130-nm SiGe BiCMOS Technology
R. Hasan, M.H. Eissa, W.A. Ahmad, H.J. Ng, D. Kissinger
IEEE Transactions on Microwave Theory and Techniques 71(1), 59 (2023)
DOI: 10.1109/TMTT.2022.3207995, (T-KOS)
This article proposes a fully integrated single-channel bistatic frequency-modulated continuous-wave (FMCW) radar transceiver (TRX) that operates at a center frequency of 256 GHz. The main focus of this work is to realize a wideband and efficient radar transceiver that offers high resolution of target detection in the short-range FMCW radar sensing application. The radar transceiver chip is designed and manufactured using 130 nm SiGe BiCMOS technology which offers heterojunction bipolar transistors (HBTs) with fT/fMAX of 300/500 GHz. The transmitter (TX) of the radar transceiver is based on a fundamentally operated multiplier - by - 8 chain architecture that offers a 3 - dB bandwidth of around 65 GHz with a saturated output power of -5.4 dBm. On the other hand, the receiver (RX) is based on a sub-harmonic architecture that provides a conversion gain (CG) of 10.4 dB with an average noise figure (NF) of 23.5 dB. This transceiver is realized with two integrated on-chip folded dipole antennas. The antenna offers high antenna gain and radiation efficiency due to the use of the selective localized backside etching (LBE) technique. This chip consumes 305 mW of power from a 3.3 V supply and occupies a silicon area of 3.3 mm2. The radar range measurement is performed in the anechoic chamber, and it shows the maximum dynamic range of around 32 dB at the 1m range of the target.
(7) A 128 Gb/s 7-Tap FIR Filter in 130 nm SiGe:C BiCMOS for High-Speed Channel Equalization
M. Inac, A. Peczek, F. Gerfers, A. Malignaggi
IEEE Microwave and Wireless Components Letters 33(2), 169 (2023)
DOI: 10.1109/LMWC.2022.3212277
In this letter, a fully analog differential 7-tap 128 Gb/s finite impulse response (FIR) filter using IHP’s 130 nm SG13G2 SiGe:C BiCMOS process is presented. The design includes microstrip transmission line (TL) delay structures for introducing 3 ps tap delay, which corresponds to a third-bit period at 112 Gb/s. Detailed measurements show that the filter is capable of eye diagram improvements up to 128 Gb/s while consuming 693 mW, demonstrating its suitability for new generation 400 Gb/s communication channels. To the best of the authors’ knowledge, this is the fastest NRZ equalization by a fully analog FIR filter, to be found in the literature.
(8) Tunable and Highly Power Efficient Traveling Wave Amplifier in SiGe BiCMOS for Optical Modulators
M. Inac, F. Korndörfer, F. Gerfers, A. Malignaggi
Proc. Radio Wireless Week (RWW 2023), 58 (2023)
DOI: 10.1109/SiRF56960.2023.10046248
(9) DC-Coupled Ultra Broadband Differential to Single-Ended Active Balun in 130-nm SiGe BiCMOS Technology
F. Iseini, A. Malignaggi, F. Korndörfer, G. Kahmen
IEEE Microwave and Wireless Components Letters 33(3), 307 (2023)
DOI: 10.1109/LMWC.2022.3216347, (100G)
The dc-coupled (DCC) broadband operation is a fundamental requirement in many applications, especially in optical communication systems. However, circuits allowing differential to single-ended conversion in a DCC fashion are very rare to be found in the literature. In this letter, a novel differential to single-ended ultrabroadband DCC balun in a 130-nm SiGe BiCMOS technology featuring ft/fmax of 300/500 GHz is presented. A circuit analysis and a performance comparison between the proposed balun and two other configurations which are commonly used to convert a differential signal to a single-ended one is carried out. The design of the mentioned balun is described focusing on the trade-offs between gain, bandwidth (BW) and linearity. Measurement results show how the presented topology can achieve a low-frequency power gain of −7 dB and a 1 dB BW of 80 GHz, along with a total harmonic distortion (THD) of 7%.
(10) Monolithically Integrated Optoelectronic Transmitter based on Segmented Mach-Zehnder Modulator in EPIC 250 nm BiCMOS Technology
F. Iseini, M. Inac, A. Malignaggi, A. Peczek, G. Kahmen
Proc. 23rd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2023), 51 (2023)
DOI: 10.1109/SiRF56960.2023.10046278, (PEARLS)
(11) HBT Power Detector Utilizing an Ultra-Compact Transformer-based Coupler for 5G BIST
E. Jimenez Tuero, A. Franzese, A. Malignaggi
Proc. IEEE Radio and Wireless Week (RWW 2023), 91 (2023)
DOI: 10.1109/RWS55624.2023.10046321, (100G)
(12) A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology
A. Karakuzulu, W. Ahmad, D. Kissinger, A. Malignaggi
IEEE Journal of Solid-State Circuits 58(5), 1310 (2023)
DOI: 10.1109/JSSC.2022.3232948, (6GKom)
This article demonstrates a fully integrated broadband four-channel phased array transceiver, capable of wireless data rates up to 200 Gb/s covering the entire D -band (110–170 GHz). The circuit is developed in a 130-nm SiGe BiCMOS technology, featuring ft/fmax of 300/500 GHz, and includes localized back-side etching-based ON-chip patch antennas. In both transmit and receive modes, direct up- and down-conversions are performed by in-phase and quadrature mixers driven by a multiplier-by-four local oscillator chain. A bidirectional true time delay circuit, with a resolution of 0.446 ps, which is equivalent to the accuracy of a 4-bit phase shifter, provides the squint-free beam-steering capability. Beam-steering measurements show how the beam can be steered from −45° to 45° in a 7° step. The transceiver achieves a 3-dB baseband bandwidth of 30 and 27 GHz in the transmit and receive modes, respectively. A wireless link demonstration is performed by mounting two chips on printed circuit boards, one in the transmit and one in the receive mode, together with plastic lenses on both sides, at a distance of 15 cm. Hardware-in-the-loop measurements show record data rates of 180 Gb/s with EVM of 12.2% using 16-QAM and 200 Gb/s with 8.3% EVM using 32-QAM. The four-channel transceiver consumes 1.95 and 2.5 W in the receive and transmit modes, respectively, which correspond to power efficiencies of 9.75 pJ/bit in the receiver mode and 12.5 pJ/bit in the transmitter mode.
(13) A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology
A. Karakuzulu, W. Ahmad, D. Kissinger, A. Malignaggi
IEEE Journal of Solid-State Circuits 58(5), 1310 (2023)
DOI: 10.1109/JSSC.2022.3232948, (Taranto)
This article demonstrates a fully integrated broadband four-channel phased array transceiver, capable of wireless data rates up to 200 Gb/s covering the entire D -band (110–170 GHz). The circuit is developed in a 130-nm SiGe BiCMOS technology, featuring ft/fmax of 300/500 GHz, and includes localized back-side etching-based ON-chip patch antennas. In both transmit and receive modes, direct up- and down-conversions are performed by in-phase and quadrature mixers driven by a multiplier-by-four local oscillator chain. A bidirectional true time delay circuit, with a resolution of 0.446 ps, which is equivalent to the accuracy of a 4-bit phase shifter, provides the squint-free beam-steering capability. Beam-steering measurements show how the beam can be steered from −45° to 45° in a 7° step. The transceiver achieves a 3-dB baseband bandwidth of 30 and 27 GHz in the transmit and receive modes, respectively. A wireless link demonstration is performed by mounting two chips on printed circuit boards, one in the transmit and one in the receive mode, together with plastic lenses on both sides, at a distance of 15 cm. Hardware-in-the-loop measurements show record data rates of 180 Gb/s with EVM of 12.2% using 16-QAM and 200 Gb/s with 8.3% EVM using 32-QAM. The four-channel transceiver consumes 1.95 and 2.5 W in the receive and transmit modes, respectively, which correspond to power efficiencies of 9.75 pJ/bit in the receiver mode and 12.5 pJ/bit in the transmitter mode.
(14) A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology
A. Karakuzulu, W. Ahmad, D. Kissinger, A. Malignaggi
IEEE Journal of Solid-State Circuits 58(5), 1310 (2023)
DOI: 10.1109/JSSC.2022.3232948, (Open 6G Hub)
This article demonstrates a fully integrated broadband four-channel phased array transceiver, capable of wireless data rates up to 200 Gb/s covering the entire D -band (110–170 GHz). The circuit is developed in a 130-nm SiGe BiCMOS technology, featuring ft/fmax of 300/500 GHz, and includes localized back-side etching-based ON-chip patch antennas. In both transmit and receive modes, direct up- and down-conversions are performed by in-phase and quadrature mixers driven by a multiplier-by-four local oscillator chain. A bidirectional true time delay circuit, with a resolution of 0.446 ps, which is equivalent to the accuracy of a 4-bit phase shifter, provides the squint-free beam-steering capability. Beam-steering measurements show how the beam can be steered from −45° to 45° in a 7° step. The transceiver achieves a 3-dB baseband bandwidth of 30 and 27 GHz in the transmit and receive modes, respectively. A wireless link demonstration is performed by mounting two chips on printed circuit boards, one in the transmit and one in the receive mode, together with plastic lenses on both sides, at a distance of 15 cm. Hardware-in-the-loop measurements show record data rates of 180 Gb/s with EVM of 12.2% using 16-QAM and 200 Gb/s with 8.3% EVM using 32-QAM. The four-channel transceiver consumes 1.95 and 2.5 W in the receive and transmit modes, respectively, which correspond to power efficiencies of 9.75 pJ/bit in the receiver mode and 12.5 pJ/bit in the transmitter mode.
(15) First 100 Gb/s Monolithically Integrated Electronic-Photonic Coherent Receiver with Direct Edge Coupling to Standard Single Mode Fiber Array
A. Osman, G. Winzer, Ch. Mai, A. Peczek, K. Voigt, W. Dorward, St. Lischke, M. Inac, A. Malignaggi, L. Zimmermann, I. Sourikopoulos, L. Stampoulidis
Proc. Optical Fiber Communication Conference (OFC 2023), M3I.3 (2023)
(16) Monolithically Integrated O-Band Coherent ROSA Featuring 2D Grating Couplers for Self-Homodyne Intra Data Center Links
P.M. Seiler, G. Georgieva, A. Peczek, M. Oberon, Ch. Mai, St. Lischke, A. Malignaggi, L. Zimmermann
IEEE Photonics Journal 15(3), 6601306 (2023)
DOI: 10.1109/JPHOT.2023.3272476
In this work, we present an O-band dual-polarization coherent receiver optical sub-assembly (cROSA), monolithically integrated in a 0.25 μ m BiCMOS technology. The receiver features 248 nm deep ultra violet compatible 2-dimensional grating couplers (2D-GRCs), and an adaptive polarization controller, suitable for mitigation of local oscillator induced power fading in self-homodyne transmission systems. The cROSA is evaluated in system experiments at 64 GBd quadrature-phase shift-keying. Experimental results are related to grating coupler induced polarization crosstalk through Monte-Carlo simulations. Second generation 2D-GRCs are proposed.
(17) Vector Modulator Based Leakage Cancellation Technique for CW Radar Transceiver Frontends
B. Sütbas, M.H. Eissa, G. Kahmen
Proc. IEEE Radio and Wireless Symposium (RWS 2023), 88 (2023)
DOI: 10.1109/RWS55624.2023.10046307, (iCampus)
(18) COCHISA Approach: European Core-Chip for Space Applications
F. Vargas, C. Corrado, A. Malignaggi, M. Krstic, D. Verploegen, G. Mannocchi, M.Petri, P. Fontana, U. Lewark, R. Follmann, S. Rochette
Proc. 1st ESA/ESTEC Space Microwave Week (2023), (2023)
(COCHISA)
