Script list Publications
(1) Design and Characterization of a Variable Gain D-Band LNA for Optimized Link Budgeting for a 6G Receiver in 22FDX
P.J. Artz, Q.H. Le, D.K. Huynh, P. Scholz, T. Kämpfe, S. Lehmann, T. Mausolf, F. Gerfers
IEEE Transactions on Microwave Theory and Techniques 72(2), 1008 (2024)
DOI: 10.1109/TMTT.2023.3298197
This article describes the design and characterization of a fully differential D -band low noise amplifier (LNA) with a measured gain of 9.0–18.0 dB at 153.5 GHz over a 3-dB bandwidth of 10.8 GHz. A minimum noise figure (NF) of 7.9 dB is achieved, measured with the cold-noise source method using a source tuner for noise parameter extraction to enable high accurate NF measurements. The extracted noise parameters allow the source impedance sensitivity to be calculated, with an NF degradation of less than 1.2 dB demonstrated for a source reflection |Γs|≤0.3 . Using the back gate control of the 22-nm fully depleted silicon on insulator (FDSOI) technology enables a passive gain control range of 9 dB, reducing the NF and compression point degradation while scaling the power consumption, thanks to optimal transistor biasing. The measured LNA parameters such as gain, NF, compression, and bandwidth are applied in a link budget analyzer to verify sufficient signal-to-noise and distortion ratio (SNDR) for a 100-GBit/s receiver.
(2) Sub-THz Beam-Steering Antenna in Silicon Interposer Technology
A. Bhutani, L. Valenziano, P. Krüger, T. Voß, T. Zwick, C. Carta, M. Wietstruck
Proc. 27th IEEE European Microwave Week (EuMW 2024), 808 (2024)
DOI: 10.23919/EuMC61614.2024.10732488, (ESSENCE-6GM)
(3) D-Band Active Antenna Array with Lens Enabling Quasi-Optical and Analogue Beam Reconfiguration for 6G Applications
M.A. Campo, S. Bruni, W. Wischmann, A. Lauer, A. Friedrich, M. Wleklinski, C. Oikonomopoulos, O. Litschke, K. KrishneGowda, C. Herold, N. Moroni, W. Keusgen
Proc. 18th European Conference on Antennas and Propagation (EuCAP 2024), (2024)
DOI: 10.23919/EuCAP60739.2024.10501233
(4) The Chip-Level in-Plane Stress Distribution over BiCMOS Wafers
Z. Cao, T. Voss, M. Wietstruck, C. Carta, M. Kaynak
Proc. 24th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2024), 45 (2024)
DOI: 10.1109/SiRF59913.2024.10438504, (FLEXCOM)
(5) The Assembly Investigation of a Multichip to PCB Flip-Chip Package using Cu Pillar Bumps
Z. Cao, J. Lehmann, B. Heusdens, E.C. Durmaz, P. Krüger, M. Wietstruck, N. Herfurth, A.A. Adesunkanmi, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 14(9), 1661 (2024)
DOI: 10.1109/TCPMT.2024.3443599, (FLEXCOM)
This article conducts a comprehensive investigation of the assembly technologies of a Cu pillar-based multichip flip-chip package with low-cost PCB substrates. Such a package is considered as a cost-effective solution for mm-wave broadband applications below 60 GHz. Three main trend flip-chip assembly methods are compared: mass reflow soldering, Cu pillar thermocompression soldering, and Au-Cu thermocompression bonding (TCB). Within these three assembly approaches, both the samples used for assembly and the assembly conditions are systematically compared. Specifically, Cu pillars with and without solder caps, PCB substrates with different solder mask thicknesses, PCB substrates with different glass transition temperatures, and different bonding compression forces are carried out in different assembly approaches. After the assembly, the assembly yield and contact resistance per bump are examined by meander daisy chain resistance measurement and the bonding qualities of both the whole chip and individual bumps are inspected using shear testing and cross sectioning. Findings reveal that reflow soldering offers advantages for high-volume, cost-effective assemblies despite a slightly lower yield, and the Au-Cu TCB exhibits a very high yield with diminished throughput. Whereas, Cu pillar thermocompression soldering does not manifest advantages over the other two approaches. This meticulous investigation enhances the accessibility of the discussed packaging approach, contributing to the groundwork for future technological advancements in this domain.
(6) A 240-GHz VMPS with 1.2° and 0.35 dB RMS Errors in 130 nm BiCMOS:C Technology
M.H. Eissa, Ch. Wipf, A. Malignaggi, G. Kahmen
IEEE Microwave and Wireless Technology Letters (MWTL) 34(3), 295 (2024)
DOI: 10.1109/LMWT.2024.3357203
This work presents a low phase error (PE) and amplitude error (AE) vector modulator phase shifter (VMPS) in the J -band. The influence of the IQ crosstalk RF impairment on the performance is analyzed for different vector summation implementations, guiding to the VMPS architecture choice and design optimization. The chosen architecture consists of an IQ analog-controlled voltage-gain amplifier (IQ-VGA), Branchline coupler, and a Wilkinson combiner. Test structures for the variable-gain amplifier (VGA) and the VMPS are manufactured and measured in a 130-nm BiCMOS technology (fT / fmax = 300/500 GHz). For the phase resolution of 11.25°, the VMPS achieves an average rms PE and AE of 1.2° and 0.35 dB, respectively, with equivalent to 5.5 -bits control voltage across the frequency band 220–260 GHz. The VMPS consumes 60 mW from 2.5-V supply and occupies 0.2 mm 2 of silicon area. This work presents the least PE and AE across a wide bandwidth for VMPS in silicon technologies above 200 GHz, which is crucial for large-scale beam-steering arrays.
(7) Advanced Characterization Approaches with Pad-Model De-Embedding of Sub-THz Devices for 6G Applications
A. Franzese, B. Sütbas, T. Mausolf, N. Moroni, R. Negra, A. Sanchez Ramos, F. Greco, L. Boccia, E. Shokrolahzade, M. Spirito, C. Carta
Proc. 19th European Microwave Integrated Circuits Conference (EuMIC 2024), 428 (2024)
DOI: 10.23919/EuMIC61603.2024.10732437
(8) 56% PAE mm-Wave SiGe BiCMOS Power Amplifier Employing Local Backside Etching
A. Franzese, B. Sutbas, R. Hasan, A. Malignaggi, T. Mausolf, N. Maletic, M.-D. Wey, H. Zhou, C. Fager, C. Carta, R. Negra
IEEE Microwave and Wireless Technology Letters (MWTL) 34(8), 1023 (2024)
DOI: 10.1109/LMWT.2024.3409149
This letter presents a power amplifier (PA) with excellent power-added efficiency (PAE) for millimeter-wave (mm-wave) applications. The high efficiency is achieved by leveraging a local backside etching (LBE) process to enhance the quality factor ( Q ) of the output matching network. The PA was fabricated in a mature SiGe BiCMOS technology featuring heterojunction bipolar transistors (HBTs) having an fT / fmax of 250/340 GHz. While the measured peak PAE is 56% at 24 and 25 GHz, the PA provides 16 dB of peak gain and a 3-dB bandwidth of 19 GHz ranging from 13.5 to 32.5 GHz, which makes the circuit well suited for multiple purposes, such as sensors, radars, 5G, and satellite communications. The maximum PAE exceeds 40% from 22 to 28 GHz, with a peak saturated power (Psat) of 16.5 dBm at 25 GHz. To the best of authors’ knowledge, this PA achieves the highest PAE reported to date for silicon-based mm-wave amplifiers.
(9) 28-GHz SiGe Bidirectional 4-Element Beamformer Chip for 5G Applications based on a 4-Way Ultracompact Switchable Power Divider
A. Franzese, R. Negra, A. Malignaggi, N. Maletic, B. Sütbas, C. Carta
IEEE Transactions on Microwave Theory and Techniques 72(12), 7050 (2024)
DOI: 10.1109/TMTT.2024.3409571
This article describes the design of a 28-GHz bidirectional 4-element beamformer chip based on a 4-way ultracompact switchable power divider (SPD). The addition of the divider solves the ineffective power splitting and the inefficient use of valuable chip area. Therefore, this work is devoted to remove the drawbacks associated with the Wilkinson power dividers (PDs) and single-pole double-throw switches (SPDTs) leveraging a single-inductor N-way PD topology. In this article, the PD design is presented and its analysis is carried out, extending the previous literature. In addition, the embedding of the SPDTs within the PD is described in detail. Employing the proposed technique, the chip size is limited only to the dimensions of the main RF building blocks, analog circuitry, and digital logic; hence, eliminating the cumbersome divider chain which connects the transmitting/receiving (TRx) elements before going on-board. Finally, the measured performance of the beamformer designed in the IHP SG13S SiGe BiCMOS technology is reported. The beamformer achieves an OP1 dB of 11 dBm in Tx-mode with a power consumption of 231 mW for each element, whereas an IP1 dB of -28 dBm in Rx-mode is achieved consuming only 92 mW per element. The chip occupies a silicon area of 2.9×2.2 mm2. Moreover, a shift step of 11.25° is achieved with 2.4° and 0.4 dB of phase and amplitude root-mean-square error (RMSE), respectively. To the best of the authors’ knowledge, this is the first beamformer which substitutes the divider chain with a novel SPD. In this way, the chip length could be reduced by 1 mm with respect to their previous design, which proves that the proposed technique is promising for chips with high number of TRx elements.
(10) A Flexible and Fast Digital Twin for RRAM Systems Applied for Training Resilient Neural Networks
M. Fritscher, S. Singh, T. Rizzi, A. Baroni, D. Reiser, M. Mallah, D. Hartmann, A. Bende, T. Kempen, M. Uhlmann, G. Kahmen, D. Fey, V. Rana, S. Menzel, M. Reichenbach, M. Krstic, F. Merchant, Ch. Wenger
Scientific Reports 14, 23695 (2024)
DOI: 10.1038/s41598-024-73439-z, (MIMEC)
Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).
(11) Area-Efficient Digital Design using RRAM-CMOS Standardcells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, M.A. Schubert, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2024), 81 (2024)
DOI: 10.1109/ISVLSI61997.2024.00026, (iCampus II)
(12) Area-Efficient Digital Design using RRAM-CMOS Standardcells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, M.A. Schubert, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2024), 81 (2024)
DOI: 10.1109/ISVLSI61997.2024.00026, (HYB-RISC)
(13) A Flexible and Fast Digital Twin for RRAM Systems Applied for Training Resilient Neural Networks
M. Fritscher, S. Singh, T. Rizzi, A. Baroni, D. Reiser, M. Mallah, D. Hartmann, A. Bende, T. Kempen, M. Uhlmann, G. Kahmen, D. Fey, V. Rana, S. Menzel, M. Reichenbach, M. Krstic, F. Merchant, Ch. Wenger
Scientific Reports 14, 23695 (2024)
DOI: 10.1038/s41598-024-73439-z, (iCampus II)
Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).
(14) Area-Efficient Digital Design using RRAM-CMOS Standardcells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, M.A. Schubert, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2024), 81 (2024)
DOI: 10.1109/ISVLSI61997.2024.00026, (KI-IoT)
(15) A Flexible and Fast Digital Twin for RRAM Systems Applied for Training Resilient Neural Networks
M. Fritscher, S. Singh, T. Rizzi, A. Baroni, D. Reiser, M. Mallah, D. Hartmann, A. Bende, T. Kempen, M. Uhlmann, G. Kahmen, D. Fey, V. Rana, S. Menzel, M. Reichenbach, M. Krstic, F. Merchant, Ch. Wenger
Scientific Reports 14, 23695 (2024)
DOI: 10.1038/s41598-024-73439-z, (6G-RIC)
Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).
(16) Over-the-Air 26 GHz Receiver Hardware-Software Evaluation towards Joint Communication and Radar Sensing
S. George, P. Sen, M. Umar, M. Matthe, J. Adler, M. Ramzan, C. Carta
Proc. 54th European Microwave Conference (EuMC 2024), 509 (2024)
DOI: 10.23919/EuMC61614.2024.10732620
(17) A Multi-Mode Direct Conversion Receiver for Joint Communication and Radar Sensing
S. George, P. Sen, C. Carta
Proc. 15th German Microwave Conference (GeMiC 2024), 229 (2024)
DOI: 10.23919/GeMiC59120.2024.10485239
(18) Realizing Joint Communication and Sensing RF Receiver Front-Ends: A Survey
S. George, P. Sen, C. Carta
IEEE Access 12, 9440 (2024)
DOI: 10.1109/ACCESS.2024.3351572
Joint Communication and radio Sensing (JC&S) has gained significant attention over the past few years. The advantages of this technology include reduced cost, size and power consumption. With further advancements in JC&S systems, it can potentially be used in next-generation cellular networks, internet-of-things and upcoming applications such as Industry 4.0, where a single system is capable of performing a wide variety of functions or tasks. The inclusion of this technology will result in improved performance and safety of the systems. Even though communication and radio sensing make use of a similar Radio Frequency (RF) front-end, the specifications for both these technologies mainly differ in terms of bandwidth and linearity. In this survey, a detailed study of the specifications of radar and communication was conducted. For the RF front-end to operate efficiently in both radar and communication modes, there must be reconfigurability in terms of frequency, bandwidth, gain and linearity. In this survey, we investigated different frequency, bandwidth, gain and linearity reconfigurable low noise amplifier (LNA) and down-conversion mixer architectures. The merits and demerits of each architecture are discussed and a summary of the performance of the reconfigurable LNAs and down-conversion mixers in the literature is presented. Finally, possible topologies for JC&S are deduced based on their performance.
(19) Design of Radiation-Tolerant Digital-to-Analog Converter and Investigation on Analog Single Event Transient Effects
A. Harneer Suresh, C. Carta, G. Fischer
AEÜ - International Journal of Electronics and Communications 187, 155503 (2024)
DOI: 10.1016/j.aeue.2024.155503, (AMX IP)
A circuit design methodology for space applications is presented with an 8-bit resistive digital-to-analog converter (DAC) with XY addressing mode and BiCMOS buffer designed in IHP’s 130 nm SiGe BiCMOS technology (SG13S). The radiation tolerance of the implemented DAC is evaluated by circuit-level simulations particularly analyzing the radiation sensitivity of the DAC to analog single-event transients (ASETs). Radiation mitigation techniques are addressed. The total current consumption with a 3.3 V supply is 0.54 mA at a 1 MHz sampling frequency.
(20) Circuit Design Methodology of Radiation-Tolerant DAC for Space Applications
A. Harneer Suresh, J.A. Singer, G. Fischer
Proc. PAnhellenic Conference on Electronics and Telecommunication (PACET 2024), (2024)
DOI: 10.1109/PACET60398.2024.10497042, (AMX IP)
(21) Jitter Minimization of Phase-Locked Loops for OFDM-Based Millimeter-Wave Communication Systems with Beam Steering
F. Herzel, C. Carta, G. Fischer
Proc. 31st IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2024), 19 (2024)
DOI: 10.23919/MIXDES62605.2024.10614043, (AMX IP)
(22) Jitter Minimization of Phase-Locked Loops for OFDM-Based Millimeter-Wave Communication Systems with Beam Steering
F. Herzel, C. Carta, G. Fischer
Proc. 31st IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2024), abstr. book 52 (2024)
DOI: 10.23919/MIXDES62605.2024.10613942, (AMX IP)
(23) Contactless Assessment of Physiological Parameters with a 61 GHz CW Medical Radar System
R. Holzschuh, H. Lu, B. Sütbas, A.E. Bezer, R. Freund, St. Ortmann, D.G. Meininghaus
Proc. iCampus Cottbus Conference (iCCC 2024), 53 (2024)
DOI: 10.5162/iCCC2024/2.3, (iCampus II)
(24) A Tunable Inductor Peaking Technique for Optical Communication Systems
F. Iseini, H.-T. Lin, N. Pelagalli, A. Malignaggi, C. Carta, G. Kahmen, A. Weisshaar
Proc. 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS 2024), 55 (2024)
DOI: 10.1109/EPEPS61853.2024.10753708, (100G)
(25) A Signal Source in J-Band with 237-287 GHz Tuning Range in a 130-nm SiGe BiCMOS Process
F.I. Jamal, T. Mausolf, M. Yazici, F. Vater, C. Carta, R. Scholz
Proc. 54th European Microwave Week (EuMW 2024), 114 (2024)
DOI: 10.23919/EuMIC61603.2024.10732403, (SMARTWAY)
(26) A 2.5 - 2.7 GHz Frequency-Tunable Band-Pass Delta-Sigma Modulator in a 0.25μm SiGe BiCMOS for Fiber-Wireless Digital Distributed Antenna Systems
S. Jang, B. Park, P. Ostrovskyy, J. Jung, K.-S. Kim, J.-H. Hwang
Proc. 50th European Conference on Optical Communications (ECOC 2024), 1220 (2024)
(27) Tunable True-Time-Delay Unit Based on Bridged T-Coil
H.T. Lin, F. Iseini, A. Weisshaar
Proc. 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS 2024), 56 (2024)
DOI: 10.1109/EPEPS61853.2024.10753922
(28) Influence of Stop and Gate Voltage on Resistive Switching of 1T1R HfO2-based Memristors, a Modeling and Variability Analysis
D. Maldonado, A. Cantudo, K.D.S. Reddy, S. Pechmann, M. Uhlmann, Ch. Wenger, J.B. Roldán, E. Pérez
Materials Science in Semiconductor Processing 182, 108726 (2024)
DOI: 10.1016/j.mssp.2024.108726, (KI-IoT)
Memristive devices, particularly resistive random access memory (RRAM) cells based on hafnium oxide (HfO₂) dielectrics, exhibit promising characteristics for a wide range of applications. In spite of their potential, issues related to intrinsic variability and the need for precise simulation tools and modeling methods remain a medium-term hurdle. This study addresses these challenges by investigating the resistive switching (RS) behavior of different 1T1R HfO₂-based memristors under various experimental conditions. Through a comprehensive experimental analysis, we extract RS parameters using different numerical techniques to understand the cycle-to-cycle (C2C) and device-to-device (D2D) variability. Additionally, we employ advanced simulation methodologies, including circuit breaker-based 3D simulation, to shed light on our experimental findings and provide a theoretical framework to disentangle the switching phenomena. Our results offer valuable insights into the RS mechanisms and variability, contributing to the improvement of robust parameter extraction methods, which are essential for the industrial application of memristive devices.
(29) A 434 MHz Wakeup Receiver Analog Frontend based on a Switched Injection-Triggered Oscillator with -91 dBm Input Sensitivity and 175 pJ/bit Efficiency
G. Meller, M. Methfessel, F. Protze, J. Wagner, F. Ellinger
Proc. 27th European Microwave Week (EuMW 2024), 251 (2024)
DOI: 10.23919/EuMIC61603.2024.10732288
(30) A 30GHz PLL with Automated Frequency Control Option for Robust Operation in Harsh Environments
A. Minareci Ergintav, F. Herzel, G. Fischer, D. Kissinger, C. Carta
Proc. 19th European Microwave Integrated Circuits Conference (EuMIC 2024), 34 (2024)
DOI: 10.23919/EuMIC61603.2024.10732750
(31) Vital Signs Monitoring using 61.4 GHz CW MIMO Radar Sensor with LO-Scalable Low-Voltage Low-Power SiGe BiCMOS Chipset
B. Sütbas, H.J. Ng, M.H. Eissa, C. Carta, G. Kahmen
Proc. 54th European Microwave Conference (EuMC 2024), 497 (2024)
DOI: 10.23919/EuMC61614.2024.10732052, (iCampus II)
(32) Vital Signs Monitoring using 61.4 GHz CW MIMO Radar Sensor with LO-Scalable Low-Voltage Low-Power SiGe BiCMOS Chipset
B. Sütbas, H.J. Ng, M.H. Eissa, C. Carta, G. Kahmen
Proc. 54th European Microwave Conference (EuMC 2024), 497 (2024)
DOI: 10.23919/EuMC61614.2024.10732052, (iCampus)
(33) Effect of the Temperature on the Performance and Dynamic Behaviour of HfO2-based RRAM Devices
G. Vinuesa, H. Garcia, S. Dueñas, H. Castan, I. Iñiguez-de-la-Torre, T. Gonzalez, K.D.S. Reddy, M. Uhlmann, Ch. Wenger, E. Perez
Proc. 245th ECS Meeting: Advancing Solid State & Electrochemical Science & Technology (ECS Meeting 2024), abstr. book 1297 (2024)
DOI: 10.1149/MA2024-01211297mtgabs, (KI-IoT)
(34) Towards Reliable and Energy-Efficient RRAM based Discrete Fourier Transform Accelerator
J. Wen, A. Baroni, E. Perez, M. Uhlmann, M. Fritscher, K. KrishneGowda, M. Ulbricht, Ch. Wenger, M. Krstic
Proc. 27th Design, Automation and Test in Europe (DATE 2024), (2024)
(6G-RIC)
(35) Fabrication and Implementation of BiCMOS BEOL Silicon Interposer Technologies with Integrated Metal Reflectors for Sub-THz Leaky-Wave Antennas
M. Wietstruck, P. Krüger, T. Voß, T. Mausolf, M.F. Bashir, A. Bhutani
Proc. 10th IEEE Electronics System-Integration Technology Conference (ESTC 2024), (2024)
DOI: 10.1109/ESTC60143.2024.10712047, (ESSENCE-6GM)
(36) A 60 GHz Broadband LNA with Joined Variable Gain Control and Switching in 22 nm FD-SOI
X. Xu, J. Wagner, C. Carta, F. Ellinger
IEEE Access 12, 111627 (2024)
DOI: 10.1109/ACCESS.2024.3441853
This paper investigates a 60 GHz low-power broadband low noise amplifier (LNA) with variable gain control. To prove the concept, the circuit is implemented in a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS technology. It supports broadband operation at 60 GHz achieved by gain peaking (gain distribution) technique. By tuning some key matching networks of the amplifier, the peak gain of each stage was distributed to different frequencies resulting in an overall broadband frequency response. The circuit consists of three cascaded cascode amplifier stages. Matching networks were optimized regarding bandwidth and noise figure. The transistor back-gate was used for LNA designs to switch the circuit to low-power standby mode. This avoids the problems of front-gate based switching regarding voltage breakdown and circuit stability. Additionally, simultaneous realization of variable gain control at such high frequencies was achieved via the back-gate. Compared to the front-gate based, the back-gate based variable gain control can deliver a continuous fine-tuning of the gain while requiring less accuracy or resolution of the control voltage. In the measurement, The gain was successfully tuned from 20 dB down to −25 dB via the back-gate. At a DC power of 8.1 mW from a nominal supply of 1 V, the LNA provides a peak gain of 20 dB, a bandwidth of 18.5 GHz, and a minimum noise figure of 3.3 dB. When biased at a reduced DC supply of 0.4 V, the presented circuit consumes only 2.5 mW of DC power, and still provides a power gain of 10 dB and a minimum noise figure of around 4.5 dB. By switching to standby mode, the LNA consumes 850 µW of DC power at the nominal supply and 240 µW at the reduced supply. The LNA compares well against previously reported designs by showing the lowest noise figure with competitive gain, bandwidth and DC power. To the authors’ knowledge, this is the first 60 GHz LNA featuring joined variable gain control and switching capability via solely back-gate biasing.
P.J. Artz, Q.H. Le, D.K. Huynh, P. Scholz, T. Kämpfe, S. Lehmann, T. Mausolf, F. Gerfers
IEEE Transactions on Microwave Theory and Techniques 72(2), 1008 (2024)
DOI: 10.1109/TMTT.2023.3298197
This article describes the design and characterization of a fully differential D -band low noise amplifier (LNA) with a measured gain of 9.0–18.0 dB at 153.5 GHz over a 3-dB bandwidth of 10.8 GHz. A minimum noise figure (NF) of 7.9 dB is achieved, measured with the cold-noise source method using a source tuner for noise parameter extraction to enable high accurate NF measurements. The extracted noise parameters allow the source impedance sensitivity to be calculated, with an NF degradation of less than 1.2 dB demonstrated for a source reflection |Γs|≤0.3 . Using the back gate control of the 22-nm fully depleted silicon on insulator (FDSOI) technology enables a passive gain control range of 9 dB, reducing the NF and compression point degradation while scaling the power consumption, thanks to optimal transistor biasing. The measured LNA parameters such as gain, NF, compression, and bandwidth are applied in a link budget analyzer to verify sufficient signal-to-noise and distortion ratio (SNDR) for a 100-GBit/s receiver.
(2) Sub-THz Beam-Steering Antenna in Silicon Interposer Technology
A. Bhutani, L. Valenziano, P. Krüger, T. Voß, T. Zwick, C. Carta, M. Wietstruck
Proc. 27th IEEE European Microwave Week (EuMW 2024), 808 (2024)
DOI: 10.23919/EuMC61614.2024.10732488, (ESSENCE-6GM)
(3) D-Band Active Antenna Array with Lens Enabling Quasi-Optical and Analogue Beam Reconfiguration for 6G Applications
M.A. Campo, S. Bruni, W. Wischmann, A. Lauer, A. Friedrich, M. Wleklinski, C. Oikonomopoulos, O. Litschke, K. KrishneGowda, C. Herold, N. Moroni, W. Keusgen
Proc. 18th European Conference on Antennas and Propagation (EuCAP 2024), (2024)
DOI: 10.23919/EuCAP60739.2024.10501233
(4) The Chip-Level in-Plane Stress Distribution over BiCMOS Wafers
Z. Cao, T. Voss, M. Wietstruck, C. Carta, M. Kaynak
Proc. 24th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2024), 45 (2024)
DOI: 10.1109/SiRF59913.2024.10438504, (FLEXCOM)
(5) The Assembly Investigation of a Multichip to PCB Flip-Chip Package using Cu Pillar Bumps
Z. Cao, J. Lehmann, B. Heusdens, E.C. Durmaz, P. Krüger, M. Wietstruck, N. Herfurth, A.A. Adesunkanmi, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 14(9), 1661 (2024)
DOI: 10.1109/TCPMT.2024.3443599, (FLEXCOM)
This article conducts a comprehensive investigation of the assembly technologies of a Cu pillar-based multichip flip-chip package with low-cost PCB substrates. Such a package is considered as a cost-effective solution for mm-wave broadband applications below 60 GHz. Three main trend flip-chip assembly methods are compared: mass reflow soldering, Cu pillar thermocompression soldering, and Au-Cu thermocompression bonding (TCB). Within these three assembly approaches, both the samples used for assembly and the assembly conditions are systematically compared. Specifically, Cu pillars with and without solder caps, PCB substrates with different solder mask thicknesses, PCB substrates with different glass transition temperatures, and different bonding compression forces are carried out in different assembly approaches. After the assembly, the assembly yield and contact resistance per bump are examined by meander daisy chain resistance measurement and the bonding qualities of both the whole chip and individual bumps are inspected using shear testing and cross sectioning. Findings reveal that reflow soldering offers advantages for high-volume, cost-effective assemblies despite a slightly lower yield, and the Au-Cu TCB exhibits a very high yield with diminished throughput. Whereas, Cu pillar thermocompression soldering does not manifest advantages over the other two approaches. This meticulous investigation enhances the accessibility of the discussed packaging approach, contributing to the groundwork for future technological advancements in this domain.
(6) A 240-GHz VMPS with 1.2° and 0.35 dB RMS Errors in 130 nm BiCMOS:C Technology
M.H. Eissa, Ch. Wipf, A. Malignaggi, G. Kahmen
IEEE Microwave and Wireless Technology Letters (MWTL) 34(3), 295 (2024)
DOI: 10.1109/LMWT.2024.3357203
This work presents a low phase error (PE) and amplitude error (AE) vector modulator phase shifter (VMPS) in the J -band. The influence of the IQ crosstalk RF impairment on the performance is analyzed for different vector summation implementations, guiding to the VMPS architecture choice and design optimization. The chosen architecture consists of an IQ analog-controlled voltage-gain amplifier (IQ-VGA), Branchline coupler, and a Wilkinson combiner. Test structures for the variable-gain amplifier (VGA) and the VMPS are manufactured and measured in a 130-nm BiCMOS technology (fT / fmax = 300/500 GHz). For the phase resolution of 11.25°, the VMPS achieves an average rms PE and AE of 1.2° and 0.35 dB, respectively, with equivalent to 5.5 -bits control voltage across the frequency band 220–260 GHz. The VMPS consumes 60 mW from 2.5-V supply and occupies 0.2 mm 2 of silicon area. This work presents the least PE and AE across a wide bandwidth for VMPS in silicon technologies above 200 GHz, which is crucial for large-scale beam-steering arrays.
(7) Advanced Characterization Approaches with Pad-Model De-Embedding of Sub-THz Devices for 6G Applications
A. Franzese, B. Sütbas, T. Mausolf, N. Moroni, R. Negra, A. Sanchez Ramos, F. Greco, L. Boccia, E. Shokrolahzade, M. Spirito, C. Carta
Proc. 19th European Microwave Integrated Circuits Conference (EuMIC 2024), 428 (2024)
DOI: 10.23919/EuMIC61603.2024.10732437
(8) 56% PAE mm-Wave SiGe BiCMOS Power Amplifier Employing Local Backside Etching
A. Franzese, B. Sutbas, R. Hasan, A. Malignaggi, T. Mausolf, N. Maletic, M.-D. Wey, H. Zhou, C. Fager, C. Carta, R. Negra
IEEE Microwave and Wireless Technology Letters (MWTL) 34(8), 1023 (2024)
DOI: 10.1109/LMWT.2024.3409149
This letter presents a power amplifier (PA) with excellent power-added efficiency (PAE) for millimeter-wave (mm-wave) applications. The high efficiency is achieved by leveraging a local backside etching (LBE) process to enhance the quality factor ( Q ) of the output matching network. The PA was fabricated in a mature SiGe BiCMOS technology featuring heterojunction bipolar transistors (HBTs) having an fT / fmax of 250/340 GHz. While the measured peak PAE is 56% at 24 and 25 GHz, the PA provides 16 dB of peak gain and a 3-dB bandwidth of 19 GHz ranging from 13.5 to 32.5 GHz, which makes the circuit well suited for multiple purposes, such as sensors, radars, 5G, and satellite communications. The maximum PAE exceeds 40% from 22 to 28 GHz, with a peak saturated power (Psat) of 16.5 dBm at 25 GHz. To the best of authors’ knowledge, this PA achieves the highest PAE reported to date for silicon-based mm-wave amplifiers.
(9) 28-GHz SiGe Bidirectional 4-Element Beamformer Chip for 5G Applications based on a 4-Way Ultracompact Switchable Power Divider
A. Franzese, R. Negra, A. Malignaggi, N. Maletic, B. Sütbas, C. Carta
IEEE Transactions on Microwave Theory and Techniques 72(12), 7050 (2024)
DOI: 10.1109/TMTT.2024.3409571
This article describes the design of a 28-GHz bidirectional 4-element beamformer chip based on a 4-way ultracompact switchable power divider (SPD). The addition of the divider solves the ineffective power splitting and the inefficient use of valuable chip area. Therefore, this work is devoted to remove the drawbacks associated with the Wilkinson power dividers (PDs) and single-pole double-throw switches (SPDTs) leveraging a single-inductor N-way PD topology. In this article, the PD design is presented and its analysis is carried out, extending the previous literature. In addition, the embedding of the SPDTs within the PD is described in detail. Employing the proposed technique, the chip size is limited only to the dimensions of the main RF building blocks, analog circuitry, and digital logic; hence, eliminating the cumbersome divider chain which connects the transmitting/receiving (TRx) elements before going on-board. Finally, the measured performance of the beamformer designed in the IHP SG13S SiGe BiCMOS technology is reported. The beamformer achieves an OP1 dB of 11 dBm in Tx-mode with a power consumption of 231 mW for each element, whereas an IP1 dB of -28 dBm in Rx-mode is achieved consuming only 92 mW per element. The chip occupies a silicon area of 2.9×2.2 mm2. Moreover, a shift step of 11.25° is achieved with 2.4° and 0.4 dB of phase and amplitude root-mean-square error (RMSE), respectively. To the best of the authors’ knowledge, this is the first beamformer which substitutes the divider chain with a novel SPD. In this way, the chip length could be reduced by 1 mm with respect to their previous design, which proves that the proposed technique is promising for chips with high number of TRx elements.
(10) A Flexible and Fast Digital Twin for RRAM Systems Applied for Training Resilient Neural Networks
M. Fritscher, S. Singh, T. Rizzi, A. Baroni, D. Reiser, M. Mallah, D. Hartmann, A. Bende, T. Kempen, M. Uhlmann, G. Kahmen, D. Fey, V. Rana, S. Menzel, M. Reichenbach, M. Krstic, F. Merchant, Ch. Wenger
Scientific Reports 14, 23695 (2024)
DOI: 10.1038/s41598-024-73439-z, (MIMEC)
Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).
(11) Area-Efficient Digital Design using RRAM-CMOS Standardcells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, M.A. Schubert, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2024), 81 (2024)
DOI: 10.1109/ISVLSI61997.2024.00026, (iCampus II)
(12) Area-Efficient Digital Design using RRAM-CMOS Standardcells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, M.A. Schubert, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2024), 81 (2024)
DOI: 10.1109/ISVLSI61997.2024.00026, (HYB-RISC)
(13) A Flexible and Fast Digital Twin for RRAM Systems Applied for Training Resilient Neural Networks
M. Fritscher, S. Singh, T. Rizzi, A. Baroni, D. Reiser, M. Mallah, D. Hartmann, A. Bende, T. Kempen, M. Uhlmann, G. Kahmen, D. Fey, V. Rana, S. Menzel, M. Reichenbach, M. Krstic, F. Merchant, Ch. Wenger
Scientific Reports 14, 23695 (2024)
DOI: 10.1038/s41598-024-73439-z, (iCampus II)
Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).
(14) Area-Efficient Digital Design using RRAM-CMOS Standardcells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, M.A. Schubert, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2024), 81 (2024)
DOI: 10.1109/ISVLSI61997.2024.00026, (KI-IoT)
(15) A Flexible and Fast Digital Twin for RRAM Systems Applied for Training Resilient Neural Networks
M. Fritscher, S. Singh, T. Rizzi, A. Baroni, D. Reiser, M. Mallah, D. Hartmann, A. Bende, T. Kempen, M. Uhlmann, G. Kahmen, D. Fey, V. Rana, S. Menzel, M. Reichenbach, M. Krstic, F. Merchant, Ch. Wenger
Scientific Reports 14, 23695 (2024)
DOI: 10.1038/s41598-024-73439-z, (6G-RIC)
Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).
(16) Over-the-Air 26 GHz Receiver Hardware-Software Evaluation towards Joint Communication and Radar Sensing
S. George, P. Sen, M. Umar, M. Matthe, J. Adler, M. Ramzan, C. Carta
Proc. 54th European Microwave Conference (EuMC 2024), 509 (2024)
DOI: 10.23919/EuMC61614.2024.10732620
(17) A Multi-Mode Direct Conversion Receiver for Joint Communication and Radar Sensing
S. George, P. Sen, C. Carta
Proc. 15th German Microwave Conference (GeMiC 2024), 229 (2024)
DOI: 10.23919/GeMiC59120.2024.10485239
(18) Realizing Joint Communication and Sensing RF Receiver Front-Ends: A Survey
S. George, P. Sen, C. Carta
IEEE Access 12, 9440 (2024)
DOI: 10.1109/ACCESS.2024.3351572
Joint Communication and radio Sensing (JC&S) has gained significant attention over the past few years. The advantages of this technology include reduced cost, size and power consumption. With further advancements in JC&S systems, it can potentially be used in next-generation cellular networks, internet-of-things and upcoming applications such as Industry 4.0, where a single system is capable of performing a wide variety of functions or tasks. The inclusion of this technology will result in improved performance and safety of the systems. Even though communication and radio sensing make use of a similar Radio Frequency (RF) front-end, the specifications for both these technologies mainly differ in terms of bandwidth and linearity. In this survey, a detailed study of the specifications of radar and communication was conducted. For the RF front-end to operate efficiently in both radar and communication modes, there must be reconfigurability in terms of frequency, bandwidth, gain and linearity. In this survey, we investigated different frequency, bandwidth, gain and linearity reconfigurable low noise amplifier (LNA) and down-conversion mixer architectures. The merits and demerits of each architecture are discussed and a summary of the performance of the reconfigurable LNAs and down-conversion mixers in the literature is presented. Finally, possible topologies for JC&S are deduced based on their performance.
(19) Design of Radiation-Tolerant Digital-to-Analog Converter and Investigation on Analog Single Event Transient Effects
A. Harneer Suresh, C. Carta, G. Fischer
AEÜ - International Journal of Electronics and Communications 187, 155503 (2024)
DOI: 10.1016/j.aeue.2024.155503, (AMX IP)
A circuit design methodology for space applications is presented with an 8-bit resistive digital-to-analog converter (DAC) with XY addressing mode and BiCMOS buffer designed in IHP’s 130 nm SiGe BiCMOS technology (SG13S). The radiation tolerance of the implemented DAC is evaluated by circuit-level simulations particularly analyzing the radiation sensitivity of the DAC to analog single-event transients (ASETs). Radiation mitigation techniques are addressed. The total current consumption with a 3.3 V supply is 0.54 mA at a 1 MHz sampling frequency.
(20) Circuit Design Methodology of Radiation-Tolerant DAC for Space Applications
A. Harneer Suresh, J.A. Singer, G. Fischer
Proc. PAnhellenic Conference on Electronics and Telecommunication (PACET 2024), (2024)
DOI: 10.1109/PACET60398.2024.10497042, (AMX IP)
(21) Jitter Minimization of Phase-Locked Loops for OFDM-Based Millimeter-Wave Communication Systems with Beam Steering
F. Herzel, C. Carta, G. Fischer
Proc. 31st IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2024), 19 (2024)
DOI: 10.23919/MIXDES62605.2024.10614043, (AMX IP)
(22) Jitter Minimization of Phase-Locked Loops for OFDM-Based Millimeter-Wave Communication Systems with Beam Steering
F. Herzel, C. Carta, G. Fischer
Proc. 31st IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2024), abstr. book 52 (2024)
DOI: 10.23919/MIXDES62605.2024.10613942, (AMX IP)
(23) Contactless Assessment of Physiological Parameters with a 61 GHz CW Medical Radar System
R. Holzschuh, H. Lu, B. Sütbas, A.E. Bezer, R. Freund, St. Ortmann, D.G. Meininghaus
Proc. iCampus Cottbus Conference (iCCC 2024), 53 (2024)
DOI: 10.5162/iCCC2024/2.3, (iCampus II)
(24) A Tunable Inductor Peaking Technique for Optical Communication Systems
F. Iseini, H.-T. Lin, N. Pelagalli, A. Malignaggi, C. Carta, G. Kahmen, A. Weisshaar
Proc. 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS 2024), 55 (2024)
DOI: 10.1109/EPEPS61853.2024.10753708, (100G)
(25) A Signal Source in J-Band with 237-287 GHz Tuning Range in a 130-nm SiGe BiCMOS Process
F.I. Jamal, T. Mausolf, M. Yazici, F. Vater, C. Carta, R. Scholz
Proc. 54th European Microwave Week (EuMW 2024), 114 (2024)
DOI: 10.23919/EuMIC61603.2024.10732403, (SMARTWAY)
(26) A 2.5 - 2.7 GHz Frequency-Tunable Band-Pass Delta-Sigma Modulator in a 0.25μm SiGe BiCMOS for Fiber-Wireless Digital Distributed Antenna Systems
S. Jang, B. Park, P. Ostrovskyy, J. Jung, K.-S. Kim, J.-H. Hwang
Proc. 50th European Conference on Optical Communications (ECOC 2024), 1220 (2024)
(27) Tunable True-Time-Delay Unit Based on Bridged T-Coil
H.T. Lin, F. Iseini, A. Weisshaar
Proc. 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS 2024), 56 (2024)
DOI: 10.1109/EPEPS61853.2024.10753922
(28) Influence of Stop and Gate Voltage on Resistive Switching of 1T1R HfO2-based Memristors, a Modeling and Variability Analysis
D. Maldonado, A. Cantudo, K.D.S. Reddy, S. Pechmann, M. Uhlmann, Ch. Wenger, J.B. Roldán, E. Pérez
Materials Science in Semiconductor Processing 182, 108726 (2024)
DOI: 10.1016/j.mssp.2024.108726, (KI-IoT)
Memristive devices, particularly resistive random access memory (RRAM) cells based on hafnium oxide (HfO₂) dielectrics, exhibit promising characteristics for a wide range of applications. In spite of their potential, issues related to intrinsic variability and the need for precise simulation tools and modeling methods remain a medium-term hurdle. This study addresses these challenges by investigating the resistive switching (RS) behavior of different 1T1R HfO₂-based memristors under various experimental conditions. Through a comprehensive experimental analysis, we extract RS parameters using different numerical techniques to understand the cycle-to-cycle (C2C) and device-to-device (D2D) variability. Additionally, we employ advanced simulation methodologies, including circuit breaker-based 3D simulation, to shed light on our experimental findings and provide a theoretical framework to disentangle the switching phenomena. Our results offer valuable insights into the RS mechanisms and variability, contributing to the improvement of robust parameter extraction methods, which are essential for the industrial application of memristive devices.
(29) A 434 MHz Wakeup Receiver Analog Frontend based on a Switched Injection-Triggered Oscillator with -91 dBm Input Sensitivity and 175 pJ/bit Efficiency
G. Meller, M. Methfessel, F. Protze, J. Wagner, F. Ellinger
Proc. 27th European Microwave Week (EuMW 2024), 251 (2024)
DOI: 10.23919/EuMIC61603.2024.10732288
(30) A 30GHz PLL with Automated Frequency Control Option for Robust Operation in Harsh Environments
A. Minareci Ergintav, F. Herzel, G. Fischer, D. Kissinger, C. Carta
Proc. 19th European Microwave Integrated Circuits Conference (EuMIC 2024), 34 (2024)
DOI: 10.23919/EuMIC61603.2024.10732750
(31) Vital Signs Monitoring using 61.4 GHz CW MIMO Radar Sensor with LO-Scalable Low-Voltage Low-Power SiGe BiCMOS Chipset
B. Sütbas, H.J. Ng, M.H. Eissa, C. Carta, G. Kahmen
Proc. 54th European Microwave Conference (EuMC 2024), 497 (2024)
DOI: 10.23919/EuMC61614.2024.10732052, (iCampus II)
(32) Vital Signs Monitoring using 61.4 GHz CW MIMO Radar Sensor with LO-Scalable Low-Voltage Low-Power SiGe BiCMOS Chipset
B. Sütbas, H.J. Ng, M.H. Eissa, C. Carta, G. Kahmen
Proc. 54th European Microwave Conference (EuMC 2024), 497 (2024)
DOI: 10.23919/EuMC61614.2024.10732052, (iCampus)
(33) Effect of the Temperature on the Performance and Dynamic Behaviour of HfO2-based RRAM Devices
G. Vinuesa, H. Garcia, S. Dueñas, H. Castan, I. Iñiguez-de-la-Torre, T. Gonzalez, K.D.S. Reddy, M. Uhlmann, Ch. Wenger, E. Perez
Proc. 245th ECS Meeting: Advancing Solid State & Electrochemical Science & Technology (ECS Meeting 2024), abstr. book 1297 (2024)
DOI: 10.1149/MA2024-01211297mtgabs, (KI-IoT)
(34) Towards Reliable and Energy-Efficient RRAM based Discrete Fourier Transform Accelerator
J. Wen, A. Baroni, E. Perez, M. Uhlmann, M. Fritscher, K. KrishneGowda, M. Ulbricht, Ch. Wenger, M. Krstic
Proc. 27th Design, Automation and Test in Europe (DATE 2024), (2024)
(6G-RIC)
(35) Fabrication and Implementation of BiCMOS BEOL Silicon Interposer Technologies with Integrated Metal Reflectors for Sub-THz Leaky-Wave Antennas
M. Wietstruck, P. Krüger, T. Voß, T. Mausolf, M.F. Bashir, A. Bhutani
Proc. 10th IEEE Electronics System-Integration Technology Conference (ESTC 2024), (2024)
DOI: 10.1109/ESTC60143.2024.10712047, (ESSENCE-6GM)
(36) A 60 GHz Broadband LNA with Joined Variable Gain Control and Switching in 22 nm FD-SOI
X. Xu, J. Wagner, C. Carta, F. Ellinger
IEEE Access 12, 111627 (2024)
DOI: 10.1109/ACCESS.2024.3441853
This paper investigates a 60 GHz low-power broadband low noise amplifier (LNA) with variable gain control. To prove the concept, the circuit is implemented in a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS technology. It supports broadband operation at 60 GHz achieved by gain peaking (gain distribution) technique. By tuning some key matching networks of the amplifier, the peak gain of each stage was distributed to different frequencies resulting in an overall broadband frequency response. The circuit consists of three cascaded cascode amplifier stages. Matching networks were optimized regarding bandwidth and noise figure. The transistor back-gate was used for LNA designs to switch the circuit to low-power standby mode. This avoids the problems of front-gate based switching regarding voltage breakdown and circuit stability. Additionally, simultaneous realization of variable gain control at such high frequencies was achieved via the back-gate. Compared to the front-gate based, the back-gate based variable gain control can deliver a continuous fine-tuning of the gain while requiring less accuracy or resolution of the control voltage. In the measurement, The gain was successfully tuned from 20 dB down to −25 dB via the back-gate. At a DC power of 8.1 mW from a nominal supply of 1 V, the LNA provides a peak gain of 20 dB, a bandwidth of 18.5 GHz, and a minimum noise figure of 3.3 dB. When biased at a reduced DC supply of 0.4 V, the presented circuit consumes only 2.5 mW of DC power, and still provides a power gain of 10 dB and a minimum noise figure of around 4.5 dB. By switching to standby mode, the LNA consumes 850 µW of DC power at the nominal supply and 240 µW at the reduced supply. The LNA compares well against previously reported designs by showing the lowest noise figure with competitive gain, bandwidth and DC power. To the authors’ knowledge, this is the first 60 GHz LNA featuring joined variable gain control and switching capability via solely back-gate biasing.
