Publications 2026
Script list Publications
(1) 230 - 330 GHz Microstrip Leaky-Wave Antenna Array using BiCMOS BEOL Silicon Interposer
A. Bhutani, J. Yin, E. Bekker, J. Dittmer, J. Blank, K. Joy, P. Krüger, T. Voß, C. Carta, M. Wietstruck, T. Zwick
Proc. 17th IEEE German Microwave Conference (GeMiC 2026), (2026)
(ESSENCE-6GM)
(2) Design and Characterization of a Differential UWB LNA Intended for Space Applications
A. Harneer Suresh, G. Fischer, D. Martynenko, F. Korndörfer, C. Carta
Proc. 17th German Microwave Conference (GeMiC 2026), (2026)
(AMX IP)
(3) Chessboard FPA in 130-nm SiGe BiCMOS for High-Resolution Passive Terahertz Imaging
M. Hoogelander, M. Spirito, B. Sütbas, C. Carta, N. Llombart, M. Alonso-delPino
IEEE Journal of Microwaves 6(2), 334 (2026)
DOI: 10.1109/JMW.2026.3660185, (Radar)
This work presents a chessboard focal plane array (FPA) camera with state-of-the-art thermal and spatial resolution in the 200–600GHz frequency range. The FPA is implemented in a 130-nm SiGe BiCMOS technology, where each antenna element is loaded with a direct detector based on heterojunction bipolar transistors (HBTs). The antenna and detector architecture, including the vias and biasing network, were optimized to achieve a noise-equivalent power (NEP) suitable for passive THz imaging. Overall, the estimated loss of the FPA is better than 4dB between 350 and 600GHz, of which 1.5dB is due to ohmic losses in the FPA, 1dB to mutual coupling between detectors, and 0.7dB to the impedance mismatch between the detector and antenna. A prototype of 24 pixels was manufactured and mounted on the base of a silicon hyperhemispherical lens with an anti-reflection coating. Excellent spatial resolution is achieved through a tight element spacing in the fabricated FPA, which is only half the wavelength in silicon at 350GHz and therefore consistent with the state-of-the-art. Its responsivity, noise, and radiation patterns were characterized using a quasi-optical measurement setup. The measured radiation patterns are within 1dB of simulations, demonstrating that the integrated THz camera achieves excellent spatial resolution. Between 330GHz and 500GHz, the NEP was measured to be on the order of 10pW/√Hz. When considering the entire operational band, this NEP results in a noise-equivalent temperature difference (NETD) of the camera is 1.6K for an integration time of 1s per pixel, which is comparable to the state-of-the-art. While THz detectors with state-of-the-art sensitivity are limited to single-pixel designs, the presented work combines a multi-pixel implementation with competitive sensitivity.
(4) A Tunable Bandwidth Equalization Technique for Optical Communication Systems
F. Iseini, H.-T. Lin, A. Malignaggi, C. Carta, A. Weisshaar, G. Kahmen
Proc. IEEE Radio & Wireless Week (RWW 2026), 57 (2026)
DOI: 10.1109/SiRF69501.2026.11408692
(5) Wideband 300 GHz Power Detectors in SiGe 130 nm BiCMOS Technology for BIST Applications
E. Jimenez Tuero, C. Herold, A. Malignaggi, C. Carta
Proc. 25th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2026), 33 (2026)
DOI: 10.1109/SiRF69501.2026.11408664, (6G-RIC)
(6) A Wideband Differential 300 GHz SPDT Switch with Low Insertion Loss in SiGe 130 nm BiCMOS Technology
E. Jimenez Tuero, A. Malignaggi, C. Carta
Proc. IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2026), 109 (2026)
DOI: 10.1109/SiRF69501.2026.11408704, (6G-RIC)
(7) ESCALAS: SiGe-BiCMOS RFICs with Built-In Self-Test and Analog Predistortion for Ka-, Q- and V-Band Satellite Payloads
S. Koch, A. Fischer, C. Bohn, M. Jutzi, L. Baumgärtner, A. Scharpf, B. Klingenberg, M. Schick, G. Fischer, F. Herzel, A. Haag, K. Smirnova, A. Aslan, S. Klimenko, A.C. Ulusoy, M.P. Scharpf, B.G. Özat, B. Schoch, I. Kallfass
Proc. 17th IEEE German Microwave Conference (GeMiC 2026), (2026)
(ESCALAS)
(8) High-Output Power Optically Injection-Locked Oscillator in 250 nm SiGe BiCMOS EPIC Technology
N. Pelagalli, A. Malignaggi, C. Carta
Proc. IEEE Radio & Wireless Week (RWW 2026), 89 (2026)
DOI: 10.1109/RWS64705.2026.11408741
(9) End-to-End Design Flow for Resistive Neural Accelerators
M. Uhlmann, T. Rizzi, E. Perez-Bosch Quesada, B. Al Beattie, K. Ochs, E. Perez, P. Ostrovskyy, C. Carta, Ch. Wenger, G. Kahmen
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 45(3), 1504 (2026)
DOI: 10.1109/TCAD.2025.3597237, (Neutronics)
Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP’s onetransistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies
exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.
(10) Silicon Interposer with Advanced RF Technology Modules for BiCMOS Wafer-Level Packaging
M. Wietstruck, P. Krüger, T. Voß, S. Schulze, M.F. Bashir, S. Tolunay Wipf, E.C. Durmaz, K. Joy, N. Hasnayen, B. Sütbas
Proc. 17th IEEE German Microwave Conference (GeMiC 2026), (2026)
(ESSENCE-6GM)
A. Bhutani, J. Yin, E. Bekker, J. Dittmer, J. Blank, K. Joy, P. Krüger, T. Voß, C. Carta, M. Wietstruck, T. Zwick
Proc. 17th IEEE German Microwave Conference (GeMiC 2026), (2026)
(ESSENCE-6GM)
(2) Design and Characterization of a Differential UWB LNA Intended for Space Applications
A. Harneer Suresh, G. Fischer, D. Martynenko, F. Korndörfer, C. Carta
Proc. 17th German Microwave Conference (GeMiC 2026), (2026)
(AMX IP)
(3) Chessboard FPA in 130-nm SiGe BiCMOS for High-Resolution Passive Terahertz Imaging
M. Hoogelander, M. Spirito, B. Sütbas, C. Carta, N. Llombart, M. Alonso-delPino
IEEE Journal of Microwaves 6(2), 334 (2026)
DOI: 10.1109/JMW.2026.3660185, (Radar)
This work presents a chessboard focal plane array (FPA) camera with state-of-the-art thermal and spatial resolution in the 200–600GHz frequency range. The FPA is implemented in a 130-nm SiGe BiCMOS technology, where each antenna element is loaded with a direct detector based on heterojunction bipolar transistors (HBTs). The antenna and detector architecture, including the vias and biasing network, were optimized to achieve a noise-equivalent power (NEP) suitable for passive THz imaging. Overall, the estimated loss of the FPA is better than 4dB between 350 and 600GHz, of which 1.5dB is due to ohmic losses in the FPA, 1dB to mutual coupling between detectors, and 0.7dB to the impedance mismatch between the detector and antenna. A prototype of 24 pixels was manufactured and mounted on the base of a silicon hyperhemispherical lens with an anti-reflection coating. Excellent spatial resolution is achieved through a tight element spacing in the fabricated FPA, which is only half the wavelength in silicon at 350GHz and therefore consistent with the state-of-the-art. Its responsivity, noise, and radiation patterns were characterized using a quasi-optical measurement setup. The measured radiation patterns are within 1dB of simulations, demonstrating that the integrated THz camera achieves excellent spatial resolution. Between 330GHz and 500GHz, the NEP was measured to be on the order of 10pW/√Hz. When considering the entire operational band, this NEP results in a noise-equivalent temperature difference (NETD) of the camera is 1.6K for an integration time of 1s per pixel, which is comparable to the state-of-the-art. While THz detectors with state-of-the-art sensitivity are limited to single-pixel designs, the presented work combines a multi-pixel implementation with competitive sensitivity.
(4) A Tunable Bandwidth Equalization Technique for Optical Communication Systems
F. Iseini, H.-T. Lin, A. Malignaggi, C. Carta, A. Weisshaar, G. Kahmen
Proc. IEEE Radio & Wireless Week (RWW 2026), 57 (2026)
DOI: 10.1109/SiRF69501.2026.11408692
(5) Wideband 300 GHz Power Detectors in SiGe 130 nm BiCMOS Technology for BIST Applications
E. Jimenez Tuero, C. Herold, A. Malignaggi, C. Carta
Proc. 25th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2026), 33 (2026)
DOI: 10.1109/SiRF69501.2026.11408664, (6G-RIC)
(6) A Wideband Differential 300 GHz SPDT Switch with Low Insertion Loss in SiGe 130 nm BiCMOS Technology
E. Jimenez Tuero, A. Malignaggi, C. Carta
Proc. IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2026), 109 (2026)
DOI: 10.1109/SiRF69501.2026.11408704, (6G-RIC)
(7) ESCALAS: SiGe-BiCMOS RFICs with Built-In Self-Test and Analog Predistortion for Ka-, Q- and V-Band Satellite Payloads
S. Koch, A. Fischer, C. Bohn, M. Jutzi, L. Baumgärtner, A. Scharpf, B. Klingenberg, M. Schick, G. Fischer, F. Herzel, A. Haag, K. Smirnova, A. Aslan, S. Klimenko, A.C. Ulusoy, M.P. Scharpf, B.G. Özat, B. Schoch, I. Kallfass
Proc. 17th IEEE German Microwave Conference (GeMiC 2026), (2026)
(ESCALAS)
(8) High-Output Power Optically Injection-Locked Oscillator in 250 nm SiGe BiCMOS EPIC Technology
N. Pelagalli, A. Malignaggi, C. Carta
Proc. IEEE Radio & Wireless Week (RWW 2026), 89 (2026)
DOI: 10.1109/RWS64705.2026.11408741
(9) End-to-End Design Flow for Resistive Neural Accelerators
M. Uhlmann, T. Rizzi, E. Perez-Bosch Quesada, B. Al Beattie, K. Ochs, E. Perez, P. Ostrovskyy, C. Carta, Ch. Wenger, G. Kahmen
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 45(3), 1504 (2026)
DOI: 10.1109/TCAD.2025.3597237, (Neutronics)
Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP’s onetransistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies
exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.
(10) Silicon Interposer with Advanced RF Technology Modules for BiCMOS Wafer-Level Packaging
M. Wietstruck, P. Krüger, T. Voß, S. Schulze, M.F. Bashir, S. Tolunay Wipf, E.C. Durmaz, K. Joy, N. Hasnayen, B. Sütbas
Proc. 17th IEEE German Microwave Conference (GeMiC 2026), (2026)
(ESSENCE-6GM)
