System Architectures

System Architectures department researches and develops high-end communication and embedded Systems

The System Architectures department strategically focuses on three important topics: Design and Test Methods for Digital Circuits, Fault tolerant Computing and Wireless Broadband Systems. The group of Design and Test Methods for Digital Systems is focused on providing the service activities to internal and external customers (ASIC design & test, chip integration) and applied research in industry projects. The group Fault Tolerant Computing investigates the following research areas: fault tolerance in computer architectures and multi-processors, design methodology for fault tolerant and radhard designs, intelligent sensing based on radar technology and reliable hardware for accelerating AI applications. The activities of the group Wireless Broadband Systems relate to 5G and Beyond 5G communication systems. Important topics of the IHP are primarily ranging and localization, which can be achieved with cooperative time-of-flight methods and non-cooperative radar methods. Another goal is high data throughput for fronthaul/backhaul networks, whereby wireless links with 100 Gbit/s and more are aimed for.

Technical Competencies

  • design of fault tolerant computer architectures and multi-processors
  • design methodology for fault tolerant, robust and radhard designs
  • digital signal processing for localization and ranging based on n-way ranging and radar technology
  • management and modelling of hardware for accelerating AI applications
  • highest data rate wireless communication (5G and Beyond-5G)
  • safety related WLAN for low latency systems
  • fronthaul/backhaul networks
  • signal processing for ultra-high speed at 60-300 GHz
  • ASIC design and test

Prof. Miloš Krstić

Department Head

Im Technologiepark 25
15236 Frankfurt (Oder)

Heike Wasgien
Phone: +49 335 5625 342
Fax: +49 335 5625 671 
Send e-mail »

Technical Basis

Facilities for Functional Test on Integrated Circuits

Production Test System - Advantest 93000

Power supply:
2xGP-DPS: 4 ch., max 16 A, ±8 V force/measure
MS-DPS: 8 ch., max 16 A, ±8 V force/measure
DPS32: 32 ch., max 48 A @ 3 V, 0-7 V force/measure
digital resources:
2xPS1600: 256 ch. @ 533 Mb/s, 32 ch. @ 1.6 Gb/s
1xPS9G: 64 ch. @ 800 Mb/s, 32 ch. @ 8 Gb/s
1xPSSL: 16 ch. @ 16 Gb/s

Analog resources:
Source 4 AWG, max 200 MHz @ 500 Ms/s
Measure 4 Digitizers, max 16 bit @ 300 MHz
V-Source, PMU, HPPMU multiplex

Additional software for memory test and scan test analysis
Supports manual package test and automatic wafer test (using the UF200 wafer prober)

Accretech UF200 wafer prober
Fully automatic wafer prober for up to 25 wafers/lot
Supports 6inch and 8inch wafers
Temperature controlled chuck, -40°C up to +125°C

Debugging Test System


  • pre-series & medium scale
    volume production tester
  • radiation test
  • power supply
    • 8 channels with 800 mA
    • 2 channels with 5 A
    • Voltage range -4 V to 10 V
  • digital resources
    • 4xM-D864: 256 ch @ 800 Mb/s
    • voltage range -1.5 V to 6.5 V

Binder MK 53 E2

  • climate chamber for endurance tests
  • temperature range: 40 ° to 150 °C
  • fully programmable & remotely controllable

Thermostream TP04300

  • mobile programmable temperature system
  • temperature performance:
    • Range: -75 ° to 228 °C
    • Transition: ±180 °C in < 10 s
    • Accuracy: 1 °C
  • DUT temperature sensors

Infrared camera

Spectral range 7.5 .. 14µm
Temperature measurement range -40°C .. 1200°C
Image size 640x480

Standard lens 1.0/30 mm
image area (30 x 23)°,
minimum distance 300mm

Microscope objective 1,0x
image (16 x 12) mm²,
distance 50 mm, resolution 25µm

up to 10 points

temperature of each pixel can be determined, additionally regions with min/max evaluation can be defined

e.g. detection of hot spots on chips (caused by shorts), thermal check of PCBs, etc.

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