Hybrid Integration Platform for Reliable High Frequency Circuits
The project HyTeck aims to develop a fan-out wafer-level packaging (FOWLP) platform for the hybrid integration of SiGe BiCMOS and GaN. The potential of this FOWLP technology will be evaluated in terms of high complexity, high power density and the combination of different technologies. A co-design environment will be developed, to ensure an efficient chip-package co-design, which is a key requirement for future high performance mm-wave packages.
IHP is responsible for the EM and thermal design of the FOWLP technology enabling the desired materials, the RDL layer stack and the design rules. In addition, IHP develops a design flow and environment enabling a highly efficient SiGe BiCMOS FOWLP packaging design.
This project is funded by the BMBF under grant agreement No 16ES0713.
- Rohde & Schwarz
- Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (IZM)
- Fraunhofer-Institut für Angewandte Festkörperphysik IAF
- AMIC Angewandte Micro-Messtechnik GmbH
- Unity Semiconductor GmbH