Fast De­sign En­able­ment

We sup­port IHP de­signer, ex­ter­nal project part­ners and cus­tomers to ac­cel­er­ate their de­sign cycle form de­sign idea to suc­cess­ful TAPE OUT.

For our qual­i­fied tech­nolo­gies we of­fer­ing tested and re­li­able process de­sign kits (PDKs) within state-​​of-the-art elec­tronic and op­ti­cal de­sign plat­forms. This en­ables de­sign­ers to ob­tain work­ing sil­i­con in their prod­uct de­vel­op­ment projects in the first TAPE OUT.

IHP stan­dard de­sign kits sup­port RF MMIC de­signs, mixed sig­nal de­signs and a dig­i­tal de­sign flow. Fur­ther­more spe­cial tools sup­port pas­sive de­vice sim­u­la­tion, ther­mal sim­u­la­tion and aging sim­u­la­tion.

A new area cov­ers ap­pli­ca­tions for harsh en­vi­ron­ments. Here we pro­vide and de­velop de­sign method­olo­gies for radiation-​​hardened de­sign.

As a re­search fa­cil­ity IHP is also of­fer­ing de­sign tool sup­port for tech­nolo­gies under de­vel­op­ment to offer de­sign­ers the pos­si­bil­ity to per­form de­signs for re­search and bench­mark stud­ies in a very early stage of de­vel­op­ment. For ex­am­ple PDK de­vel­op­ment is un­der­way for cryo­genic de­signs.

De­tailed doc­u­men­ta­tion, video tu­to­ri­als, and de­sign ex­am­ples are avail­able to learn the ins and outs of IHP PDKs. Reg­u­lar PDK tu­to­ri­als are of­fered to train new users and in­tro­duce new de­sign tools and fea­tures. A ded­i­cated sup­port ser­vice is avail­able through IHP’s PDK web plat­form. For spe­cial prob­lems, cus­tomers ob­tain an­swers di­rectly from IHP ex­perts.

The de­sign kits sup­port a Ca­dence mixed sig­nal plat­form

Ana­log/Mixed-​Signal Flow

• De­sign Frame­work II (Ca­dence 6.1)
• schematic De­sign Entry (Ca­dence Vir­tu­oso Schematic Ed­i­tor)
• sim­u­la­tion
  • Sim­u­la­tion Cock­pit: Ana­log De­sign En­vi­ron­ment – ADE (Ca­dence)
  • RF: Spec­tr­eRF (Ca­dence)
  • ana­log: Spec­tre/APS (Ca­dence)
  • mixed-​Signal: AMS De­signer/XPS (Ca­dence)
• full Cus­tom Lay­out (Ca­dence Vir­tu­oso Lay­out Ed­i­tor)
• phys­i­cal Ver­i­fi­ca­tion (Ca­dence As­sura: DRC/LVS, Ca­dence QRC: Par­a­sitic Ex­trac­tion, se­lected PDKs sup­port Sub­strate Noise Analy­sis)
• se­lected PDKs sup­port Ca­dence VPS for EMIR analy­sis
• sup­port of Ana­log Of­fice and TexEDA via part­ners is avail­able
• son­net sup­port for all de­sign kits
• ca­dence in­ter­op­er­a­ble ADS PDK in­clud­ing Mo­men­tum and Electro-​thermal sim­u­la­tion
• phys­i­cal ver­i­fi­ca­tion POLY­TEDA Pow­er­DRC/LVS and PV­CLOUD:
  • DRC/LVS, par­a­sitic ex­trac­tion and filler gen­er­a­tion
  • in­te­grated with Keysight ADS, Ca­dence Vir­tu­oso and TexEDA Lay­TOOLS en­vi­ron­ments

Dig­i­tal De­sign Flow

• dig­i­tal CMOS li­braries and IO Cells for 0.25 µm CMOS and 0.13 µm CMOS are avail­able:
  • Be­ha­vo­r­ial Mod­els (Ver­ilog)
  • Tim­ing Files (LIB)
  • Ab­stracts (LEF)
• dig­i­tal ECL Li­brary in a fu­ture re­lease (ad­di­tional fee)
• sim­u­la­tion: Mod­el­Sim (Men­tor Graph­ics), In­ci­sive En­ter­prise Sim­u­la­tor IES (Ca­dence)
• logic Syn­the­sis: De­sign Com­piler (Syn­op­sys), RTL Com­piler (Ca­dence)
• for­mal Ver­i­fi­ca­tion: For­mal­ity (Syn­op­sys)
• Scan In­ser­ta­tion and Test Pat­tern Gen­er­a­tion: DFT Com­piler/Tetra­Max (Syn­op­sys)
• Place & Route: En­counter Dig­i­tal Im­ple­men­ta­tion Sys­tem (Ca­dence)
  • OA views of dig­i­tal li­braries are avail­able for mixed sig­nal flow
• Power Analy­sis: Prime­Time with Prime­Power Op­tion (Syn­op­sys)
• Sta­tic Tim­ing Analy­sis: Prime­Time (Syn­op­sys)

Please con­sider that the lists above are non-​binding re­gard­ing the sup­ported tools and de­sign flows.  If you have any ques­tions please do not hes­i­tate to con­tact us.

On­line tu­to­ri­als are avail­able in our login area »