Fast Design Enablement

We support IHP designer, external project partners and customers to accelerate their design cycle form design idea to successful TAPE OUT.

For our qualified technologies we offering tested and reliable process design kits (PDKs) within state-​of-the-art electronic and optical design platforms. This enables designers to obtain working silicon in their product development projects in the first TAPE OUT.

IHP standard design kits support RF MMIC designs, mixed signal designs and a digital design flow. Furthermore special tools support passive device simulation, thermal simulation and aging simulation.

A new area covers applications for harsh environments. Here we provide and develop design methodologies for radiation-​hardened design.

As a research facility IHP is also offering design tool support for technologies under development to offer designers the possibility to perform designs for research and benchmark studies in a very early stage of development. For example PDK development is underway for cryogenic designs.

Detailed documentation, video tutorials, and design examples are available to learn the ins and outs of IHP PDKs. Regular PDK tutorials are offered to train new users and introduce new design tools and features. A dedicated support service is available through IHP’s PDK web platform. For special problems, customers obtain answers directly from IHP experts.

The design kits support a Cadence mixed signal platform

Analog/Mixed-Signal Flow

  • Design Framework II (Cadence 6.1)
  • schematic Design Entry (Cadence Virtuoso Schematic Editor)
  • simulation
    • Simulation Cockpit: Analog Design Environment – ADE (Cadence)
    • RF: SpectreRF (Cadence)
    • analog: Spectre/APS (Cadence)
    • mixed-Signal: AMS Designer/XPS (Cadence)
  • full Custom Layout (Cadence Virtuoso Layout Editor)
  • physical Verification (Cadence Assura: DRC/LVS, Cadence QRC: Parasitic Extraction, selected PDKs support Substrate Noise Analysis)
  • selected PDKs support Cadence VPS for EMIR analysis
  • support of Analog Office and TexEDA via partners is available
  • sonnet support for all design kits
  • cadence interoperable ADS PDK including Momentum and Electro-thermal simulation
  • physical verification POLYTEDA PowerDRC/LVS and PVCLOUD:
    • DRC/LVS, parasitic extraction and filler generation
    • integrated with Keysight ADS, Cadence Virtuoso and TexEDA LayTOOLS environments

Digital Design Flow

  • digital CMOS libraries and IO Cells for 0.25 µm CMOS and 0.13 µm CMOS are available:
    • Behavorial Models (Verilog)
    • Timing Files (LIB)
    • Abstracts (LEF)
  • digital ECL Library in a future release (additional fee)
  • simulation: ModelSim (Mentor Graphics), Incisive Enterprise Simulator IES (Cadence)
  • logic Synthesis: Design Compiler (Synopsys), RTL Compiler (Cadence)
  • formal Verification: Formality (Synopsys)
  • Scan Insertation and Test Pattern Generation: DFT Compiler/TetraMax (Synopsys)
  • Place & Route: Encounter Digital Implementation System (Cadence)
    • OA views of digital libraries are available for mixed signal flow
  • Power Analysis: PrimeTime with PrimePower Option (Synopsys)
  • Static Timing Analysis: PrimeTime (Synopsys)

Please consider that the lists above are non-binding regarding the supported tools and design flows.  If you have any questions please do not hesitate to contact us.

Online tutorials are available in our login area »

Dr.-Ing. Frank Vater

Im Technologiepark 25
15236 Frankfurt (Oder)

Phone: +49 335 5625 434
Send e-mail »

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