The Research & Prototyping Service (RPS) coordinates service- and industry-relevant design-enablement and prototyping activities within IHP’s Technology Department. It provides the operational interface between IHP’s semiconductor technology portfolio and its internal and external users, bringing together Process Design Kits (PDKs), technical customer support, Assembly Design Kits (ADKs), modelling, mask-data preparation, backend coordination and the software required to support these activities.
In close cooperation with IHP’s cleanroom, technology, circuit-design and system-design groups, RPS supports users from initial technology access and design-flow setup through to manufacturable layouts and functional prototypes.
RPS comprises three closely cooperating teams: Design Kit & Customer Support, ADK & Modelling, and Mask Preparation, Backend & Software. They support commercial, research-oriented and open-source design environments, as well as Multi-Project Wafer (MPW) including tape-out support, mask preparation back end activities to chip or package delivery.
RPS is primarily a service group; complementary national and European projects are used to extend its capabilities and translate project results into reusable tools, design infrastructure, training material and sustainable services for the semiconductor ecosystem.
Service and Application Areas
RPS enables internal research groups, universities, research organizations and industrial users in accessing and applying IHP technologies and translate them into designs that can be simulated, verified, fabricated, assembled and evaluated. Its service portfolio includes PDKs and their technical documentation, device and interconnect models, PCells, standard-cell and I/O-cell libraries, memory generators, DRC, LVS and parasitic-extraction decks, and the integration of commercial and open-source EDA tools. These resources are complemented by structured technical support, tutorials and onboarding material.
Standard customer support covers the correct use of the PDK and the associated design flow—including simulation, physical verification and extraction—while circuit-design consulting is not part of the standard service. For heterogeneous systems, RPS develops ADKs, component and interconnect models, and assembly-level design and verification methods for chiplets, interposers and their interconnections. At the manufacturing interface, the group supports layout registration, DRC at upload, test-field placement, frame and mask-data preparation, cleanroom documentation, dicing and wafer and chip traceability. This continuous service chain establishes clear handovers between design, fabrication and backend processing, helps identify avoidable errors before tape-out, and enables customers to plan prototype development realistically against fabrication schedules and tape-out constraints.
Regular Multi-Project Wafer runs provide access to IHP’s 0.13 μm and 0.25 μm SiGe BiCMOS technologies, silicon-photonics technologies and a silicon interposer technology for heterogeneous integration. New or adapted technologies can be used for research and benchmarking, while stable technologies support the development of functional prototypes. Stable and qualified technologies are also available for small-batch production through IHP Solutions.
The RPS service chain covers design enablement, design-flow support, heterogeneous-integration enablement, tape-out preparation, mask-data generation, backend processing and traceability. Where standard technology offerings are insufficient, RPS coordinates access to dedicated process steps, process modules, wafer preparations and short-flow developments, as well as wafer-level measurement and analytical diagnostics. Technology-transfer activities support the subsequent implementation of suitable IHP technologies and developments at commercial foundries. Together, these services establish clear handovers between design, fabrication, characterisation and backend processing and help users plan prototype development realistically against technical and fabrication constraints.
Main Service Objectives
- Provide reliable design enablement for commercial, research-oriented and open-source platforms.
- Develop, maintain and document PDK content and multi-tool design flows across IHP’s technology portfolio.
- Support users through structured technical support, application-oriented documentation, tutorials and onboarding.
- Provide access to MPW runs and dedicated prototyping services for research, benchmarking and functional-prototype development.
- Extend design enablement from individual dies to chiplet- and interposer-based assemblies through ADKs, modelling and assembly-level verification.
- Transform accepted layouts into fabrication-ready test fields and mask data and support the subsequent backend processing and traceability.
- Coordinate access to process and module services, wafer short-flow developments, wafer-level measurement, analytical diagnostics and technology transfer.
- Convert results from national and European projects into reusable, maintainable and scalable service capabilities.
Service Areas and Teams
Design Kit & Customer Support
Team lead: F. Vater
The team develops, maintains and supports Process Design Kits for IHP technologies across commercial and open-source EDA environments. Its scope includes process specifications and layout rules, device and interconnect models, PCells, standard and I/O-cell libraries, memory generators, DRC, LVS physical-verification, and parasitic-extraction decks, technical documentation and release management. As the interface between technology development, the cleanroom and PDK users, the team provides first-level and expert support for design-kit and design-flow questions. It also develops and delivers tutorials and onboarding material for commercial, academic, internal and open-source users.
ADK & Modelling
Team lead: F. I. Jamal
The team develops Assembly Design Kits and modelling methods for heterogeneous integration, enabling dies and chiplets from different semiconductor technologies to be combined within a coherent assembly-level design environment. Its activities include design enablement for silicon and glass interposers; assembly interconnects such as copper pillars, bumps, wire bonding, Al–Al bonding and through-silicon vias (TSVs); dedicated test structures; electrical-interconnect and electromagnetic modelling; assembly-level DRC; and KiCad/KLayout-based design workflows. A central objective is to establish consistent interfaces between die-level PDKs, interposer technologies, component and interconnect models, and assembly-level design rules. This enables multi-technology assemblies to be designed, verified and documented systematically before fabrication and physical assembly.
Mask Preparation, Backend & Software
Team lead: Simone Jätzlau
The team transforms customer and project layouts into fabrication-ready test fields and mask data. Its responsibilities include test-field registration, automated DRC at upload, placement of MPW and engineering-run layouts, preparation of frames and process-control-monitor (PCM) structures, CD and overlay marks, density fillers, optical proximity correction (OPC), mask tables, reticle data and cleanroom documentation. Backend activities include the coordination of blade and laser dicing, die-pick-up, wafer and chip traceability, archive management and mask-fix handling. The team also develops and operates the software supporting layout registration, data preparation, production handovers and traceability throughout the prototyping flow.
