Publications 2024

Script list Publications

(1) All-Epitaxial Self-Assembly of Silicon Color Centers Confined Within Sub-Nanometer Thin Layers Using Ultra-Low Temperature Epitaxy
J. Aberl, E.P. Navarrete, M. Karaman, D.H. Enriquez, C. Wilflingseder, A. Salomon, D. Primetzhofer, M.A. Schubert, G. Capellini, T. Fromherz, P. Deák, P. Udvarhelyi, L. Song, Á. Gali, M. Brehm
Advanced Materials 36(48), 2408424 (2024)
DOI: 10.1002/adma.202408424
Silicon-based color-centers (SiCCs) have recently emerged as quantum-light sources that can be combined with telecom-range Si Photonics platforms. Unfortunately, using conventional SiCC fabrication schemes, deterministic control over the vertical emitter position is impossible due to the stochastic nature of the required ion-implantation(s). To overcome this bottleneck toward high-yield integration, a radically innovative creation method is demonstrated for various SiCCs with excellent optical quality, solely relying on the epitaxial growth of Si and C-doped Si at atypically-low temperatures in an ultra-clean growth environment. These telecom emitters can be confined within sub-nm thick epilayers embedded within a highly crystalline Si matrix at arbitrary vertical positions. Tuning growth conditions and doping, different well-known SiCC types can be selectively created, including W-centers, T-centers, G-centers, and, especially, a so far unidentified derivative of the latter, introduced as G′-center. The zero-phonon emission from G′-centers at ≈1300 nm can be conveniently tuned by the C-concentration, leading to a systematic wavelength shift and linewidth narrowing toward low emitter densities, which makes both, the epitaxy-based fabrication and the G′-center particularly promising as integrable Si-based single-photon sources and spin-photon interfaces.

(2) A 220—320 GHz High Image Rejection Sideband Separating Receiver for Space-Borne Observatories
E.M. Al Seragi, Y.L. Rajendra, W. Ahmad, M. Kaynak, P.F. Goldsmith, S. Zeinoladedinzadeh
IEEE Transactions on Terahertz Science and Technology 14(2), 162 (2024)
DOI: 10.1109/TTHZ.2024.3349483
This work presents a novel terahertz THz sideband separating receiver (SSR) implemented in silicon germanium (SiGe) 0.13 μm BiCMOS technology that covers a broad frequency range of 220-320 GHz. The proposed architecture provides simultaneous observation of spectral lines with high image rejection ratio (IRR) across the entire operating frequency range. The double down conversion architecture with a first mixer operating as a sub-harmonic mixer was configurated as a sideband separating receiver leveraging the Weaver topology to provide two differential channels, one for the upper sideband (USB) and one for the lower sideband (LSB). The presented design demonstrates an IRR exceeding 20 dB across the entire frequency range of 220-320 GHz, without the need for calibration. To the best of the author's knowledge, this is the first reported H-band simultaneous sideband separation receiver in silicon technology. The fabricated receiver measures 1.2×1 mm2 and consumes 19 mW (not including LO power consumption), showcasing its potential for application in multiple-pixel arrays for space-borne observations.

(3) Adhesive-Free Bonding for Hetero-Integration of InP based Coupons Micro-Transfer Printed on SiO2 into Complementary Metal-Oxide-Semiconductor Backend for Si Photonics Application on 8” Wafer Platform
K. Anand, P. Steglich, J. Kreissl, C.A. Chavarin, D. Spirito, M. Franck, G. Lecci, I. Costina, N. Herfurth, J. Katzer, Ch. Mai, A. Becker, J.P. Reithmaier, L. Zimmermann, A. Mai
Thin Solid Films 799, 140399 (2024)
DOI: 10.1016/j.tsf.2024.140399, (FMD)
Micro-Transfer printing (µTP) is a promising technique for hetero-integration of III-V materials into Si-based photonic platforms. To enhance the print yield by increasing the adhesion between the III-V material and Si or SiO2 surface, an adhesion promoter like Benzocyclobutene is typically used as interlayer. In this work, we demonstrate µTP of InP based coupons on SiO2 interlayer without any adhesive interlayer and investigate the mechanism of adhesive free bonding. Source coupons are InP-based coupon stacks on a sacrificial layer that is removed by a chemical wet etch with FeCl3. For the target we fabricated amorphous-Si waveguides on 8" wafer encapsulated by a High Density Plasma SiO2 which was planarized by a chemical mechanical polishing procedure. We used O2 plasma to activate both source and target to increase adhesion between coupon and substrate. To get a better understanding of the bonding mechanism we applied several surface characterization methods. Root mean square roughness of InP and SiO2 was measured by atomic force microscopy before and after plasma activation. The step height of the micro-transfer printed source coupon on the target wafer is estimated by optical step profiler. We used Raman peak position mappings of InP to analyze possible strain and contact angle measurements on SiO2, before and after plasma activation to observe a change in the hydrophilicity of the surface. X-ray Photoelectron Spectroscopy analysis was used to characterize the surface energy states of P2p, In3d, O1s for InP source and Si2p, O1s for SiO2 target. Our results demonstrate direct bonding of InP coupons by means of µTP without the need of a strain-compensation layer. In this way, a promising route towards Complementary Metal-Oxide-Semiconductor compatible use of µTP for the hetero-integration of InP is provided.

(4) Adhesive-Free Bonding for Hetero-Integration of InP based Coupons Micro-Transfer Printed on SiO2 into Complementary Metal-Oxide-Semiconductor Backend for Si Photonics Application on 8” Wafer Platform
K. Anand, P. Steglich, J. Kreissl, C.A. Chavarin, D. Spirito, M. Franck, G. Lecci, I. Costina, N. Herfurth, J. Katzer, Ch. Mai, A. Becker, J.P. Reithmaier, L. Zimmermann, A. Mai
Thin Solid Films 799, 140399 (2024)
DOI: 10.1016/j.tsf.2024.140399, (PEARLS)
Micro-Transfer printing (µTP) is a promising technique for hetero-integration of III-V materials into Si-based photonic platforms. To enhance the print yield by increasing the adhesion between the III-V material and Si or SiO2 surface, an adhesion promoter like Benzocyclobutene is typically used as interlayer. In this work, we demonstrate µTP of InP based coupons on SiO2 interlayer without any adhesive interlayer and investigate the mechanism of adhesive free bonding. Source coupons are InP-based coupon stacks on a sacrificial layer that is removed by a chemical wet etch with FeCl3. For the target we fabricated amorphous-Si waveguides on 8" wafer encapsulated by a High Density Plasma SiO2 which was planarized by a chemical mechanical polishing procedure. We used O2 plasma to activate both source and target to increase adhesion between coupon and substrate. To get a better understanding of the bonding mechanism we applied several surface characterization methods. Root mean square roughness of InP and SiO2 was measured by atomic force microscopy before and after plasma activation. The step height of the micro-transfer printed source coupon on the target wafer is estimated by optical step profiler. We used Raman peak position mappings of InP to analyze possible strain and contact angle measurements on SiO2, before and after plasma activation to observe a change in the hydrophilicity of the surface. X-ray Photoelectron Spectroscopy analysis was used to characterize the surface energy states of P2p, In3d, O1s for InP source and Si2p, O1s for SiO2 target. Our results demonstrate direct bonding of InP coupons by means of µTP without the need of a strain-compensation layer. In this way, a promising route towards Complementary Metal-Oxide-Semiconductor compatible use of µTP for the hetero-integration of InP is provided.

(5) Towards Passive Imaging with Uncooled, Low-NEP SiGe HBT Terahertz Direct Detectors
M. Andree, J. Grzyb, H. Rücker, U.R. Pfeiffer
IEEE Transactions on Terahertz Science and Technology 14(5), 632 (2024)
DOI: 10.1109/TTHZ.2024.3432619
This work focuses on a systematic analysis of the potential as well as the limitations of modern SiGe HBT devices for broadband passive room-temperature detection in the lower THz range. Multiple necessary conditions need to be fulfilled to facilitate broadband passive imaging with a sufficiently low in-band NEP, which refer to various technology-driven device operation aspects, including the rectification process at THz frequencies and low-frequency analysis. Considering a strong frequency dependence of the devices' inherent rectification potential, an in-depth understanding and proper modeling of the device internal parasitics in combination with antenna-detector co-design aspects are crucial for successful detector implementation. For that purpose, a simplified nonlinear high-frequency detector model was applied for the device operating not only in the classical forward-active region but also in deep saturation (cold operation). The complete detector was implemented in a modern high-speed 130 nm SiGe HBT technology with ft/fmax of 470/650 GHz. It comprises two independent orthogonal polarization paths within a single dual-polarization lens-coupled on-chip antenna to operate with unpolarized passive illumination. With the aid of an efficient antenna-circuit co-design, a close-to-optimum detector performance in a near-THz fractional bandwidth can be achieved, as experimentally verified in free-space with frequency-tunable coherent CW sources. In particular, the detector optical NEP for each independent polarization path was measured across 200–1000 GHz reporting state-of-the-art values of 2.3–23 pW/√Hz$ and 4.3–45 pW/√Hz with the device operating in the forward-active range and in saturation, respectively. This, in combination with the de-embedded equivalent noise bandwidth of 512 GHz centered around 430 GHz, allowed to demonstrate the corresponding 1-Hz defined NETD of 0.86 K and 2 K in a focused measurement setup with a cavity black-body standard chopped mechanically at 1.5 kHz. With a simultaneous dual-channel operation, the NETD scaled down to 0.64 K, indicating near-zero noise correlation between both polarization paths.

(6) Leveraging Lookup Tables for Efficient LDO Design Exploration using Open-Source CAD Tools and IHP-Open130-G2 PDK
D. Arevalos, J. Marin, C. Rojas, K. Herman
31st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2024), abstr. book 53 (2024)

(7) A Highly Efficient 240-GHz Power Amplifier in 0.13-μm SiGe
K. Balaban, M. Kaynak, A.C. Ulusoy
IEEE Microwave and Wireless Technology Letters (MWTL) 34(1), 88 (2024)
DOI: 10.1109/LMWT.2023.3328934
This letter presents the design and experimental characterization of a highly efficient WR3.4-band power amplifier (PA) using 0.13-μm SiGe technology. The realized differential cascode PA demonstrates a high efficiency, owing to the gm-boosting technique which enables a relatively higher small-signal gain per stage. The proposed PA exhibits a saturated output power of 10.48 dBm with a maximum power-added-efficiency (PAE) of 5.46% at 240 GHz , which is a leading-edge performance among the reported silicon (Si)-based WR3.4-band PAs. The small-signal gain peaks at 24.1 dB and the PA has a 3-dB bandwidth of 21 GHz.

(8) Design and Investigation of 2x2 Dielectric Resonator Antennas Array for sub-THz Applications
M.F. Bashir, M. Wietstruck
18th European Conference on Antennas and Propagation (EuCAP 2024), (2024)
DOI: 10.23919/EuCAP60739.2024.10501657

(9) Design of 240 GHz Dielectric Resonator Antenna in 130 nm SiGe BiCMOS Process
M.F. Bashir, M. Wietstruck
15th German Microwave Conference (GeMIC 2024), 73 (2024)
DOI: 10.23919/GeMiC59120.2024.10485246

(10) Sub-THz Substrate Integrated Waveguide Signal Transitions in Backend-of-Line of a Silicon Process
A. Bhutani, M. Kaynak, M. Wietstruck, E. Bekker, I.K. Aksoyak, J. Hebeler, T. Zwick
Proc. 18th European Conference on Antennas and Propagation (EuCAP 2024), (2024)
DOI: 10.23919/EuCAP60739.2024.10501393

(11) Sub-THz Beam-Steering Antenna in Silicon Interposer Technology
A. Bhutani, L. Valenziano, P. Krüger, T. Voß, T. Zwick, C. Carta, M. Wietstruck
Proc. 27th IEEE European Microwave Week (EuMW 2024), 808 (2024)
DOI: 10.23919/EuMC61614.2024.10732488, (ESSENCE-6GM)

(12) Innovations in Electronics – Friend or Foe in Achieving Sustainability?
M. Birkholz
Proc. Electronics Goes Green Conference (EGG 2024), 231 (2024)
(Bioelectronics)

(13) The Assembly Investigation of a Multichip to PCB Flip-Chip Package using Cu Pillar Bumps
Z. Cao, J. Lehmann, B. Heusdens, E.C. Durmaz, P. Krüger, M. Wietstruck, N. Herfurth, A.A. Adesunkanmi, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 14(9), 1661 (2024)
DOI: 10.1109/TCPMT.2024.3443599, (FLEXCOM)
This article conducts a comprehensive investigation of the assembly technologies of a Cu pillar-based multichip flip-chip package with low-cost PCB substrates. Such a package is considered as a cost-effective solution for mm-wave broadband applications below 60 GHz. Three main trend flip-chip assembly methods are compared: mass reflow soldering, Cu pillar thermocompression soldering, and Au-Cu thermocompression bonding (TCB). Within these three assembly approaches, both the samples used for assembly and the assembly conditions are systematically compared. Specifically, Cu pillars with and without solder caps, PCB substrates with different solder mask thicknesses, PCB substrates with different glass transition temperatures, and different bonding compression forces are carried out in different assembly approaches. After the assembly, the assembly yield and contact resistance per bump are examined by meander daisy chain resistance measurement and the bonding qualities of both the whole chip and individual bumps are inspected using shear testing and cross sectioning. Findings reveal that reflow soldering offers advantages for high-volume, cost-effective assemblies despite a slightly lower yield, and the Au-Cu TCB exhibits a very high yield with diminished throughput. Whereas, Cu pillar thermocompression soldering does not manifest advantages over the other two approaches. This meticulous investigation enhances the accessibility of the discussed packaging approach, contributing to the groundwork for future technological advancements in this domain.

(14) The Chip-Level in-Plane Stress Distribution over BiCMOS Wafers
Z. Cao, T. Voss, M. Wietstruck, C. Carta, M. Kaynak
Proc. 24th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2024), 45 (2024)
DOI: 10.1109/SiRF59913.2024.10438504, (FLEXCOM)

(15) Optimization of the Metal Deposition Process for the Accurate Estimation of Low Metal-Graphene Contact-Resistance
D. Capista, R. Lukose, F. Majnoon, M. Lisker, Ch. Wenger, M. Lukosius
Proc. 47th International ICT and Electronics Convention (MIPRO 2024), 1561 (2024)
DOI: 10.1109/MIPRO60963.2024.10569895, (2D-EPL)

(16) A 300 GHz x9 Multiplier Chain with 9.6 dBm Output Power in 0.13-μm SiGe Technology
A. Chandra-Prabhu, J. Grzyb, P. Hillger, T. Bücher, H. Rücker, U. Pfeiffer
Proc. 24th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2024), 37 (2024)
DOI: 10.1109/SiRF59913.2024.10438581, (DFG-Dotseven2IC)

(17) Polarization-Resolved Raman Spectroscopy Reveals the Atomic Local Ordering in Silicon Germanium Tin Epitaxial Alloys
A.A. Corley-Wiciak, O. Concepción, M.H. Zoellner, G. Sfruncia, F. Bärwolf, G. Nicotra, D. Grützmacher, D. Buca, G. Capellini, D. Spirito
Physical Review Materials 8(10), 104601 (2024)
DOI: 10.1103/PhysRevMaterials.8.104601, (SiGeSn TE)
Ternary SiGeSn alloys have emerged as a promising material system for applications in
diverse fields such as photonics, electronics, and thermoelectrics. Its development still requires understanding the alloy properties, where an important role is alleged to the local arrangement of the Si, Ge, and Sn atoms. Structural properties of SiGeSn epitaxial layers deposited on Ge/Si virtual substrates are here investigated by polarized Raman spectroscopy; in particular, we selected a series of samples with Ge content of ~83 at.% and variable Si and Sn content. This technique, which provides access not only to the energy but also to the symmetry of the vibrational modes, makes it possible to observe the effect of composition on the local alloy ordering. By studying how the Raman modes change the energy and the relative intensity variation under different polarization configurations, we could isolate the role of alloy configuration as the composition varies. High Sn content appears to promote local ordering, as Sn atoms tend to repel other Sn and Si atoms. Our results are potentially of great interest in elucidating SiGeSn material properties that are still debated in the literature, e.g., the influence of composition on the bandgap directness of the alloy.

(18) Advancements in the Cu Pillar based PCB Microfluidic System Integration with SiGe BiCMOS Technology
E.C. Durmaz, C. Heine, Z. Cao, D. Kissinger, M. Wietstruck
Proc. Smart System Integration International Conference and Exhibition (SSI 2024), (2024)
DOI: 10.1109/SSI63222.2024.10740547, (DFG-THz LoC)

(19) A 240-GHz VMPS with 1.2° and 0.35 dB RMS Errors in 130 nm BiCMOS:C Technology
M.H. Eissa, Ch. Wipf, A. Malignaggi, G. Kahmen
IEEE Microwave and Wireless Technology Letters (MWTL) 34(3), 295 (2024)
DOI: 10.1109/LMWT.2024.3357203
This work presents a low phase error (PE) and amplitude error (AE) vector modulator phase shifter (VMPS) in the J -band. The influence of the IQ crosstalk RF impairment on the performance is analyzed for different vector summation implementations, guiding to the VMPS architecture choice and design optimization. The chosen architecture consists of an IQ analog-controlled voltage-gain amplifier (IQ-VGA), Branchline coupler, and a Wilkinson combiner. Test structures for the variable-gain amplifier (VGA) and the VMPS are manufactured and measured in a 130-nm BiCMOS technology (fT / fmax = 300/500 GHz). For the phase resolution of 11.25°, the VMPS achieves an average rms PE and AE of 1.2° and 0.35 dB, respectively, with equivalent to 5.5 -bits control voltage across the frequency band 220–260 GHz. The VMPS consumes 60 mW from 2.5-V supply and occupies 0.2 mm 2 of silicon area. This work presents the least PE and AE across a wide bandwidth for VMPS in silicon technologies above 200 GHz, which is crucial for large-scale beam-steering arrays.

(20) Epitaxial Growth of Nd2O3 Layers on Virtual SiGe Substrates on Si(111)
H. Genath, M.A. Schubert, H. Yamtomo, J. Krügener, H.J. Osten
Journal of Applied Physics 135(11), 115302 (2024)
DOI: 10.1063/5.0191350
This study explores the growth and structural characteristics of Nd2O3 layers on virtual germanium-rich SiGe substrates on Si(111). We focus on the emergence of the hexagonal phase depending on the stoichiometry of the virtual substrate. X-ray diffraction measurements reveal a hexagonal phase when Nd2O3 is grown directly on Si(111), while growth on Ge leads to a cubic oxide structure. On SiGe layers, the growth of the oxide results in a mixed phase containing hexagonal and cubic regions, regardless of the Ge content. The cubic structure grown on virtual Ge substrates exhibits strong tensile strain, while layers grown on SiGe layers show no strain. In situ growth control via electron diffraction shows a dependence of the oxide structure of the surface reconstruction of the virtual substrate. Growth on a 7×7 reconstruction leads to hexagonal parts on Si-based substrates, while growth on c(2×8) results in cubic oxide growth on Ge. Furthermore, oxide layers grown on virtual SiGe substrates form an interfacial silicate layer. The thickness of the interfacial layer is influenced by the Si content and the structure of the oxide layer enabling oxygen diffusion pathways.

(21) Improving Epitaxial Growth of γ-Al2O3 Films via Sc2O3/Y2O3 Oxide Buffers
S. Gougam, M.A. Schubert, D. Stolarek, S.B. Thapa, M.H. Zoellner
Advanced Materials Interfaces 221(12), 2400228 (2024)
DOI: 10.1002/pssa.202400228, (GaN HEMT support)
Heteroepitaxial growth of γ-Al2Oon Sc2O3/Y2O3/Si (111) is achieved with oxygen plasma-assisted molecular beam epitaxy in order to prevent polycrystalline grain boundary formation caused by lattice mismatch. Substrate temperature as well as oxygen flow are adjusted to optimize epitaxial growth conditions around 715–760 °C and 1.9 sccm, respectively. Epitaxial growth is monitored in situ by reflection high-energy diffraction, while surface morphology is studied by scanning electron microscopy ex-situ. X-ray diffraction indicates epitaxial out-of-plane 111 orientation with oxygen flow above 0.6 sccm. However, transmission electron microscopy shows stacking fault formation for high oxygen flows. Finally, nanobeam electron diffraction confirms Smrčok model of a spinel-like γ-Al2O3 crystal structure.

(22) FOSS CAD for the Compact Verilog-A Model Standardization in Open Access PDKs
W. Grabinski, R. Scholz, J. Verley, E.R. Keiter, H. Vogt, D. Warning, P. Nenzi, F. Lannutti, F. Salfelder, A. Davis, M. Brinson, B. Virdee, G. Torri, D. Tomaszewski, M. Bucher, J.-M. Sallese, M. Müller, P. Kuthe, M. Krattenmacher
Proc. 8th IEEE Electron Devices Technology and Manufacturing (EDTM 2024), (2024)
DOI: 10.1109/EDTM58488.2024.10511990, (FMD-QNC)

(23) An On-Chip Antenna-Coupled Preamplified D-Band to J-Band Total Power Radiometer Chip in 130 nm SiGe BiCMOS Technology
J. Grzyb, M. Andree, H. Rücker, U.R. Pfeiffer
Proc. IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2024), 359 (2024)
DOI: 10.1109/RFIC61187.2024.10599964

(24) Structural and Morphological Properties of CeO2 Films Deposited by Radio Frequency Magnetron Sputtering for Back-End-of-Line Integration
A. Hayat, M. Ratzke, C.A. Chavarin, M.H. Zoellner, A.A. Corley-Wiciak, M.A. Schubert, Ch. Wenger, I.A. Fischer
Thin Solid Films 807, 140547 (2024)
DOI: 10.1016/j.tsf.2024.140547, (iCampus II)
Cerium oxides have potential applications ranging from low-temperature gas sensing to photodetection. A back-end-of-line integration of the material into complementary metal-oxide-semiconductor device fabrication processes has many advantages but places limits on material deposition, most notably the thermal budget for deposition and annealing. Here, we investigate thin cerium oxide films deposited by radio frequency (RF) magnetron sputtering at substrate temperatures of 300°C and RF magnetron powers between 30 W and 70 W without any post-deposition annealing steps. Our investigation of the structural and morphological properties reveals a columnar texture of the thin films, and we find that the material is composed predominantly of CeO2 (111), with a large degree of crystallinity. We discuss implications for resistive gas sensing applications.

(25) Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design – A Review of the Final Stage of Project HEP
T. Henkes, S. Reith, M. Stöttinger, N. Herfurth, G. Panic, J. Wälde, F. Buschkowski, P. Sasdrich, C. Lüth, M. Funck, T. Kiyan, A. Weber, D. Boeck, R. Rathfelder, T. Grawunder
Proc. 27th Design, Automation and Test in Europe (DATE 2024), (2024)
(VE-HEP)

(26) Design and Simulation of Si-Photonic Nanowire-Waveguides with DEP Concentration Electrodes for Biosensing Applications
A. Henriksson, P. Neubauer, M. Birkholz
zu finden unter: https://arxiv.org/abs/2406.19534
(Bioelectronics)

(27) Novel Backside IC Preparation Stopping on STI with Full Circuit Functionality using Chemical Mechanical Polishing (CMP) with Highly Selective Slurry
N. Herfurth, A.A. Adesunkanmi, A. Bouchtouq, G. Zwicker, C. Boit
Proc. 50th International Symposiums for Testing and Failure Analysis (ISTFA 2024), 416 (2024)
DOI: 10.31399/asm.cp.istfa2024p0416

(28) Półprzewodnikowa Rewolucja w Domenie Open Source
K. Herman, A. Sojka-Piotrowska
Elektronika Praktyczna 5, (2024)
(FMD-QNC)
The keyword "open source" is associated by most people primarily with software developed by IT enthusiasts and made available for free to the worldwide community of users. No less interesting is the group of open hardware solutions so called open source hardware. A few people know that there are already free software packages designed to design integrated circuits, including even ASICs with bandwidths of hundreds of GHz. Even more surprising may be the fact that semiconductor factories are also opening their doors to small businesses, academic partners and even.... private customers!

(29) Reflections on the First European Open Source PDK by IHP – Experiences After One Year and Future Activities
K. Herman, R. Scholz, S. Andreev
Proc. 31st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2024), 19 (2024)
DOI: 10.23919/MIXDES62605.2024.10614043

(30) Jak zaprojektować i wyprodukować układ scalony bez nakładów finansowych?
K. Herman, A. Sojka-Piotrowska
Elektronika Praktyczna 6, (2024)
(FMD-QNC)
W poprzednim miesiącu obiecaliśmy Czytelnikom zarówno szczegółowy opis rozwiązań implementowanych w instytucie IHP (Leibniz-Institute for High Performance Microelectronics), a służących projektowaniu układów scalonych – jak i prezentację nadchodzących programów Open MPW (Multi Project Wafer), które umożliwiają darmowe opracowanie prototypów układów półprzewodnikowych w technologii SG13G2 BiCMOS 130 nm.

(31) On the Versatility of the IHP BiCMOS Open Source and Manufacturable PDK: A Step Towards the Future where Anybody can Design and Build a Chip
K. Herman, N. Herfurth, T. Henkes, S. Andreev, R. Scholz, M. Müller, M. Krattenmacher, H. Pretl, W. Grabinski
IEEE Solid-State Circuits Magazine 16(2), 30 (2024)
DOI: 10.1109/MSSC.2024.3372907, (FMD-QNC)
In this article, we introduce the first European opensource process design kit, namely IHP-Open130-G2. We provide a concise history of the PDK itself and offer a brief comparison with some alternative open-source PDKs, such as SKY130 and GF180. The article also includes a process description and details on deliverables, offering insights into available devices, models, supported open-source tools, and workflows. As the IHPOpen130-G2 is currently under development, we present key points outlining future activities. This aims to inform and attract users to join the open-source silicon community. The concluding section of the article compares measurement results for active devices with compact model results. The article concludes with a cryptographic IP core based on IHP-Open130-G2 as an exemplary use case.

(32) Optical Properties of Multilayered Staggered SiGe Nanodots Depending on Si Spacer Growth Temperature
Y. Ito, R. Yokogawa, W.-C. Wen, Y. Yamamoto, A. Ogura
ECS Transactions 114(2), 207 (2024)
DOI: 10.1149/11402.0207ecst
The optical properties of the multilayered staggered SiGe nanodots (NDs) embedded in the Si spacers fabricated at varying Si growth temperatures are clarified in conjunction with the effect of strain by Photoluminescence (PL) and Raman spectroscopy. We found that compressive strain is induced in the SiGe NDs, with higher growth temperatures of the Si spacer resulting in stronger compressive strain. PL spectra indicate that the higher growth temperature leads to a wider bandgap. This transition energy behavior is caused by not only the strain in the SiGe NDs but also the Ge segregation. Furthermore, luminescence from the SiGe NDs was observed along with luminescence originated at the Si/SiGe interface in the SiGe NDs with a small dot size. This phenomenon was caused by the small energy difference of the conduction-band minima between the SiGe NDs and the tensile-strained Si spacers and the small volume of the tensile-strained Si spacers.

(33) Strain and Optical Characteristics Analyses of 3-Dimentional Self-Ordered Multilayered SiGe Nanodots by Photoluminescence and Raman Spectroscopy
Y. Ito, R. Yokogawa, W.-C. Wen, Y. Yamamoto, T. Minowa, A. Ogura
Japanese Journal of Applied Physics 63(3), 035SP61 (2024)
DOI: 10.35848/1347-4065/ad231e
The strain state, optical properties, and band structure of the self-ordered multilayered silicon-germanium (SiGe) nanodots, which are staggered and dot-on-dot alignment and embedded by Si spacer, were evaluated by Raman spectroscopy and low-temperature Photoluminescence (PL). These results suggest that the compressive strain applied to the staggered nanodots is smaller than that of the dot-on-dot nanodots, which contributes to the shrinking of the bandgap of the staggered nanodots. Strong PL intensity was observed from the nanodots compared to the single crystalline bulk SiGe due to the carrier confinement and high crystal quality of the nanodots. The stack-controlled nanodots showed a redshift of the PL peaks compared to the bulk SiGe and the effect of strain induced in SiGe nanodots might not be enough to explain this phenomenon. The cause of the redshift was clarified by considering the hetero band structure of the nanodots and the tensile strained spacer.

(34) Optical Properties of Multilayered Staggered SiGe Nanodots Depending on Si Spacer Growth Temperature Evaluated by Raman and PL Spectroscopy
Y. Ito, R. Yokogawa, W.C. Wen, Y. Yamamoto, T. Minowa, R. Fujimori, A. Ogura
Proc. Pacific Rim Meeting on Electrochemical and Solid-State Science (PRIME 2024), (2024)

(35) A Signal Source in J-Band with 237-287 GHz Tuning Range in a 130-nm SiGe BiCMOS Process
F.I. Jamal, T. Mausolf, M. Yazici, F. Vater, C. Carta, R. Scholz
Proc. 54th European Microwave Week (EuMW 2024), 114 (2024)
DOI: 10.23919/EuMIC61603.2024.10732403, (SMARTWAY)

(36) Complex Electro-Optic Frequency-Response Characterization of a Si Ring Modulator
Y. Jo, Y Ji, H.-K. Kim, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2024), WA4 (2024)
DOI: 10.1109/SiPhotonics60897.2024.10544200, (MPW_ePIC)

(37) Integration Concept of Plasmonic TiN Nanohole Arrays in a 200 mm BiCMOS Si Technology for Refractive Index Sensor Applications
J. Jose, Ch. Mai, S. Reiter, Ch. Wenger, I.A. Fischer
Proc. iCampus Cottbus Conference (iCCC 2024), 96 (2024)
DOI: 10.5162/iCCC2024/7.2, (iCampus)

(38) Novel Monolithic All-Silicon Coherent Transceiver Sub-Assembly based on Ring Modulators
Y. Jo, M. Oberon, A. Peczek, Y. Ji, M. Kim, H.-K. Kim, M.-H. Kim, P.M. Seiler, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
IEEE Journal of Lightwave Technology 42(20), 7298 (2024)
DOI: 10.1109/JLT.2024.3421919
We demonstrate a novel monolithic coherent transceiver sub-assembly based on ring modulators, realized with Si photonic BiCMOS technology which allows monolithic integration of Si photonic integrated circuits and high-performance BiCMOS electronics. The transmitter consists of a ring modulator assisted Mach-Zehnder interferometer (RaMZI) and modulator driver electronics. The complex electro-optic modulation characteristics of the Si ring modulators (RMs) used for the transmitter are carefully investigated. The receiver includes the photonic components such as the Ge photodiodes and multimode interferometer (MMI) as well as the receiver front-end electronics such as transimpedance amplifier (TIA), variable gain amplifier (VGA) and output buffers. The performance evaluation of the novel monolithic all-silicon coherent transceiver sub-assembly based on ring modulators is carried out with a 28-Gbaud quadrature-phase-shift keying (QPSK) modulation signal.

(39) A 4-λ × 28-Gb/s/λ Silicon Ring-Resonator-based WDM Receiver with a Reconfigurable Temperature Controller
H.-K. Kim, J.-H. Lee, M. Kim, Y. Jo, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
IEEE Journal of Lightwave Technology 42(7), 2296 (2024)
DOI: 10.1109/JLT.2023.3337820
We present a 4-λ × 28-Gb/s/λ silicon ring-resonator-based hybrid-integrated WDM receiver along with the reconfigurable temperature controller. Each of four ring resonators is thermally controlled so that only the target wavelength can be delivered to an integrated photodetector and processed with a hybrid-integrated CMOS TIA. The controller automatically determines the heater voltage required for each ring resonator to receive any target wavelength and maintains this condition against any external temperature fluctuations. It is experimentally verified that the controller performs its task during the initial calibration process and against the thermal stress. In addition, using the controller, WDM channel reconfiguration is successfully demonstrated.

(40) Through the Looking-Glass: Sensitive Data Extraction by Optical Probing of Scan Chains
T. Kiyan, L. Renkes, M. Sass, A. Saavedra, N. Herfurth, E. Amini, J.-P. Seifert
IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES) 2024(4), 541 (2024)
DOI: 10.46586/tches.v2024.i4.541-568, (VE-HEP)
There is an imminent trade-off between an Integrated Circuit (IC)’s testability and its physical security. While Design for Test (DfT) techniques, such as scan chains make the circuit’s physical behavior at runtime observable and easy to control, these techniques form a lucrative class of attack vectors with the potential to compromise the entire security architecture of the Device under Test (DuT). Moreover, with the rapid development of more complex technologies, the need for integration of DfT techniques even intensifies due to the requirement for faster time-to-market of cutting-edge ICs. In this work, we demonstrate that sensitive data can be extracted from the registers once their locations on the chip are identified by exploiting DfT structures and optically probing them — in this case, scan chains, even after the access to test mode is restricted. Furthermore, we show that also an obfuscated scan chain architecture can be fully reconstructed by using tools and techniques encountered in the Failure Analysis (FA) domain.

(41) 200 mm Wafer Level Characterization at 2K of Si/SiGe Field-Effect Transistors
N.D. Komerički, P. Muster, F. Reichmann, T. Huckemann, D. Kaufmann, Y. Yamamoto, M. Lisker, W. Langheinrich, L.R. Schreiber, H. Bluhm, R. Quay
ECS Transactions 114(2), 133 (2024)
(QUASAR)
Si/SiGe has proven to be an excellent spin qubit platform, but industrial production of large-scale spin-qubit chips is missing. We use field effect transistors (FETs) to monitor and develop the quality of the fabrication process on 200 mm wafers at 2 K using a cryogenic wafer prober (CWP). This mass-characterization technique provides statistics on device performance. We observe variations in drain off current and gate threshold voltage of 213 FETs. These variations are related to bias voltage conditions during CWP cooldown, which differ from qubit chip cooldown. To address this, a new FET structure with an additional top gate is introduced, effectively suppressing unintentional charge accumulations. This eliminates drain off currents and improves homogeneity of FET characteristics at 2 K. Our results highlight significant impact of bias conditions during qubit chip cooldown, which, if not accounted for in the qubit chip design, can lead to incorrect conclusions when using CWP.

(42) Total-Ionizing-Dose Radiation Hardness of PJFETs Integrated in a 130nm SiGe BiCMOS Technology
F. Korndörfer, J. Schmidt, R. Sorge
Proc. iCampus Cottbus Conference (iCCC 2024), 199 (2024)
DOI: 10.5162/iCCC2024/P26

(43) Rational Design and Development of Room Temperature Hydrogen Sensors Compatible with CMOS Technology: A Necessary Step for the Coming Renewable Hydrogen Economy
J. Kosto, R. Tschammer, C. Morales, K. Henkel, C.A. Chavarin, I. Costina, M. Ratzke, Ch. Wenger, I.A. Fischer, J.I. Flege
Proc. iCampus Conference Cottbus (iCCC 2024), 182 (2024)
DOI: 10.5162/iCCC2024/P21

(44) Sustainable Use of a Smartphone and Regulatory Needs
M. Kögler, K. Paulick, J. Scheffran, M. Birkholz
Sustainable Development 32(6), 6182 (2024)
DOI: 10.1002/sd.2995
The significance of information and communication technologies (ICT) for implementing the Paris Climate Agreement is continuously increasing due to the growing energy consumption of the sector. Here we examine this question for the most widespread end user device, the smartphone, and extend the investigation to other aspects of sustainability than only climate mitigation. Emerging issues are identified for nine out of 17 UN Sustainable Development Goals (SDGs). The main discrepancies can be traced back to the oligopolistic market structure of smartphone operating systems, messenger services and social media apps. For individual users, technical means are outlined to make user behavior more sustainable by reducing energy consumption and data traffic. This applies to alternative operating systems, social media channels of the so-called Fediverse as well as free and open source software. Furthermore, societal conditions are emphasized to make the market for operating systems and apps more diverse so that a sustainable smartphone use can generally prevail.

(45) Technical and Societal Requirements for Handling of Personal Data on Wearable Devices
M. Kögler, J. Hooyberghs, M. Birkholz
Electronics Goes Green Conference (EGG 2024), 726 (2024)
(Bioelectronics)

(46) Post-CMP Cleaning of Silicon-Germanium Wafer Surfaces
A. Krüger, A.A. Adesunkanmi, R. Lukose, Y. Yamamoto, W.-C. Wen, M. Lisker
Proc. International Conference on Planarization/CMP Technology (ICPT 2024), 230 (2024)

(47) Development and Realization of Plasma Activated Low Temperature SiOx-SiOx Fusion Bonding based on a Collective Die-to-Wafer Bonding Process
P. Krüger, T. Voß, S. Schulze, M. Wietstruck
Proc. 10th IEEE Electronics System-Integration Technology Conference (ESTC 2024), (2024)
DOI: 10.1109/ESTC60143.2024.10712133

(48) A 112-Gb/s Hybrid-Integrated Si Photonic WDM Receiver with Ring-Resonator Filters
J-H. Lee, H.-K. Kim, M. Kim, Y. Jo, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2024), TuP14 (2024)
DOI: 10.1109/SiPhotonics60897.2024.10543480, (MPW_ePIC)

(49) Ultra-Fast Ge-on-Si Photodetectors
St. Lischke, D. Steckler, A. Peczek, J. Morgan, A. Beling, L. Zimmermann
Proc. Optical Fiber Communications Conference and Exposition (OFC 2024), Tu3D.1 (2024)
(PEARLS)

(50) Ultra-Fast Ge-on-Si Photodetectors
St. Lischke, D. Steckler, A. Peczek, J. Morgan, A. Beling, L. Zimmermann
Proc. Optical Fiber Communications Conference and Exposition (OFC 2024), Tu3D.1 (2024)
(CBQD)

(51) Ultra-Fast Ge-on-Si Photodetectors
St. Lischke, D. Steckler, A. Peczek, J. Morgan, A. Beling, L. Zimmermann
Proc. Optical Fiber Communications Conference and Exposition (OFC 2024), Tu3D.1 (2024)
(DFG EPIC-Sense 2)

(52) Ultra-Fast Ge-on-Si Photodetectors
St. Lischke, D. Steckler, A. Peczek, J. Morgan, A. Beling, L. Zimmermann
Proc. Optical Fiber Communications Conference and Exposition (OFC 2024), Tu3D.1 (2024)
(plaCMOS)

(53) Ultra-Fast Ge-on-Si Photodetectors
St. Lischke, D. Steckler, A. Peczek, J. Morgan, A. Beling, L. Zimmermann
Proc. Optical Fiber Communications Conference and Exposition (OFC 2024), Tu3D.1 (2024)
(DFG EPIDAC)

(54) Alternative Fabrication Method for Ge-Fin Photodiodes with 3-dB Bandwidths Exceeding 110 GHz
St. Lischke, J. Jose, D. Steckler, A. Kroh, A. Peczek, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2024), MBH6 (2024)
DOI: 10.1109/SiPhotonics60897.2024.10543707, (DFG EPIC-Sense 2)

(55) Alternative Fabrication Method for Ge-Fin Photodiodes with 3-dB Bandwidths Exceeding 110 GHz
St. Lischke, J. Jose, D. Steckler, A. Kroh, A. Peczek, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2024), MBH6 (2024)
DOI: 10.1109/SiPhotonics60897.2024.10543707, (CBQD)

(56) Graphene for Photonic Applications
M. Lukosius, R. Lukose, P.K. Dubey, A.I. Raju, M. Lisker, A. Mai, Ch. Wenger
Proc. 47th International ICT and Electronics Convention (MIPRO 2024), 1614 (2024)
DOI: 10.1109/MIPRO60963.2024.10569652, (2D-EPL)

(57) Towards a CMOS Compatible Refractive Index Sensor: Cointegration of TiN Nanohole Arrays and Ge Photodetectors in a 200 mm Wafer Silicon Technology
Ch. Mai, A. Peczek, A. Kroh, J. Jose, S. Reiter, Ch. Wenger, I.A. Fischer
Optics Express 32(17), 29099 (2024)
DOI: 10.1364/OE.530081, (iCampus)
In this work we present the monolithic integration of a TiN nanohole array and a Ge photodetector towards a CMOS compatible fabrication of a refractive index sensor in a 200 mm wafer silicon technology. We developed a technology process, which enables a fabrication with high yields of around 90 %. Ge photodetectors with a Ge layer thickness of 450 nm and an area of 1600 µm² (40 µm x 40 µm) show dark current densities of around 129 mA/cm² and responsivities of 0.114 A/W measured by top illumination (TE polarization; λ = 1310 nm; angle of incidence = 14 °) at a reverse bias of 1 V. Nanohole arrays were structured in a 150 nm thick TiN layer. They were integrated in the Back End of Line and placed spatially close to the Ge photodetectors. After the metallization, passivation and pad opening, the nanohole arrays were released with the help of an amorphous silicon stop layer. A significant impact of the TiN nanohole arrays on the optical behavior of the photodetector could be proven on wafer level. Photocurrent measurements by top illumination confirm a strong dependence of optical properties on the polarization of the incident light and the nanohole array design. We demonstrate very stable photocurrents on wafer level with a standard deviation of σ < 6 %.

(58) Electron Emission from Alignment-Controlled Multiple Stacks of SiGe Nanodots Embedded in Si Structures
K. Makihara, Y. Yamamoto, H. Yagi, L. Li, N. Taoka, B. Tillack, S. Miyazaki
Materials Science in Semiconductor Processing 174, 108227 (2024)
DOI: 10.1016/j.mssp.2024.108227
We fabricated a vertically aligned and staggered structure comprising 20–stacking layers of SiGe–nanodots (NDs) embedded in Si via reduced–pressure chemical vapor deposition and investigated their electron emission properties. The SiGe–NDs with a 35% Ge content were deposited using SiH4–GeH4, while Si spacers were deposited using SiH4 or SiH2Cl2 to control a 3D–alignment of staggered or dot–on–dot structure, respectively. Top Au electrodes with 5–nm–thick SiO2 and bottom Al contact were fabricated for electron emission measurements. After applying a bias of −3.8 V to the bottom Al–electrode with respect to the grounded top Au–electrode, electron emission was observed from the staggered SiGe–ND stack, which was slightly lower than that of the vertically–aligned NDs. In addition, we also observed a reduction in sample current with the formation of the staggered SiGe–ND stack. These results indicate that aligning SiGe–NDs in a staggered configuration suppresses leakage current and improves electron emission efficiency.

(59) Kinetic Monte Carlo Simulation Analysis of the Conductance Drift in Multilevel HfO2-based RRAM Devices
D. Maldonado, A. Baroni, S. Aldana, K.D.S. Reddy, S. Pechmann, Ch. Wenger, J.B. Roldán, E. Pérez
Nanoscale 16(40), 19021 (2024)
DOI: 10.1039/d4nr02975e, (KI-IoT)
This study investigates the retention and drift characteristics of valence change memory (VCM) devices through both experimental analysis and a 3D kinetic Monte Carlo (kMC) simulation approach. By simulating six distinct low-resistance states (LRS) over a 24-hour period at room temperature, we aim to assess the temporal stability and endurance of these devices. Our results demonstrate the feasibility of multi-level operation and reveal insights into conductive filament (CF) dynamics, including percolation path analysis and oxygen vacancy behavior. The cumulative distribution functions (CDFs) of read-out currents measured at different time intervals provide a comprehensive view of the performance of the devices across different LRS. These findings not only enhance the understanding of VCM device behavior but also inform strategies for improving retention and mitigating drift, thereby advancing the development of reliable nonvolatile resistive switching memory technologies.

(60) Influence of Stop and Gate Voltage on Resistive Switching of 1T1R HfO2-based Memristors, a Modeling and Variability Analysis
D. Maldonado, A. Cantudo, K.D.S. Reddy, S. Pechmann, M. Uhlmann, Ch. Wenger, J.B. Roldán, E. Pérez
Materials Science in Semiconductor Processing 182, 108726 (2024)
DOI: 10.1016/j.mssp.2024.108726, (KI-IoT)
Memristive devices, particularly resistive random access memory (RRAM) cells based on hafnium oxide (HfO₂) dielectrics, exhibit promising characteristics for a wide range of applications. In spite of their potential, issues related to intrinsic variability and the need for precise simulation tools and modeling methods remain a medium-term hurdle. This study addresses these challenges by investigating the resistive switching (RS) behavior of different 1T1R HfO₂-based memristors under various experimental conditions. Through a comprehensive experimental analysis, we extract RS parameters using different numerical techniques to understand the cycle-to-cycle (C2C) and device-to-device (D2D) variability. Additionally, we employ advanced simulation methodologies, including circuit breaker-based 3D simulation, to shed light on our experimental findings and provide a theoretical framework to disentangle the switching phenomena. Our results offer valuable insights into the RS mechanisms and variability, contributing to the improvement of robust parameter extraction methods, which are essential for the industrial application of memristive devices.

(61) Radiation Tolerance of SiGe BiCMOS Monolithic Silicon Pixel Detectors without Internal Gain Layer
M. Milanesio, L. Paolozzi, T. Moretti, R. Cardella, T. Kugathasan, F. Martinelli, A. Picardi, I. Semendyaev, S. Zambito, K. Nakamura, Y. Tabuko, M. Togawa, M. Elviretti, H. Rücker, F. Cadoux, R. Cardarelli, S. Débieux, Y. Favre, C.A. Fenoglio, D. Ferrere, S. Gonzalez-Sevilla, L. Iodice, R. Kotitsa, C. Magliocca, M. Nessi, A. Pizarro-Medina, J. Sabater Iglesias, J. Saidi, M. Vicente Barreto Pinto, G. Iacobucci
Journal of Instrumentation 19, P01014 (2024)
DOI: 10.1088/1748-0221/19/01/P01014
A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 × 1016 1 MeV neq/cm2. The ASIC contains a matrix of hexagonal pixels with 100 𝜇m pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 𝜇m thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. Laboratory tests conducted with a 90Sr source show that the detector works satisfactorily after irradiation. The signal-to-noise ratio is not seen to change up to fluence of 6×1014 neq/cm2. The signal time jitter was estimated as the ratio between the voltage noise and the signal slope at threshold. At -35◦C, sensor bias voltage of 200 V and frontend power consumption of 0.9 W/cm2, the time jitter of the most-probable signal amplitude was estimated to be 𝜎𝑡90Sr = 21 ps for proton fluence up to 6 × 1014 neq/cm2 and 57 ps at 1 × 1016 neq/cm2 . Increasing the sensor bias to 250 V and the analog voltage of the preamplifier from 1.8 to 2.0 V provides a time jitter of 40 ps at 1 × 1016 neq/cm2 .

(62) Time Resolution of a SiGe BiCMOS Monolithic Silicon Pixel Detector without Internal Gain Layer with a Femtosecond Laser
M. Milanesio, L. Paolozzi, T. Moretti, A. Latshaw, L. Bonacina, R. Cardella, T. Kugathasan, A. Picardi, M. Elviretti, H. Rücker, R. Cardarelli, L. Cecconi, C. A. Fenoglio, D. Ferrere, S. Gonzalez-Sevilla, L. Iodice, R. Kotitsa, C. Magliocca, M. Nessi, A. Pizarro-Medina, J. Sabater Iglesias, I. Semendyaev, J. Saidi, M. Vicente Barreto Pinto, S. Zambito, G. Iacobucci
Journal of Instrumentation 19, P04029 (2024)
DOI: 10.1088/1748-0221/19/04/P04029
The time resolution of the second monolithic silicon pixel prototype produced for the MONOLITH H2020 ERC Advanced project was studied using a femtosecond laser. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Silicon wafers with 50 µm thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. At the highest frontend power density tested of 2.7 W/cm2, the time resolution with the femtosecond laser pulses was found to be 45 ps for signals generated by 1200 electrons, and 3 ps in the case of 11k electrons, which corresponds approximately to 0.4 and 3.5 times the most probable value of the charge generated by a minimum-ionizing particle. The results were compared with testbeam data taken with the same prototype to evaluate the time jitter produced by the fluctuations of the charge collection.

(63) Low Disorder and High Mobility 2DEG in Si/SiGe Fabricated in 200 mm BiCMOS Pilotline
A. Mistroni, F. Reichmann, Y. Yamamoto, M.H. Zoellner, G. Capellini, L. Diebel, D. Bougeard, M. Lisker
ECS Transactions 114(2), 123 (2024)
DOI: 10.1149/11402.0123ecst, (QUASAR)
Spin qubits based on quantum dots built on Si/SiGe heterostructures are a leading contender for achieving large-scale quantum computation. The quality of quantum dots fabricated on these heterostructures is directly connected to the quality of the 2D electron gas (2DEG) confined in the strained Silicon quantum well. The properties of such 2DEG can be readily assessed using Hall bar-shaped field-effect transistors (HB-FETs) and magneto-transport measurements, enabling a faster feedback loop for heterostructure optimization process. In this work, we present our recent progress in enabling silicon-based quantum computation by demonstrating fundamental components for 2DEG characterization, all developed in IHP's 200 mm BiCMOS pilot line. We demonstrate fully functional HB-FETs on Si/SiGe heterostructures grown on 200 mm silicon wafers, showcasing state-of-the-art 2DEG with maximum carrier mobility exceeding 300,000 cm²/Vs and a percolation threshold of 6.3×1010 cm⁻². These results will help advance spin qubit research based on Si/SiGe heterostructures.

(64) Testbeam Results of Irradiated SiGe BiCMOS Monolithic Silicon Pixel Detector without Internal Gain Layer
T. Moretti, M. Milanesio, R. Cardella, T. Kugathasan, A. Picardi, I. Semendyaev, M. Elviretti, H. Rücker, K. Nakamura, Y. Takubo, M. Togawa, F. Cadoux, R. Cardarelli, L. Cecconi, S. Débieux, Y. Favre, C.A. Fenoglio, D. Ferrere, S. Gonzalez-Sevilla, L. Iodice, R. Kotitsa, C. Magliocca, M. Nessi, A. Pizarro-Medina, J. Sabater Iglesias, J. Saidi, M.V. Barreto Pinto, S. Zambito, L. Paolozzi, G. Iacobucci
Journal of Instrumentation 19, P07036 (2024)
DOI: 10.1088/1748-0221/19/07/P07036
Samples of the monolithic silicon pixel ASIC prototype produced in 2022 within the framework of the Horizon 2020 MONOLITH ERC Advanced project were irradiated with 70 MeV protons up to a fluence of 1 × 1016 neq/cm2 , and then tested using a beam of 120 GeV/c pions. The ASIC contains a matrix of 100 𝜇m pitch hexagonal pixels, readout out by low noise and very fast frontend electronics produced in a 130 nm SiGe BiCMOS technology process. The dependence on the proton fluence of the efficiency and the time resolution of this prototype was measured with the frontend electronics operated at a power density between 0.13 and 0.9 W/cm2. The testbeam data show that the detection efficiency of 99.8% measured at sensor bias voltage of 200 V before irradiation becomes 96.5% after a fluence of 1 × 1016 neq/cm2 . An increase of the sensor bias voltage to 300 V provides an efficiency to 99.5% at that proton fluence. The timing resolution of 20 ps measured before irradiation rises for a proton fluence of 1 × 1016 neq/cm2 to 48 and 44 ps at HV = 200 and 300 V, respectively.

(65) Local Laser-Induced Solid-Phase Recrystallization of Phosphorus-Implanted Si/SiGe Heterostructures for Contacts Below 4.2 K
M. Neul, I.V. Sprave, L.K. Diebel, L.G. Zinkl, F. Fuchs, Y. Yamamoto, C. Vedder, D. Bougeard, L.R. Schreiber
Physical Review Materials 8(4), 043801 (2024)
DOI: 10.1103/PhysRevMaterials.8.043801
Si/SiGe heterostructures are of high interest for high-mobility transistor and qubit applications, specifically for operations below 4.2K. In order to optimize parameters such as charge mobility, built-in strain, electrostatic disorder, charge noise, and valley splitting, these heterostructures require Ge concentration profiles close to monolayer precision. Ohmic contacts to undoped heterostructures are usually facilitated by a global annealing step activating implanted dopants, but compromising the carefully engineered layer stack due to atom diffusion and strain relaxation in the active device region. We demonstrate a local laser-based annealing process for recrystallization of ion-implanted contacts in SiGe, greatly reducing the thermal load on the active device area. To quickly adapt this process to the constantly evolving heterostructures, we deploy a calibration procedure based exclusively on optical inspection at room temperature. We measure the electron mobility and contact resistance of laser-annealed Hall bars at temperatures below 4.2K and obtain values similar or superior to that of a globally annealed reference sample. This highlights the usefulness of laser-based annealing to take full advantage of high-performance Si/SiGe heterostructures.

(66) Blooming and Pruning: Learning from Mistakes with Memristive Synapses
K. Nikiruy, E. Perez, A. Baroni, K.D.S. Reddy, S. Pechmann, Ch. Wenger, M. Ziegler
Scientific Reports 14, 7802 (2024)
DOI: 10.1038/s41598-024-57660-4, (KI-IoT)
Blooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.

(67) Strong Optical Coupling of Lattice Resonances in a Top-Down Fabricated Hybrid Metal−Dielectric Al/Si/Ge Metasurface
P. Oleynik, F. Berkmann, S. Reiter, J. Schlipf, M. Ratzke, Y. Yamamoto, I.A .Fischer
Nano Letters 24(10), 3142 (2024)
DOI: 10.1021/acs.nanolett.3c05050
Optical metasurfaces enable the manipulation of the light–matter interaction in ultrathin layers. Compared with their metal or dielectric counterparts, hybrid metasurfaces resulting from the combination of dielectric and metallic nanostructures can offer increased possibilities for interactions between modes present in the system. Here, we investigate the interaction between lattice resonances in a hybrid metal–dielectric metasurface obtained from a single-step nanofabrication process. Finite-difference time domain simulations show the avoided crossing of the modes appearing in the wavelength-dependent absorptance inside the Ge upon variations in a selected geometry parameter as evidence for strong optical coupling. We find good agreement between the measured and simulated absorptance and reflectance spectra. Our metasurface design can be easily incorporated into a top-down optoelectronic device fabrication process with possible applications ranging from on-chip spectroscopy to sensing.

(68) Optofluidic Biosensors with Si-based Photonic Integrated Circuit Technology
M. Paul, G. Lecci, C. Schumann, A. Mai, P. Steglich
Proc. iCampus Conference Cottbus (iCCC 2024), 112 (2024)
DOI: 10.5162/iCCC2024/8.3

(69) Repeatability of Automated Edge Coupling for Wafer Level Testing
A. Peczek, T. Minner, Q. Yuan, Ch. Mai, D. Rishavy, L. Zimmermann
Proc. 25th European Conference On Integrated Optics (ECIO 2024), in: Springer Proceedings in Physics, Springer, 402, 71 (2024)
DOI: 10.1007/978-3-031-63378-2_13
In foundries environment the optical characterization of Photonic In-tegrated Circuits (PICs) for process control and device performance verification requires a high throughput test solution. So far, wafer-level characterization of PICs has been limited to the grating couplers as the optical input/output interface. We propose an alternative optical probing technique suitable for automated on-wafer measurements based on edge coupling.
Here, we evaluate a solution based on FormFactor’s CM300-SiPh probe station and the Pharos Probe. A brief overview of the system is given and the repeatabil-ity of the coupling across the wafer is investigated.

(70) Forming and Resistive Switching of HfO2-Based RRAM Devices at Cryogenic Temperature
E. Perez-Bosch, A. Mistroni, R. Jia, K.D.S. Reddy, F. Reichmann, Ch. Wenger, E. Perez
IEEE Electron Device Letters 45(12), 2391 (2024)
DOI: 10.1109/LED.2024.3485873, (MIMEC)
Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4 K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4 K. The HfO2 -based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.

(71) Forming and Resistive Switching of HfO2-Based RRAM Devices at Cryogenic Temperature
E. Perez-Bosch, A. Mistroni, R. Jia, K.D.S. Reddy, F. Reichmann, Ch. Wenger, E. Perez
IEEE Electron Device Letters 45(12), 2391 (2024)
DOI: 10.1109/LED.2024.3485873, (KI-PRO)
Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4 K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4 K. The HfO2 -based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.

(72) Forming and Resistive Switching of HfO2-Based RRAM Devices at Cryogenic Temperature
E. Perez-Bosch, A. Mistroni, R. Jia, K.D.S. Reddy, F. Reichmann, Ch. Wenger, E. Perez
IEEE Electron Device Letters 45(12), 2391 (2024)
DOI: 10.1109/LED.2024.3485873, (KI-IoT)
Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4 K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4 K. The HfO2 -based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.

(73) Employing Optical Beam-Induced Current Measurement in Side-Channel Analysis
D. Petryk, I. Kabin, J. Bělohoubek, P. Fišer, J. Schmidt, M. Krstic, Z. Dyka
Proc. 36. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2024), 15 (2024)
(Total Resilience)

(74) Design and Phase Noise Measurements of an Ultrafast Dual-Modulus Prescaler in 130 nm SiGe:C BiCMOS
L. Polzin, M. van Delden, N. Pohl, H. Rücker, T. Musch
IEEE Transactions on Microwave Theory and Techniques 72(1), 525 (2024)
DOI: 10.1109/TMTT.2023.3329699
The design complexity of high-speed and power-efficient circuits increases to higher operation frequencies. Therefore, this manuscript gives an overview of how to design and optimize fully differential emitter-coupled logic (ECL) gates using two dual-modulus prescalers with switchable division ratios of 4 and 5. The first prescaler is optimized to the highest operation frequencies, up to 142 GHz and even 166 GHz for the division ratios of 5 and 4, respectively. Furthermore, another prescaler has been optimized for the widely used 80 GHz band, which has been heavily promoted by the automotive industry and has a high number of components in that domain. Both prescalers can be utilized in a fully programmable frequency divider with a wide division ratio range. As the measurement of the additive phase noise for frequency-converting devices with excellent noise performance is quite challenging, this is discussed theoretically and carried out practically. The measured jitter is between 500 as and 1.9 fs within integration limits of 100 Hz up to 1 MHz offset frequency.

(75) Optimization of Technology Processes for Enhanced CMOS-integrated 1T-1R RRAM Device Performance
K.D.S. Reddy, E. Perez/, A. Baroni, M.K. Mahadevaiah, St. Marschmeyer, M. Fraschke, M. Lisker, Ch. Wenger, A. Mai
The European Physics Journal B 97, 181 (2024)
DOI: 10.1140/epjb/s10051-024-00821-1, (KI-IoT)
Implementing artificial synapses that emulate the synaptic behaviour observed in the brain is one of the most critical requirement for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the Metal-Insulator-Metal (MIM) stack and the technology chosen for the selector device. To analyse these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.

(76) Optimization of Technology Processes for Enhanced CMOS-integrated 1T-1R RRAM Device Performance
K.D.S. Reddy, E. Perez/, A. Baroni, M.K. Mahadevaiah, St. Marschmeyer, M. Fraschke, M. Lisker, Ch. Wenger, A. Mai
The European Physics Journal B 97, 181 (2024)
DOI: 10.1140/epjb/s10051-024-00821-1, (FMD-QNC)
Implementing artificial synapses that emulate the synaptic behaviour observed in the brain is one of the most critical requirement for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the Metal-Insulator-Metal (MIM) stack and the technology chosen for the selector device. To analyse these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.

(77) Optimization of Technology Processes for Enhanced CMOS-integrated 1T-1R RRAM Device Performance
K.D.S. Reddy, E. Perez/, A. Baroni, M.K. Mahadevaiah, St. Marschmeyer, M. Fraschke, M. Lisker, Ch. Wenger, A. Mai
The European Physics Journal B 97, 181 (2024)
DOI: 10.1140/epjb/s10051-024-00821-1, (Neutronics)
Implementing artificial synapses that emulate the synaptic behaviour observed in the brain is one of the most critical requirement for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the Metal-Insulator-Metal (MIM) stack and the technology chosen for the selector device. To analyse these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.

(78) Advancing Si Spin Qubit Research: Process Integration of Hall Bar FETs on Si/SiGe in a 200mm BiCMOS Pilot Line
F. Reichmann, A. Mistroni, Y. Yamamoto, P. Kulse, St. Marschmeyer, D. Wolansky, O. Fursenko, M.H. Zoellner, G. Capellini, L. Diebel, D. Bougeard, M. Lisker
ECS Transactions 114(2), 109 (2024)
DOI: 10.1149/11402.0109ecst, (QUASAR)
Hall bar-shaped field-effect transistors (HB-FETs) are excellent devices for comprehensive, large-scale testing of Si/SiGe heterostructures in spin qubit applications. In this paper, we detail the process integration of high-quality HB-FETs onto Si/SiGe heterostructures within the IHP 200 mm BiCMOS pilot line. We compare various SiO2 deposition techniques to identify the most suitable process for a low thermal budget gate dielectric. The integration of HB-FETs on Si/SiGe heterostructures is discussed with a focus on the contact implant. We demonstrate the functionality of the devices at room temperature and at cryogenic temperatures. Magnetotransport measurements reveal a maximum electron mobility exceeding 300,000 cm²/Vs at 1.5 K.

(79) On-Chip Refractive Index Sensors Based on Plasmonic TiN Nanohole Arrays
S. Reiter, A. Sengül, Ch. Mai, D. Spirito, Ch. Wenger, I.A. Fischer
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2024), TuP10 (2024)
DOI: 10.1109/SiPhotonics60897.2024.10544048, (iCampus II)

(80) Open-Source Software, Fediverse and Custom ROMs as Tools for a Sustainable Internet
S. Rödiger, M. Kögler, M. Birkholz
Proc. Electronics Goes Green Conference (EGG 2024), 655 (2024)
DOI: 10.23919/EGG62010.2024.10631179, (Bioelectronics)

(81) Nanoheteroepitaxy of Ge and SiGe on Si: Role of Composition and Capping on Quantum Dot Photoluminescence
D. Ryzhak, J. Aberl, E. Prado-Navarrete, L. Vukušić, A.A. Corley-Wiciak, O. Skibitzki, M.H. Zoellner, M.A. Schubert, M. Virgilio, M. Brehm, G. Capellini, D. Spirito
Nanotechnology 35(50), 505001 (2024)
DOI: 10.1088/1361-6528/ad7f5f, (NHEQuanLEA)
We investigate the nanoheteroepitaxy of SiGe and Ge quantum dots (QDs) grown on nanotips substrates realized in Si(001) wafers. Due to the lattice strain compliance, enabled by the nanometric size of the tip and the limited dot/substrate interface area, which helps to reduce dot/substrate interdiffusion, the strain and SiGe composition in the QDs could be decoupled. This demonstrates a key advantage of the nanoheteroepitaxy over the Stranski-Krastanow growth mechanism. Nearly semi-spherical, defect-free, ∼100 nm wide SiGe QDs with different Ge contents were successfully grown on the nanotips with high selectivity and size uniformity. On the dots, thin dielectric capping layers were deposited, improving the optical properties by the passivation of surface states. Intense photoluminescence was measured from all samples investigated with emission energy, intensity, and spectral linewidth dependent on the SiGe composition of the QDs and the different capping layers. Radiative recombination occurs in the QDs, and its energy matches the results of band-structure calculations that consider strain compliance between the QD and the tip. The nanotips arrangement and the selective growth of QDs allow to studying the PL emission from only 3-4 QDs, demonstrating a bright emission and the possibility of selective addressing. These findings will support the design of optoelectronic devices based on CMOS-compatible emitters.

(82) Selective Epitaxy of Germanium on Silicon for the Fabrication of CMOS Compatible Short-Wavelength Infrared Photodetectors
D. Ryzhak, A.A. Corley-Wiciak, P. Steglich, Y. Yamamoto, J. Frigerio, R. Giani, A. De Iacovo, D. Spirito, G. Capellini
Materials Science in Semiconductor Processing 176, 108308 (2024)
DOI: 10.1016/j.mssp.2024.108308, (VISIR2)
Here we present the selective epitaxial growth of Ge on Si using reduced pressure chemical vapor deposition on SiO2/Si solid masks realized on 200 mm Si wafers, aiming at manufacturing integrated visible/short-wavelength infrared photodetectors. By a suitable choice of the reactants and of the process conditions, we demonstrated highly selective and pattern-independent growth of Ge microstructure featuring high crystalline quality. The Ge “patches” show a distinct faceting, with a flat top (001) facet and low energy facets such as e.g. {113} and {103} at their sidewalls, independently on their size. Interdiffusion of Si in to the Ge microcrystals is limited to an extension of ∼20 nm from the heterointerface. The Ge patches resulted to be plastically relaxed with threading dislocation density values better or on par than those observed in continuous two-dimensional Ge/Si epilayer in the low 107 cm−2 range. A residual tensile strain was observed for patches with size >10 μm, due to elastic thermal strain accumulation, as confirmed by μ-Raman spectroscopy and μ-photoluminescence characterization. Polarization-dependent Raman mapping highlights the strain distribution associated to the tridimensional shape. On this material, Ge photodiodes were fabricated and characterized, showing promising optoelectronic performances.

(83) Photoemission Study of Si and Ge Segregation on Al/Si0.8Ge0.2 Structures
T. Sakai, A. Ohta, N. Taoka, Y. Yamamoto, M.A. Schubert, S. Miyazaki, K. Makihara
ECS Transactions 114(2), 177 (2024)
We have demonstrated the formation of an ultrathin Si and Ge layer on an Al/Si0.8Ge0.2(111) structure caused by controlling the annealing condition. From the XPS characteristics, the annealing temperature, rather than the time, was found to be important in controlling the Si and Ge segregation. Also, by thermal annealing in N2 ambient, the segregated Ge on the Al/Si0.8Ge0.2 structure was found to be stable and resistant to oxidation due to the surface Al oxide layer and the segregated Si. We also found that Ge atoms were highly selectively segregated from the Al/Si0.8Ge0.2(111) structure below 500ºC. It was also found that Ge atoms could be selectively segregated from the Al/Si0.8Ge0.2(111) structure by rapid thermal annealing. The results will lead to the development of twodimensional. Ge crystals that are highly compatible with Si ultralarge-scale integration processing.

(84) A 79 GHz SiGe Doherty Power Amplifier Suitable for Next-Generation Automotive Radar
J. Schoepfel, T.T. Braun, J. Hellwig, H. Rücker, N. Pohl
IEEE Journal of Microwaves 4(4), 721 (2024)
DOI: 10.1109/JMW.2024.3419430
The number of environment-detecting sensors inside cars continuously increases, to enable failsafe autonomous driving. With more sensors, the probability of performance degrading interferences increases. A promising solution to the interferences is orthogonal frequency division multiplex (OFDM) radar. Due to the complex modulation scheme, the analog front end, especially the power amplifier in the transmitter, has to deal with a high peak-to-average power ratio. Therefore, conventional amplifiers have to be operated in power back-off to maintain linear operation at the drawback of reduced power-added efficiency. To mitigate this problem, a Doherty power amplifier for an automotive radar transceiver is proposed. In this work, we present a design methodology for an integrated Doherty amplifier for automotive radar applications, focussing on the theory of operation by analyzing transistor-level simulations. Small- and large signal simulations analyze the concept of load modulation for a Doherty amplifier in the automotive frequency band from 76--81 GHz. Using a fully differential transmission-line-based approach, we showcase the superior performance of an automotive Doherty amplifier over an conventional state-of-the-art reference amplifier. In measurements, the proposed Doherty amplifier achieves a saturated output power of 17.2 dBm with a peak power-added efficiency of 11.6%. When operating in 6 dB back-off, the PAE still amounts to 6.1%. Thereby we propose to improve conventional automotive power amplifiers by incorporating them into a Doherty amplifier.

(85) A Collective Die to Wafer Bonding Approach Based on Surface-Activated Aluminum-Aluminum Thermocompression Bonding
S. Schulze, T. Voß, P. Krüger, M. Wietstruck
IEEE Transactions on Components, Packaging and Manufacturing Technology 14(3), 519 (2024)
DOI: 10.1109/TCPMT.2024.3363236, (GreenICT)
This work presents a collective die to wafer (D2W) bonding concept based on surface-activated aluminum–aluminum (Al–Al) thermocompression bonding, which involves the fabrication of a reusable silicon carrier wafer onto which the dies are placed without additional adhesives. Compared to other methods, the absence of adhesives allows the subsequent processing under ultrahigh vacuum, which is beneficial for low-temperature Al–Al bonding. The Al–Al bonding is performed in an EVG ComBond system, where an argon plasma is used to remove the native oxide. The thermocompression bonding is carried out for 1 h at a temperature of 300 °C with a pressure between 52 and 60 MPa. This article shows an Al–Al collective D2W bonding process with high yield >90%, excellent bond strength >90 MPa, and contact resistances in the milliohms range.

(86) A Collective Die to Wafer Bonding Approach Based on Surface-Activated Aluminum-Aluminum Thermocompression Bonding
S. Schulze, T. Voß, P. Krüger, M. Wietstruck
IEEE Transactions on Components, Packaging and Manufacturing Technology 14(3), 519 (2024)
DOI: 10.1109/TCPMT.2024.3363236, (ESSENCE-6GM)
This work presents a collective die to wafer (D2W) bonding concept based on surface-activated aluminum–aluminum (Al–Al) thermocompression bonding, which involves the fabrication of a reusable silicon carrier wafer onto which the dies are placed without additional adhesives. Compared to other methods, the absence of adhesives allows the subsequent processing under ultrahigh vacuum, which is beneficial for low-temperature Al–Al bonding. The Al–Al bonding is performed in an EVG ComBond system, where an argon plasma is used to remove the native oxide. The thermocompression bonding is carried out for 1 h at a temperature of 300 °C with a pressure between 52 and 60 MPa. This article shows an Al–Al collective D2W bonding process with high yield >90%, excellent bond strength >90 MPa, and contact resistances in the milliohms range.

(87) Determination of the Indirect Bandgap of Lattice-Matched SiGeSn on Ge
D. Schwarz, E. Kasper, F. Bärwolf, I. Costina, M. Oehme
Materials Science in Semiconductor Processing 180, 108565 (2024)
DOI: 10.1016/j.mssp.2024.108565, (SiGeSn NanoFETs)
The first experimental results for the indirect bandgap of SiGeSn, lattice-matched on Ge are reported. The necessary condition for lattice-matching on Ge is a constant ratio of Si/Sn = 3.67. Thus, the investigated composition range is cSn={5.0,7.5,10.0}% and precisely investigated using secondary ion mass spectroscopy. The bandgap determination is based on the extraction of the built-in voltage of a SiGeSn pn++ junction utilizing the so-called capacitance-voltage intercept method. Detailed calculations of the band diagram of the pn++ junction to be investigated, including first level approximations for the effective density of states in the valence and conduction band were performed. The results show that the composition of the alloy strongly influences its bandgap and is ΕLg,SiGeSn={0.588,0.704,0.413}eV, respectively.

(88) Self-Consistent Determination of Interface and Bulk Parameters of Oxide/Si/SiGe/Si Layer Stacks by Means of Simultaneous Measurement of Gate Current and High Frequency Gate Capacitance in Non-Steady State Non-Equilibrium
R. Sorge, W.-C. Wen, M. Lisker, N. Inomata, Y. Yamamoto
Proc. iCampus Cottbus Conference (iCCC 2024), 207 (2024)
DOI: 10.5162/iCCC2024/P28, (SiGeQuant)

(89) Germanium Photodiodes with 3-dB Bandwidths >110 GHz and L-Band Responsivity of >0.7 A/W
D. Steckler, St. Lischke, A. Kroh, A. Peczek, G. Georgieva, L. Zimmermann
IEEE Photonics Technology Letters 36(12), 775 (2024)
DOI: 10.1109/LPT.2024.3398359, (DFG ULTRA 2)
We present germanium p-i-n photodiodes with opto-electrical 3-dB bandwidths >110 GHz while exhibiting high internal responsivity >0.7 AW-1 at 1620 nm wavelength. Compared to our previous work, this is an improvement of >35 % in internal responsivity without sacrificing the photo detectors bandwidths. This was achieved by the introduction of a local reduction of the silicon waveguide thickness right below the germanium body, which improves optical coupling (from the silicon waveguide into the germanium region) and confinement. In this work we study three photodiode device variants in which germanium is laterally sandwiched between complementary in-situ doped Si regions. This approach enables the side-by side realization of germanium p-i-n photodiodes with different widths, featuring different combinations of OE bandwidths and responsivities. We further investigate on the optical-power handling capabilities of these photodiodes by means of responsivity and bandwidth.

(90) Germanium Photodiodes with 3-dB Bandwidths >110 GHz and L-Band Responsivity of >0.7 A/W
D. Steckler, St. Lischke, A. Kroh, A. Peczek, G. Georgieva, L. Zimmermann
IEEE Photonics Technology Letters 36(12), 775 (2024)
DOI: 10.1109/LPT.2024.3398359, (DFG EPIC-Sense 2)
We present germanium p-i-n photodiodes with opto-electrical 3-dB bandwidths >110 GHz while exhibiting high internal responsivity >0.7 AW-1 at 1620 nm wavelength. Compared to our previous work, this is an improvement of >35 % in internal responsivity without sacrificing the photo detectors bandwidths. This was achieved by the introduction of a local reduction of the silicon waveguide thickness right below the germanium body, which improves optical coupling (from the silicon waveguide into the germanium region) and confinement. In this work we study three photodiode device variants in which germanium is laterally sandwiched between complementary in-situ doped Si regions. This approach enables the side-by side realization of germanium p-i-n photodiodes with different widths, featuring different combinations of OE bandwidths and responsivities. We further investigate on the optical-power handling capabilities of these photodiodes by means of responsivity and bandwidth.

(91) Monolithic Integration of 80-GHz Ge Photodetectors and 100-GHz Ge Electro-Absorption Modulators in a Photonic BiCMOS Technology
D. Steckler, St. Lischke, A. Peczek, A. Kroh, J. Beyer, L. Zimmermann
IEEE Transactions on Electron Devices 71(5), 3417 (2024)
DOI: 10.1109/TED.2024.3370128, (DFG EPIC-Sense 2)
We demonstrate a photonic BiCMOS technology featuring waveguide (WG)-coupled germanium electro-absorption modulators (EAMs) and photodetectors with respective 3-dB bandwidths of 100 and 80 GHz, monolithically integrated with high-performance SiGe-heterojunction bipolar transistors (HBTs) and 0.25- μ m CMOS. The EAMs feature dynamic extinction ratios of 2.3 dB at a symbol rate of 112 GBaud at 1.8 V pp and λ = 1590 nm. We demonstrate that there is no degradation of the baseline technology “SG25H5EPIC” in terms of electronic device yield or performance.

(92) On the Dynamic and Static Extinction Ratio of Germanium Electro-Absorption Modulators
D. Steckler, St. Lischke, A. Peczek, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2024), WP2 (2024)
DOI: 10.1109/SiPhotonics60897.2024.10543654, (DFG EPIC-Sense 2)

(93) Ge-fin Photodiodes with 3-dB Bandwidths Well Beyond 110 GHz for O-Band Receiver Subsystems
D. Steckler, St. Lischke, A. Peczek, L. Zimmermann
Proc. 25th European Conference on Integrated Optics (ECIO 2024), in: Springer Proceedings in Physics, Springer, 402, 58 (2024)
DOI: 10.1007/978-3-031-63378-2_11, (CBQD)

(94) Ge-fin Photodiodes with 3-dB Bandwidths Well Beyond 110 GHz for O-Band Receiver Subsystems
D. Steckler, St. Lischke, A. Peczek, L. Zimmermann
Proc. 25th European Conference on Integrated Optics (ECIO 2024), in: Springer Proceedings in Physics, Springer, 402, 58 (2024)
DOI: 10.1007/978-3-031-63378-2_11, (DFG ULTRA 2)

(95) Ge-fin Photodiodes with 3-dB Bandwidths Well Beyond 110 GHz for O-Band Receiver Subsystems
D. Steckler, St. Lischke, A. Peczek, L. Zimmermann
Proc. 25th European Conference on Integrated Optics (ECIO 2024), in: Springer Proceedings in Physics, Springer, 402, 58 (2024)
DOI: 10.1007/978-3-031-63378-2_11, (DFG EPIC-Sense 2)

(96) Light Propagation in Anisotropic Materials and Electro-Optical Effects: Tutorial on the Use of Eigenvalue Problems, Tensors, and Symmetries
P. Steglich, A. Kehrein
Journal of the Optical Society of America B: Optical Physics 41(9), 2191 (2024)
DOI: 10.1364/JOSAB.524213
The properties of anisotropic materials are used in many optical components such as waveplates or polarizing beamsplitters. In particular, anisotropic materials that possess electro-optical properties allow the realization of actively controllable optical components like optical switches, phase shifters, or modulators. Hence, understanding and computation of light propagation in anisotropic materials with electro-optical effects are crucial in optical science and technology. On the one hand this tutorial stresses the use of eigenvalue problems to explain qualitatively and to compute quantitatively important properties such as polarization. On the other hand it discusses the mathematical model of both electro-optical effects, namely, the Pockels and the DC Kerr effect. This tutorial describes the basic concepts in a consistent tensor language, shows how the tensors are conveniently summarized in matrices, and points out that these matrices do not transform like tensors. The tensor approach clarifies how symmetry arguments affect tensor components. Further, this paper derives the more accurate nonlinear relationship between the refractive index and the externally applied electric field.

(97) Structural Changes in Ge1-xSnx and Si1-x-yGeySnx Thin Films on SOI Substrates Treated by Pulse Laser Annealing
O. Steuer, D. Schwarz, M. Oehme, F. Bärwolf, Y. Cheng, F. Ganss, R. Hübner, R. Heller, S. Zhou, M. Helm, G. Cuniberti, Y.M. Georgiev, S. Prucnal
Journal of Applied Physics 136(5), 055303 (2024)
DOI: 10.1063/5.0218703, (SiGeSn NanoFETs)
Ge1−xSnx and Si1−x−yGeySnx alloys are promising materials for future opto- and nanoelectronics applications. These alloys enable effective bandgap engineering, broad adjustability of their lattice parameter, exhibit much higher carrier mobility than pure Si, and are compatible with the complementary metal-oxide-semiconductor technology. Unfortunately, the equilibrium solid solubility of Sn in Si1−xGex is less than 1% and the pseudomorphic growth of Si1−x−yGeySnx on Ge or Si can cause in-plane compressive strain in the grown layer, degrading the superior properties of these alloys. Therefore, post-growth strain engineering by ultrafast non-equilibrium thermal treatments like pulse laser annealing (PLA) is needed to improve the layer quality. In this article, Ge0.94Sn0.06 and Si0.14Ge0.8Sn0.06 thin films grown on silicon-on-insulator substrates by molecular beam epitaxy were post-growth thermally treated by PLA. The material is analyzed before and after the thermal treatments by transmission electron microscopy, x-ray diffraction (XRD), Rutherford backscattering spectrometry, secondary ion mass spectrometry, and Hall-effect measurements. It is shown that after annealing, the material is single-crystalline with improved crystallinity than the as-grown layer. This is reflected in a significantly increased XRD reflection intensity, well-ordered atomic pillars, and increased active carrier concentrations up to 4 × 1019 cm−3.

(98) Chemical Vapor Deposition of Hexagonal Boron Nitride on Germanium from Borazine
K.A. Su, S. Li, W.-C. Wen, Y. Yamamoto, M.S. Arnold
Chemistry of Materials 14(35), 25378 (2024)
DOI: 10.1039/d4ra03704a
The growth of hexagonal boron nitride (hBN) directly onto semiconducting substrates, like Ge and Ge on Si, promises to advance the integration of hBN into microelectronics. However, a detailed understanding of the growth and characteristics of hBN islands and monolayers on these substrates is lacking. Here, we present the growth of hBN on Ge and Ge epilayers on Si via high-vacuum chemical vapor deposition from borazine and study the effects of Ge sublimation, surface orientation, and vicinality on the shape and alignment of hBN islands. We find that suppressing Ge sublimation is essential for growing high quality hBN and that the Ge surface orientation and vicinality strongly affect hBN alignment. Interestingly, 95% of hBN islands are unidirectionally aligned on Ge(111), which may be a path toward metal- and transfer-free, single-crystalline hBN. Finally, we extend the growth time and borazine partial pressure to grow monolayer hBN on Ge and Ge epilayers on Si. These findings provide new insights into the growth of high-quality hBN on semiconducting substrates.

(99) BiCMOS BEOL Coupon Fabrication and Micro Transfer Printing for Heterogeneous Integration Applications
S. Tolunay Wipf, St. Marschmeyer, M. Drost, K. Anand, M. Wietstruck
Proc. 10th IEEE Electronics System-Integration Technology Conference (ESTC 2024), (2024)
DOI: 10.1109/ESTC60143.2024.10712098

(100) Robust Systems and Technology Dissemination for Space Applications: From Cross-Layer Analytics to an Open-Access Reliability Framework
F. Vargas, M. Krstic, M. Andjelkovic, S. Andreev, A. Balashov, M. Ulbricht, J.-C. Chen
Proc. International Conference on Radiation Applications (RAP 2024), abstr. book 108 (2024)
(COCHISA)

(101) Design, Fabrication, and Characterization of Integrated Optical Through-Silicon Waveguides for 3D Photonic Interconnections
F. Villasmunta, P. Steglich, C. Villringer, S. Schrader, H. Schenk, A. Mai, M. Regehly
Proc. 24th SPIE Optical Interconnects (OPTO 2024), 12892, 128920I (2024)
DOI: 10.1117/12.3003146

(102) Effect of the Temperature on the Performance and Dynamic Behaviour of HfO2-based RRAM Devices
G. Vinuesa, H. Garcia, S. Dueñas, H. Castan, I. Iñiguez-de-la-Torre, T. Gonzalez, K.D.S. Reddy, M. Uhlmann, Ch. Wenger, E. Perez
Proc. 245th ECS Meeting: Advancing Solid State & Electrochemical Science & Technology (ECS Meeting 2024), abstr. book 1297 (2024)
DOI: 10.1149/MA2024-01211297mtgabs, (KI-IoT)

(103) Characterization, Analysis, and Modeling of Long-Term RF Reliability and Degradation of SiGe HBTs for High Power Density Applications
C. Weimer, G.G. Fischer, M. Schröter
IEEE Transactions on Device and Materials Reliability 24(1), 20 (2024)
DOI: 10.1109/TDMR.2023.3343503, (SIGEREL)
This paper aims at determining RF operating limits of SiGe HBTs. Long-term stress tests consisting of RF large-signal stress and periodic measurements of small-signal parameters are performed. Reliable dynamic large-signal transistor operation is demonstrated beyond conventional static safe operating limits. In addition, RF operating limits are identified and degradation of SiGe HBTs accelerated by extreme RF stress is systematically characterized, analyzed and modeled. RF-stress-caused degradation is shown to significantly affect the collector current and demonstrated to be different from electrothermal breakdown caused by DC stress. A modeling approach for estimating SiGe HBT degradation under RF large-signal operating conditions is proposed and shown to agree very well with experimental data.

(104) Lateral Mn5Ge3 Spin Valve in Contact with a High Mobility Ge Two-Dimensional Hole Gas
D. Weisshaupt, C. Sürgers, D. Bloos, H.S. Funk, M. Oehme, G. Fischer, M.A. Schubert, Ch. Wenger, J. van Slageren, I.A. Fischer, J. Schulze
Semiconductor Science and Technology 39(12), 125004 (2024)
DOI: 10.1088/1361-6641/ad8d06
Ge two-dimensional hole gases in a strained modulation-doped quantum-wells represent a promising material platform for future spintronic applications due to their excellent spin transport properties and the theoretical possibility of efficient spin manipulation. Due to the continuous development of epitaxial growth recipes extreme high hole mobilities and low effective masses can be achieved, promising an efficient spin transport. Furthermore, the Ge two-dimensional hole gas (2DHG) can be integrated in the well-established industrial complementary metal-oxide-semiconductor (CMOS) devices technology. However, efficient electrical spin injection into a Ge 2DHG - an essential prerequisite for the realization of spintronic devices - has not yet been demonstrated. In this work, we report the fabrication and low-temperature magnetoresistance measurements of a laterally structured Mn5Ge3/Ge 2DHG/ Mn5Ge3 device. The ferromagnetic Mn5Ge3 contacts are grown directly into the Ge quantum well by means of an interdiffusion process with a spacing of approximately 130 nm. We observe a magnetoresistance signal for temperatures below 13 K, indicating successful spin injection. The results represent an essential step forward toward the realization of CMOS compatible spintronic devices based on a 2DHG.

(105) Differential-Mode Power Detection for Built-In Self-Test of SiGe Automotive Radar Transceiver Front Ends
Y. Wenger, H.J. Ng, F. Korndörfer, B. Meinerzhagen, V. Issakov
IEEE Transactions on Microwave Theory and Techniques 72(8), 4717 (2024)
DOI: 10.1109/TMTT.2024.3354124
Recently, the feasibility of differential-mode power detection for built-in self-test (BIST) in millimeter-wave SiGe transceiver front ends has been demonstrated. In this work, a system analysis of typical BIST scenarios is performed. Specifications for the input power levels as well as the accuracy of power detectors are derived from this analysis. A need for at least two different differential detector architectures is identified. Two detectors are derived from the differential power measurement concept, analyzed, and implemented in the 76–81-GHz automotive radar frequency band. They feature a low power consumption of 500 μ W and, to the authors’ best knowledge, the lowest published circuit areas of approximately 0.005 mm2 while still being input matched to the differential 100 Ω system impedance. Both these characteristics are essential to keep the overhead of the BIST minimal. With dynamic ranges of 30 dB and up to 46 dB for the two different architectures, the differential power detector concept can achieve sufficient performance for BIST applications. The robustness against process and temperature effects as well as noise is analyzed and reported for both detectors.

(106) Photoluminescence of Three-Dimensional Self-Aligned SiGe Nanodots
W.-C. Wen, D. Wang, K. Yamamoto, M.A. Schubert, R. Sorge, B. Tillack, Y. Yamamoto
Proc. 56th International Conference on Solid State Device and Materials (SSDM 2024), (2024)

(107) Fabrication and Implementation of BiCMOS BEOL Silicon Interposer Technologies with Integrated Metal Reflectors for Sub-THz Leaky-Wave Antennas
M. Wietstruck, P. Krüger, T. Voß, T. Mausolf, M.F. Bashir, A. Bhutani
Proc. 10th IEEE Electronics System-Integration Technology Conference (ESTC 2024), (2024)
DOI: 10.1109/ESTC60143.2024.10712047, (ESSENCE-6GM)

(108) High Frequency Properties of an Integrated PJFET for Sensor Applications
Ch. Wipf, R. Sorge
Proc. iCampus Cottbus Conference (iCCC 2024), 216 (2024)
DOI: 10.5162/iCCC2024/P30

(109) Thin and Locally Dislocation-Free SiGe Virtual Substrate Fabrication by Lateral Selective Growth
Y. Yamamoto, W.-C. Wen, M.A. Schubert, A.A. Corley-Wiciak, S. Sugawa, Y. Ito, R. Yokogawa, H. Han, R. Loo, A. Ogura, B. Tillack
Japanese Journal of Applied Physics 63(2), 02SP53 (2024)
DOI: 10.35848/1347-4065/ad189d
Locally dislocation-free SiGe-on-insulator (SGOI) is fabricated by chemical vapor deposition. Lateral selective SiGe growth of ~30%, ~45% and ~55% is performed around ~1 µm square Si(001) pillar located under the center of a 6.3 µm square SiO2 on Si-on-insulator substrate which is formed by H2-HCl vapor phase etching. The selective SiGe is deposited by H2-SiH2Cl2-GeH4-HCl. In the deposited SiGe layer, tensile strain is observed by top-view. The degree of strain is slightly increased at the corner of the SiGe. The tensile strain is caused by the partial compressive strain of SiGe in lateral direction and thermal expansion difference between Si and SiGe. Slightly higher Ge incorporation is observed in higher tensile strain region. At the peaks formed between the facets of growth front, Ge incorporation is reduced. These phenomena are pronounced for SiGe with higher Ge contents. Dislocation-free SGOI is formed along <010> from the Si pillar by lateral aspect-ratio-trapping.

(110) Piezo Electric Properties of Epitaxial SiGe
Y. Yamamoto, W.-C. Wen, N. Inomata A.A. Corley-Wiciak,, D. Ryzhak, C. Corley-Wiciack, Z. Zhizianb, R. Sorge, B. Tillack, T. Ono
ECS Transactions 114(2), 353 (2024)
DOI: 10.1149/11402.0353ecst
Piezo resistivity of B- and P-doped epitaxial Si1-xGex (x=10-30%) is investigated to assess its potential of application for thin film strain sensors. The gauge factor (GF) is calculated based on resistivity change by the externally induced compressive uniaxial strain along the current flow direction. In the case of the B-doped SiGe, the resistivity decreases by induced strain which may be related to hole mobility enhancement, while no influence for the P-doped SiGe is detected. A significant increase in the GF is observed by lowering B concentration. At the same B concentration, slightly higher GF is observed for higher Ge content. Moreover, the GF is slightly improved by lowering the SiGe growth temperature. The slight improvement may be related to improved crystallinity. These results suggest that the low-doped p-type SiGe deposited at low temperature has reasonable GF and can potentially be applied in strain sensors.

(111) Evaluation of Thermal Transport Characteristics of Three-Dimensional Self-Ordered Multilayered Silicon-Germanium Nanodots
R. Yokogawa, Y. Maeda, Y. Ito, Y. Yamashita, W.-C. Wen, Y. Yamamoto, A. Ogura
Proc. 245th ECS Meeting: Dielectric Science and Materials (ECS Meeting 2024), abstr. book 1370 (2024)
DOI: 10.1149/MA2024-01231370mtgabs

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