Publications 2023
Script list Publications
(1) Chemical Vapor Deposition Growth of Graphene on 200 mm Ge(110)/Si Wafers and Ab Initio Analysis of Differences in Growth Mechanisms on Ge(110) and Ge(001)
F. Akhtar, J. Dabrowski, R. Lukose, Ch. Wenger, M.Lukosius
ACS Applied Materials & Interfaces 15(30), 36966 (2023)
DOI: 10.1021/acsami.3c05860, (2D-EPL)
For the fabrication of modern graphene devices, uniform growth of high-quality monolayer graphene on wafer scale is important. This work reports on the growth of large-scale graphene on semiconducting 8 inch Ge(110)/Si wafers by chemical vapor deposition and a DFT analysis of the growth process. Good graphene quality is indicated by the small FWHM (32 cm–1) of the Raman 2D band, low intensity ratio of the Raman D and G bands (0.06), and homogeneous SEM images and is confirmed by Hall measurements: high mobility (2700 cm2/Vs) and low sheet resistance (800 Ω/sq). In contrast to Ge(001), Ge(110) does not undergo faceting during the growth. We argue that Ge(001) roughens as a result of vacancy accumulation at pinned steps, easy motion of bonded graphene edges across (107) facets, and low energy cost to expand Ge area by surface vicinals, but on Ge(110), these mechanisms do not work due to different surface geometries and complex reconstruction.
(2) Towards Heterogeneous Integration of InP on Si via Micro Transfer Printing by Direct Adhesion
K. Anand, P. Steglich, J. Kreißl, L. Zimmermann, A. Mai
Proc. 10. MikroSystemTechnik Kongress (MST 2023), 430 (2023)
(PEARLS)
(3) Lateral Selective SiGe Growth for Local Dislocation-Free SiGe-on-Insulator Virtual Substrate Fabrication
K. Anand, M.A. Schubert, D. Spirito, A.A. Corley-Wiciak, C. Corley-Wiciak, W.M. Klesse, A. Mai, B. Tillack, Y. Yamamoto
ECS Journal of Solid State Science and Technology 12(2), 024003 (2023)
DOI: 10.1149/2162-8777/acb739
Dislocation-free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around ~1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850°C from side of SiO2 / Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ~40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ~0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ~1.4% along <010> direction, which is higher compared to that along <110> direction, is observed. The tensile strain is induced from both [110] and [-110] directions. Threading dislocations in the SiGe are located only ~400 nm from Si pillar and stacking faults are running towards <110> directions, resulting in wide dislocation-free area formation in SiGe along <010> due to horizontal aspect ratio trapping.
(4) A D-Band to J-Band Low-Noise Amplifier with High Gain-Bandwidth Product in an Advanced 130 nm SiGe BiCMOS Technology
M. Andree, J. Grzyb, B. Heinemann, U. Pfeiffer
Proc. IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2023), 137 (2023)
DOI: 10.1109/RFIC54547.2023.10186116
(5) Messverfahren zur Kontrolle tiefer Siliziumstrukturen für die 3D-Chip-Integration
J. Bauer, F. Villasmunta, F. Heinrich, C. Villinger, J. Reck, S. Peters, A. Treffer, Ch. Kuhnt, St. Marschmeyer, O. Fursenko, P. Steglich, A. Mai, S. Schrader, M. Regehly
Proc. 124. Jahrestagung der Deutschen Gesellschaft für angewandte Optik e.V. (DGaO 2023), B35 (2023)
(6) 200–330-GHz Substrate-Integrated Waveguide in BEOL of a SiGe BiCMOS Process
A. Bhutani, M. Kaynak, E. Bekker, T. Zwick
IEEE Microwave and Wireless Technology Letters (MWTL)
DOI: 10.1109/LMWT.2023.3283304
This letter shows the first 200–330-GHz substrate-integrated waveguide (SIW) to a grounded coplanar waveguide (GCPW) transition realized in backend-of-line (BEOL) of a SiGe BiCMOS process. The transition uses two rectangular slots and a GCPW stub, which convert a quasi-TE10 to quasi-TEM mode with the highest operating frequency of up to 330 GHz, largest operation bandwidth of 49%, and smallest transition length of 99μm for a silicon process-based SIW transition demonstrated to date. A back-to-back configuration with ground–signal–ground (GSG) pads on either end enables probe-based S-parameter measurement. The influence of the GSG pads is de-embedded by measuring a 50- Ω GCPW connected by a pair of the GSG pads. A comparison of the measured and de-embedded S-parameters with the electromagnetic simulation results show that the SIW–GCPW transition operates from 200 to 330 GHz (49% bandwidth) with an average insertion loss of ≈1.2 dB per transition.
(7) Implantable Microelectronics
M. Birkholz
Bioelectronics: Materials, Technologies, and Emerging Applications, 1st Edition, Editors: A. Kumar, R.K. Gupta, Chapter 21. Implantable Microelectronics, CRC Press 341 (2023)
DOI: 10.1201/9781003263265-21, (Bioelectronics)
(8) Sustainable Design of Online Biosensors
M. Birkholz, M. Kögler
Proc. 4th European Biosensor Symposium (EBS 2023), 88 (2023)
(Bioelectronics)
(9) A 100 GBd PAM-4 Combiner and Driver in SiGe BiCMOS
C. Bohn, M. Kaynak, T. Zwick, A.C. Ulusoy
IEEE Microwave and Wireless Technology Letters (MWTL) 33(9), 1337 (2023)
DOI: 10.1109/LMWT.2023.3293040
In this letter, we present an analog PAM-4 combiner and driver circuit based on a current steering output stage designed in a 130 nm SiGe BiCMOS technology. The circuit features an on-chip active balun with more than 67 GHz bandwidth. The output stage supports an adjustable PAM-4 level spacing. It consumes 315 mW and delivers 2 Vpp,diff in a 100 Ω load. Operation of up to 100 GBd has been verified by measured eye diagrams.
(10) Fabrication of Gate Electrodes for Scalable Quantum Computing using CMOS Industry Compatible E-Beam Lithography and Numerical Simulation of the Resulting Quantum Device
V. Brackmann, M. Neul, M. Friedrich, W. Langheinrich, M. Simon, S. Pregl, A. Demmler, N. Hanisch, M. Lederer, K. Zimmermann, J. Klos, F. Reichmann, Y. Yamamoto, M. Wislicenus, C. Dahl, L. Schreiber, H. Bluhm, B. Lilienthal-Uhlig
Proc. 38th Mask and Lithography Conference (ELMC 2023), 12802, 128020F (2023)
DOI: 10.1117/12.2675943, (QUASAR)
(11) Progress on SiGeSn Light Emitters and Detectors on Si
D. Buca, T. Liu, O. Concepción, M. El Kurdi, Y. Yamamoto, G. Capellini, G Isella, D. Grützmacher
Proc. 13th International WorkShop on New Group IV Semiconductor Nanoelectronics (2023), abstr. book 9 (2023)
(12) In-Orbit VNIR Sensor Quality Validation
J. Buschek, A. Eckardt, K. Manthey, K. Sengebusch, O. Schrey, D. Piechaczek, G. Kahmen
Proc. Sensors, Systems, and Next-Generation Satellites XXVII, 12729, 1272913 (2023)
DOI: 10.1117/12.2680166
(13) Characterization and Optimization of the Heat Dissipation Capability of a Chip-on-Board Package using Finite Element Methods
Z. Cao, M. Stocchi, M. Wietstruck, T. Mausolf, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 13(3), 346 (2023)
DOI: 10.1109/TCPMT.2023.3259199, (FLEXCOM)
The present study endeavors to investigate the thermal dissipation capability of a chip-on-board package by means of a comprehensive experimental and numerical analysis. For this purpose, a BiCMOS chip is designed and fabricated in conjunction with three different printed circuit board (PCB) configurations, including a single-sided board, a thermal via board, and a copper frame board. Transient thermal measurements are carried out on all three packages, and the results are subsequently transformed into cumulative structure functions. Then the finite element models are established for each package configuration, and their validity is confirmed through comparison with the experimental structure functions. The models are then characterized in accordance with the Joint Electron Device Engineering Council (JEDEC) 38-set boundary conditions, followed by a series of optimizations targeted toward the PCB, including the board stack-up and the board sizes. Parametric studies are performed to quantitatively assess the impact of these parameters on the thermal performance. Finally, the present study provides a comprehensive discussion of the optimal application scenarios for each board configuration, with a view to achieving good thermal performance. The findings of this study will contribute to the development of more thermally effective chip-on-board packages for high-performance electronic systems.
(14) D-Band Flip-Chip Packaging with Wafer-Level Cu-Pillar Bumps
Z. Cao, M. Stocchi, Ch. Wipf, J. Lehmann, L. Li, S. Tolunay Wipf, M. Wietstruck, C. Carta, M. Kaynak
Proc. 32th IEEE Conference on Electrical Performance on Electronic Packaging and Systems (EPEPS 2023), (2023)
DOI: 10.1109/EPEPS58208.2023.10314877, (FLEXCOM)
(15) Characterization and Optimization of the Heat Dissipation Capability of a Chip-on-Board Package using Finite Element Methods
Z. Cao, M. Stocchi, M. Wietstruck, T. Mausolf, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 13(3), 346 (2023)
DOI: 10.1109/TCPMT.2023.3259199, (Hytech)
The present study endeavors to investigate the thermal dissipation capability of a chip-on-board package by means of a comprehensive experimental and numerical analysis. For this purpose, a BiCMOS chip is designed and fabricated in conjunction with three different printed circuit board (PCB) configurations, including a single-sided board, a thermal via board, and a copper frame board. Transient thermal measurements are carried out on all three packages, and the results are subsequently transformed into cumulative structure functions. Then the finite element models are established for each package configuration, and their validity is confirmed through comparison with the experimental structure functions. The models are then characterized in accordance with the Joint Electron Device Engineering Council (JEDEC) 38-set boundary conditions, followed by a series of optimizations targeted toward the PCB, including the board stack-up and the board sizes. Parametric studies are performed to quantitatively assess the impact of these parameters on the thermal performance. Finally, the present study provides a comprehensive discussion of the optimal application scenarios for each board configuration, with a view to achieving good thermal performance. The findings of this study will contribute to the development of more thermally effective chip-on-board packages for high-performance electronic systems.
(16) An Advanced Finite Element Model of the Cu Pillar Solder Reflow Assembly
Z. Cao, B. Pekkolay, A. Okur, B. Heusdens, C. Carta, M. Kaynak
Proc. 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2023), (2023)
DOI: 10.1109/EuroSimE56861.2023.10100808, (FLEXCOM)
(17) An Advanced Finite Element Model of the Cu Pillar Solder Reflow Assembly
Z. Cao, B. Pekkolay, A. Okur, B. Heusdens, C. Carta, M. Kaynak
Proc. 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2023), (2023)
DOI: 10.1109/EuroSimE56861.2023.10100808, (SMARTWAVE)
(18) Study on the Metal-Graphene Contact Resistance Achieved with One-Dimensional Contact Architecture
D. Capista, R. Lukose, F. Majnoon, M. Lisker, Ch. Wenger, M. Lukosius
Proc. IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), 118 (2023)
(Graphen)
(19) Study on the Metal-Graphene Contact Resistance Achieved with One-Dimensional Contact Architecture
D. Capista, R. Lukose, F. Majnoon, M. Lisker, Ch. Wenger, M. Lukosius
Proc. IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), 118 (2023)
(2D-EPL)
(20) A Wideband W-Band Frequency Tripler with a Novel Mode-Selective Filter for High Harmonic Rejection
A. Chandra-Prabhu, J. Grzyb, P. Hillger, B. Heinemann, H. Rücker, U. Pfeiffer
Proc. 18th European Microwave Integrated Circuits Conference (EuMIC 2023), 197 (2023)
DOI: 10.23919/EuMIC58042.2023.10288850, (SG13G3)
(21) Structural and Electrical Characterization of Cerium-Tin Oxide Heterolayers for Hydrogen Sensing
C.A. Chavarin, I. Costina, Ch. Wenger, M. Ratzke,C. Morales Sanchez, Y. Kosto, I. Flege, I.A. Fischer
Proc. 10. MikroSystemTechnik Kongress (MST 2023), 1 (2023)
(iCampus II)
(22) Isothermal Heteroepitaxy of Ge1-xSnx Structures for Electronic and Photonic Applications
O. Concepción, N.B. Søgaard, J.-H. Bae, Y. Yamamoto, A.T. Tiedemann, Z. Ikonic, G. Capellini, Q.T. Zhao, D. Grützmacher, D. Buca
ACS Applied Electronic Materials 5(4), 2268 (2023)
DOI: 10.1021/acsaelm.3c00112, (DFG GeSn Laser)
Epitaxy of semiconductor-based quantum well structures is a challenging task since it requires precise control of the deposition at the submonolayer scale. In the case of Ge1–xSnx alloys, the growth is particularly demanding since the lattice strain and the process temperature greatly impact the composition of the epitaxial layers. In this paper, the realization of high-quality pseudomorphic Ge1–xSnx layers with Sn content ranging from 6 at. % up to 15 at. % using isothermal processes in an industry-compatible reduced-pressure chemical vapor deposition reactor is presented. The epitaxy of Ge1–xSnx layers has been optimized for a standard process offering a high Sn concentration at a large process window. By varying the N2 carrier gas flow, isothermal heterostructure designs suitable for quantum transport and spintronic devices are obtained.
(23) Si-Ge-Sn Heterostructures Grown by Chemical Vapor Deposition for Electronic and Photonic Devices
O. Concepción, Y. Yamamoto, G. Capellini, M. El-Kurdi, Q.-T. Zhao, D. Buca, D. Grützmacher
Proc. 55th International Conference on Solid State Devices and Materials (SSDM 2023), 517 (2023)
(24) Lattice Deformation at the Submicron Scale: X-Ray Nanobeam Measurements of Elastic Strain in Electron Shuttling Devices
C. Corley-Wiciak, M.H. Zoellner, I. Zaitsev, K. Anand, E. Zatterin, Y. Yamamoto, A.A. Corley-Wiciak, F. Reichmann, W. Langheinrich, L.R. Schreiber, C.L. Manganelli, M. Virgilio, C. Richter, G. Capellini
Physical Review Applied 20(2), 0247056 (2023)
DOI: 10.1103/PhysRevApplied.20.024056, (QLSI)
The lattice strain induced by metal electrodes can impair the functionality of advanced quantum devices operating with electron or hole spins. Here we investigate the deformation induced by CMOS-manufactured titanium nitride electrodes on the lattice of a buried, 10 nm-thick Si/SiGe Quantum Well by means of nanobeam Scanning X-ray Diffraction Microscopy. We were able to measure TiN electrode-induced local modulations of the strain tensor components in the range of 2 – 8 × 10−4 with 50 nm lateral resolution. We have evaluated that these strain fluctuations are reflected into local modulations of the potential of the conduction band minimum larger than 2 meV, which is close to the orbital energy of an electrostatic quantum dot. We observe that the sign of the strain modulations at a given depth of the quantum well layer depends on the lateral dimensions of the electrodes. Since our work explores the impact of device geometry on the strain-induced energy landscape, it enables further optimization of the design of scaled CMOS-processed quantum devices.
(25) Lattice Deformation at the Submicron Scale: X-Ray Nanobeam Measurements of Elastic Strain in Electron Shuttling Devices
C. Corley-Wiciak, M.H. Zoellner, I. Zaitsev, K. Anand, E. Zatterin, Y. Yamamoto, A.A. Corley-Wiciak, F. Reichmann, W. Langheinrich, L.R. Schreiber, C.L. Manganelli, M. Virgilio, C. Richter, G. Capellini
Physical Review Applied 20(2), 0247056 (2023)
DOI: 10.1103/PhysRevApplied.20.024056, (SiGeQuant)
The lattice strain induced by metal electrodes can impair the functionality of advanced quantum devices operating with electron or hole spins. Here we investigate the deformation induced by CMOS-manufactured titanium nitride electrodes on the lattice of a buried, 10 nm-thick Si/SiGe Quantum Well by means of nanobeam Scanning X-ray Diffraction Microscopy. We were able to measure TiN electrode-induced local modulations of the strain tensor components in the range of 2 – 8 × 10−4 with 50 nm lateral resolution. We have evaluated that these strain fluctuations are reflected into local modulations of the potential of the conduction band minimum larger than 2 meV, which is close to the orbital energy of an electrostatic quantum dot. We observe that the sign of the strain modulations at a given depth of the quantum well layer depends on the lateral dimensions of the electrodes. Since our work explores the impact of device geometry on the strain-induced energy landscape, it enables further optimization of the design of scaled CMOS-processed quantum devices.
(26) Lattice Deformation at the Submicron Scale: X-Ray Nanobeam Measurements of Elastic Strain in Electron Shuttling Devices
C. Corley-Wiciak, M.H. Zoellner, I. Zaitsev, K. Anand, E. Zatterin, Y. Yamamoto, A.A. Corley-Wiciak, F. Reichmann, W. Langheinrich, L.R. Schreiber, C.L. Manganelli, M. Virgilio, C. Richter, G. Capellini
Physical Review Applied 20(2), 0247056 (2023)
DOI: 10.1103/PhysRevApplied.20.024056, (QUASAR)
The lattice strain induced by metal electrodes can impair the functionality of advanced quantum devices operating with electron or hole spins. Here we investigate the deformation induced by CMOS-manufactured titanium nitride electrodes on the lattice of a buried, 10 nm-thick Si/SiGe Quantum Well by means of nanobeam Scanning X-ray Diffraction Microscopy. We were able to measure TiN electrode-induced local modulations of the strain tensor components in the range of 2 – 8 × 10−4 with 50 nm lateral resolution. We have evaluated that these strain fluctuations are reflected into local modulations of the potential of the conduction band minimum larger than 2 meV, which is close to the orbital energy of an electrostatic quantum dot. We observe that the sign of the strain modulations at a given depth of the quantum well layer depends on the lateral dimensions of the electrodes. Since our work explores the impact of device geometry on the strain-induced energy landscape, it enables further optimization of the design of scaled CMOS-processed quantum devices.
(27) Nanoscale Mapping of the 3D Strain Tensor in a Germanium Quantum Well Hosting a Functional Spin Qubit Device
C. Corley-Wiciak, C. Richter, M.H. Zoellner, I. Zaitev, C.L. Manganelli, E. Zatterin, T.U. Schülli, A.A. Corley-Wiciak, J. Katzer, F. Reichmann, W.M. Klesse, N.W. Hendrickx, A. Sammak, M. Veldhorst, G. Scappucci, M. Virgilio, G. Capellini
ACS Applied Materials & Interfaces 15(2), 3119 (2023)
DOI: 10.1021/acsami.2c17395, (QUASAR)
A strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by Synchrotron-based Scanning X-ray Diffraction Microscopy to determine all its Bravais lattice parameters.
This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approx. 50 nm. Two different spatial scales governing the strain field fluctuations in the proximity of the qubits are observed over < 100 nm and > 1μm respectively. The short-ranged fluctuations have a typical bandwidth of 2 · 10−4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations it is estimated that this strain fluctuation is increased up to 6·10−4 at cryogenic temperature. The longer-ranged fluctuations are of the 10−3 order, and are associated to misfit dislocations in the plastically-relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 μeV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material related inhomogeneities may feed into further modelling for the optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.
(28) Nanoscale Mapping of the 3D Strain Tensor in a Germanium Quantum Well Hosting a Functional Spin Qubit Device
C. Corley-Wiciak, C. Richter, M.H. Zoellner, I. Zaitev, C.L. Manganelli, E. Zatterin, T.U. Schülli, A.A. Corley-Wiciak, J. Katzer, F. Reichmann, W.M. Klesse, N.W. Hendrickx, A. Sammak, M. Veldhorst, G. Scappucci, M. Virgilio, G. Capellini
ACS Applied Materials & Interfaces 15(2), 3119 (2023)
DOI: 10.1021/acsami.2c17395, (QLSI)
A strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by Synchrotron-based Scanning X-ray Diffraction Microscopy to determine all its Bravais lattice parameters.
This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approx. 50 nm. Two different spatial scales governing the strain field fluctuations in the proximity of the qubits are observed over < 100 nm and > 1μm respectively. The short-ranged fluctuations have a typical bandwidth of 2 · 10−4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations it is estimated that this strain fluctuation is increased up to 6·10−4 at cryogenic temperature. The longer-ranged fluctuations are of the 10−3 order, and are associated to misfit dislocations in the plastically-relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 μeV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material related inhomogeneities may feed into further modelling for the optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.
(29) Nanoscale Mapping of the 3D Strain Tensor in a Germanium Quantum Well Hosting a Functional Spin Qubit Device
C. Corley-Wiciak, C. Richter, M.H. Zoellner, I. Zaitev, C.L. Manganelli, E. Zatterin, T.U. Schülli, A.A. Corley-Wiciak, J. Katzer, F. Reichmann, W.M. Klesse, N.W. Hendrickx, A. Sammak, M. Veldhorst, G. Scappucci, M. Virgilio, G. Capellini
ACS Applied Materials & Interfaces 15(2), 3119 (2023)
DOI: 10.1021/acsami.2c17395, (SiGeQuant)
A strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by Synchrotron-based Scanning X-ray Diffraction Microscopy to determine all its Bravais lattice parameters.
This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approx. 50 nm. Two different spatial scales governing the strain field fluctuations in the proximity of the qubits are observed over < 100 nm and > 1μm respectively. The short-ranged fluctuations have a typical bandwidth of 2 · 10−4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations it is estimated that this strain fluctuation is increased up to 6·10−4 at cryogenic temperature. The longer-ranged fluctuations are of the 10−3 order, and are associated to misfit dislocations in the plastically-relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 μeV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material related inhomogeneities may feed into further modelling for the optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.
(30) Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
A. Datsuk, P. Ostrovskyy, F. Vater, C. Wieden
Proc. 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), (2023)
DOI: 10.1109/VLSI-SoC57769.2023.10321846, (Design Kit)
(31) SiGe BiCMOS Technology with Embedded Microchannels based on Cu Pillar PCB Integration Enabling Sub-THz Microfluidic Sensor Applications
E.C. Durmaz, C. Heine, Z. Cao, J. Lehmann, D. Kissinger, M. Wietstruck
Proc. IEEE International 3D System Integration Conference (3DIC 2023), (2023)
DOI: 10.1109/3DIC57175.2023.10155073, (DFG-THz LoC)
(32) Low-Temperature Monitoring with Implantation and Alloying
L. Ende, M. Grund, U. Schwarz, C. Preiss, V. Götz, S. Ramasubramanian, J. Niess, W. Lerch, A. Scheit
MRS Advances 7, 1525 (2023)
DOI: 10.1557/s43580-022-00459-0
Rapid thermal processing is one of the key thermal processes in semiconductor manufacturing. The temperatures and times at which they are carried out range from very low to extremely high temperatures for very short or long durations depending on the application. As the temperature–time cycle has changed radically over the years, manufacturing equipments need to be monitored for the stability of the manufacturing process. This paper examines and presents especially the complex monitoring process for low temperature processing by a defined implantation condition and an alloying method capable of monitoring processes at temperatures below 600 °C to ensure the process requirements of the manufacturing flow.
(33) Prototyping Reconfigurable RRAM-based AI Accelerators using the RISC-V Ecosystem and Digital Twins
M. Fritscher, A. Veronesi, A. Baroni, J. Wen, T. Spätling, M.K. Mahadevaiah, N. Herfurth, E. Perez, M. Ulbricht, M. Reichenbach, A. Hagelauer, M. Krstic
Proc. 1st International Conference on High Performance Computing (ISC High Performance 2023), in: Lecture Notes in Computer Science, Springer, LNCS 13999, 500 (2023)
DOI: 10.1007/978-3-031-40843-4_37, (KI-PRO)
(34) Prototyping Reconfigurable RRAM-based AI Accelerators using the RISC-V Ecosystem and Digital Twins
M. Fritscher, A. Veronesi, A. Baroni, J. Wen, T. Spätling, M.K. Mahadevaiah, N. Herfurth, E. Perez, M. Ulbricht, M. Reichenbach, A. Hagelauer, M. Krstic
Proc. 1st International Conference on High Performance Computing (ISC High Performance 2023), in: Lecture Notes in Computer Science, Springer, LNCS 13999, 500 (2023)
DOI: 10.1007/978-3-031-40843-4_37, (KI-IoT)
(35) Prototyping Reconfigurable RRAM-based AI Accelerators using the RISC-V Ecosystem and Digital Twins
M. Fritscher, A. Veronesi, A. Baroni, J. Wen, T. Spätling, M.K. Mahadevaiah, N. Herfurth, E. Perez, M. Ulbricht, M. Reichenbach, A. Hagelauer, M. Krstic
Proc. 1st International Conference on High Performance Computing (ISC High Performance 2023), in: Lecture Notes in Computer Science, Springer, LNCS 13999, 500 (2023)
DOI: 10.1007/978-3-031-40843-4_37, (iCampus II)
(36) Prototyping Reconfigurable RRAM-based AI Accelerators using the RISC-V Ecosystem and Digital Twins
M. Fritscher, A. Veronesi, A. Baroni, J. Wen, T. Spätling, M.K. Mahadevaiah, N. Herfurth, E. Perez, M. Ulbricht, M. Reichenbach, A. Hagelauer, M. Krstic
Proc. 1st International Conference on High Performance Computing (ISC High Performance 2023), in: Lecture Notes in Computer Science, Springer, LNCS 13999, 500 (2023)
DOI: 10.1007/978-3-031-40843-4_37, (VE-HEP)
(37) Prototyping Reconfigurable RRAM-based AI Accelerators using the RISC-V Ecosystem and Digital Twins
M. Fritscher, A. Veronesi, A. Baroni, J. Wen, T. Spätling, M.K. Mahadevaiah, N. Herfurth, E. Perez, M. Ulbricht, M. Reichenbach, A. Hagelauer, M. Krstic
Proc. 1st International Conference on High Performance Computing (ISC High Performance 2023), in: Lecture Notes in Computer Science, Springer, LNCS 13999, 500 (2023)
DOI: 10.1007/978-3-031-40843-4_37, (6G-RIC)
(38) Toward FEOL Integration of SiN Waveguides into a Photonic BiCMOS Process
F. Goetz, St. Lischke, G. Georgieva, A. Peczek, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), WC5 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141964, (PEARLS)
(39) Toward FEOL Integration of SiN Waveguides into a Photonic BiCMOS Process
F. Goetz, St. Lischke, G. Georgieva, A. Peczek, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), WC5 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141964, (DFG ULTRA 2)
(40) On Cold Operation of an SiGe HBT as a Broadband Low-NEP THz Direct Detector
J. Grzyb, M. Andree, B. Heinemann, H. Rücker, U. Pfeiffer
Proc. 48th International Conference on Infrared, Millimeter and Terahertz Waves (IRMMW-THz 2023), (2023)
DOI: 10.1109/IRMMW-THz57677.2023.10299102
(41) Thermal Analysis and Design of a Ka-Band Power Amplifier in 130 nm SiGe BiCMOS
A. Haag, M. Kaynak, A.C. Ulusoy
Proc. 23rd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2023), 47 (2023)
DOI: 10.1109/SiRF56960.2023.10046279
(42) Strongly Enhanced Sensitivities of CMOS Compatible Plasmonic Titanium Nitride Nanohole Arrays for Refractive Index Sensing under Oblique Incidence
W. Han, S. Reiter, J. Schlipf, Ch. Mai, D. Spirito, J. Jose, Ch. Wenger, I.A. Fischer
Optics Express 31(11), 17389 (2023)
DOI: 10.1364/OE.481993, (iCampus)
TiN is a complementary metal-oxide-semiconductor (CMOS) compatible material with large potential for the fabrication of plasmonic structures suited for device integration. However, the comparatively large optical losses can be detrimental for application. This work reports a CMOS compatible TiN nanohole array (NHA) on top of a multilayer stack for potential use in integrated refractive index sensing with high sensitivities. The stack, consisting of the TiN NHA on a silicon dioxide (SiO2) layer with Si as substrate (TiN NHA/SiO2/Si), is prepared using an industrial CMOS compatible process. The TiN NHA/SiO2/Si shows Fano resonances in reflectance spectra under oblique excitation, which are very well reproduced by simulation using both finite difference time domain (FDTD) and rigorous coupled-wave analysis (RCWA) methods. Our systematic simulation-based investigation of the sensitivity of the TiN NHA/SiO2/Si stack under varied conditions reveals that very large sensitivities up to 2305 nm per refractive index unit (nm RIU–1) are predicted when the refractive index of superstrate is similar to that of the SiO2 layer. We analyze in detail how the interplay between plasmonic and photonic resonances such as surface plasmon polaritons (SPPs), localized surface plasmon resonances (LSPRs), Rayleigh Anomalies (RAs), and photonic microcavity modes (Fabry-Pérot resonances) contributes to this result. This work not only reveals the tunability of TiN nanostructures for plasmonic applications but also paves the way to explore efficient devices for sensing in broad conditions.
(43) MBE-Based Growth of Sn-Rich Quantum Wells and Dots at Low Sn Deposition Rates
A. Hayat, D. Spirito, A.A. Corley-Wiciak, M.A. Schubert, M. Masood, F. Reichmann, M. Ratzke, G. Capellini, I.A. Fischer
Materials Science in Semiconductor Processing 165, 107693 (2023)
DOI: 10.1016/j.mssp.2023.107693
Alloying Ge with Sn is a possible route towards obtaining a direct bandgap material that can be integrated with Si technology for optoelectronic device applications. Low-dimensional structures such as GeSn quantum wells or islands are of particular interest, since those applications can benefit from quantum confinement effects. Here, we investigate the formation of Sn-rich quantum wells and islands formed by the deposition of few MLs of Sn on Ge and their overgrowth with Ge both based on a morphological characterization of the samples as well as photoluminescence measurements. We find that a low substrate temperature as well as a low deposition rate have an impact on the critical layer thickness at which the onset of Sn island formation can be observed and discuss the implications both for the samples grown and future research efforts.
(44) Silicon Photonic Supported by Dielectrophoresis for Detecting Microbes
A. Henriksson, M. Altmann, P. Neubauer, M. Birkholz
Proc. 4th European Biosensor Symposium (EBS 2023), 116 (2023)
(Bioelectronics)
(45) Reliable Backside IC Preparation Down to STI Level Using Chemical Mechanical Polishing (CMP) with Highly Selective Slurry
N. Herfurth, A.A. Adesunkanmi, G. Zwicker, C. Boit
Proc. 49th International Symposium for Testing and Failure Analysis (ISTFA 2023), 265 (2023)
DOI: 10.31399/asm.cp.istfa2023p0265
(46) Selective Electrodeposition of Indium Microstructures on Silicon and their Conversion into InAs and InSb Semiconductors
K.E. Hnida-Gut, M. Sousa, P. Tiwari, H. Schmid
Discover Nano 18, 4 (2023)
DOI: 10.1186/s11671-023-03778-9
The idea of benefitting from the properties of III-V semiconductors and silicon on the same substrate has been occupying the minds of scientists for several years. Although the principle of III-V integration on a silicon-based platform is simple, it is often challenging to perform due to demanding requirements for sample preparation rising from a mismatch in physical properties between those semiconductor groups (e.g. different lattice constants and thermal expansion coefficients), high cost of device-grade materials formation and their post-processing. In this paper, we demonstrate the deposition of group-III metal and III-V semiconductors in microfabricated template structures on silicon as a strategy for heterogeneous device integration on Si. The metal (indium) is selectively electrodeposited in a 2-electrode galvanostatic configuration with the working electrode (WE) located in each template, resulting in well-defined In structures of high purity. The semiconductors InAs and InSb are obtained by vapour phase diffusion of the corresponding group-V element (As, Sb) into the liquified In confined in the template. We discuss in detail the morphological and structural characterization of the synthesized In, InAs and InSb crystals as well as chemical analysis through scanning electron microscopy (SEM), scanning transmission electron microscopy (TEM/STEM), and energy-dispersive X-ray spectroscopy (EDX). The proposed integration path combines the advantage of the mature top-down lithography technology to define device geometries and employs economic electrodeposition (ED) and vapour phase processes to directly integrate difficult-to-process materials on a silicon platform.
(47) Formation of One-Dimensionally Self–Aligned Si–QDs and their Local Electron Charging Properties
Y. Imai, K. Makihara , Y. Yamamoto, W.-C. Wen, M.A. Schubert, J. Baek, R. Tsuji, N. Taoka, A. Ohta, S. Miyazaki
Proc. 55th International Conferene on Solid State Devices and Materials (SSDM 2023), 523 (2023)
(48) Tunable and Highly Power Efficient Traveling Wave Amplifier in SiGe BiCMOS for Optical Modulators
M. Inac, F. Korndörfer, F. Gerfers, A. Malignaggi
Proc. Radio Wireless Week (RWW 2023), 58 (2023)
DOI: 10.1109/SiRF56960.2023.10046248
(49) DC-Coupled Ultra Broadband Differential to Single-Ended Active Balun in 130-nm SiGe BiCMOS Technology
F. Iseini, A. Malignaggi, F. Korndörfer, G. Kahmen
IEEE Microwave and Wireless Components Letters 33(3), 307 (2023)
DOI: 10.1109/LMWC.2022.3216347, (100G)
The dc-coupled (DCC) broadband operation is a fundamental requirement in many applications, especially in optical communication systems. However, circuits allowing differential to single-ended conversion in a DCC fashion are very rare to be found in the literature. In this letter, a novel differential to single-ended ultrabroadband DCC balun in a 130-nm SiGe BiCMOS technology featuring ft/fmax of 300/500 GHz is presented. A circuit analysis and a performance comparison between the proposed balun and two other configurations which are commonly used to convert a differential signal to a single-ended one is carried out. The design of the mentioned balun is described focusing on the trade-offs between gain, bandwidth (BW) and linearity. Measurement results show how the presented topology can achieve a low-frequency power gain of −7 dB and a 1 dB BW of 80 GHz, along with a total harmonic distortion (THD) of 7%.
(50) Determining Graphene and Substrate Quality from the Coupled Hall Mobility Measurements and Theoretical Modeling
K. Japec, M. Matić, R. Lukose, M. Lisker, M. Lukosius, M. Poljak
46th MIPRO ICT and Electronics Convention (MIPRO 2023), 179 (2023)
DOI: 10.23919/MIPRO57284.2023.10159692, (GRONGER)
(51) A Si Photonic BiCMOS Coherent QPSK Transmitter Based on Parallel-Dual Ring Modulators
Y. Jo, Y. Ji, M. Kim, H.-K. Kim, M.-H. Kim, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), WC4 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141915
(52) Monte-Carlo Characterization of Si Ring Modulator PAM-4 Eye Diagram Performance
Y. Jo, Y. Ji, M. Kim, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
Japanese Journal of Applied Physics 62(6), 066502 (2023)
DOI: 10.35848/1347-4065/acd3cb
The eye diagram performance of the Si ring modulator (RM) is Monte-Carlo characterized with the RM equivalent circuit model. Inter-die statistical distributions of Si-RM model parameters are determined from simple RM optical transmission and electrical reflection coefficient measurement, and the correlated model parameter sets are randomly generated for Monte-Carlo simulation of 40-Gbps 4-level pulse amplitude modulation (PAM-4) eye diagrams within SPICE. From the resulting Monte-Carlo simulated eye diagrams, the yield for the Si RMs that satisfy optical modulation amplitude (OMA) and ratio of level mismatch (RLM) requirements can be corroborated with measurement. With these, the eye diagrams of Si electronic-photonic integrated PAM-4 transmitter with RMs and driver electronics are Monte-Carlo characterized. This approach allows the extension of the standard Si IC characterization technique to the electronic-photonic ICs and can produce better-performing solutions with better yields in the design stage.
(53) Vertical Gate-All-Around SiGeSn/GeSn/SiGeSn Nanowire nFETs
Y. Junk, O. Concepción, M. Frauenrath, F. Bärwolf, A. Mai, J.-M. Hartmann, D. Grützmacher, D. Buca, Q.-T. Zhao
Proc. 55th International Conference on Solid State Devices and Materials (SSDM 2023), 649 (2023)
(54) Monolithic Integration of InP Nanowires with CMOS Fabricated Silicon Nanotips Wafer
A. Kamath, O. Skibitzki, D. Spirito, S. Dadgostar, I.M. Martinez, M. Schmidbauer, C. Richter, A. Kwasniewski, J. Serrano, J. Jimenez, C. Golz, M.A. Schubert, J.W. Tomm, N. Gang, F. Hatami
Physical Review Materials 7(10), 103801 (2023)
DOI: 10.1103/PhysRevMaterials.7.103801, (NHEQuanLEA)
The integration of both optical and electronic components on a single chip, despite several challenges, holds the promise of compatibility with complementary metal-oxide semiconductor (CMOS) technology and high scalability. Among all candidate materials, III-V semiconductors exhibit great potential for optoelectronics and quantum-optics based devices, such as light emitters and harvesters. The control over geometry, and dimensionality of the III-V nanostructures, enables one to modify the band structures, and hence provide a powerful tool for tailoring the optoelectronic properties of III-V compounds. One of the most creditable approaches towards such growth control is the combination of using a patterned wafer and the self-assembled epitaxy. This work presents monolithically integrated catalyst-free InP nanowires grown selectively on Si nanotip-patterned, CMOS compatible (001) Si substrates using gas-source molecular-beam epitaxy. We use nanoheteroepitaxy approach to selectively grow InP nanowires on Si nanotips, which holds benefits due to its peculiar substrate design. In addition, our methodology allows the switching of dimensionality of the InP structures between one-dimensional nanowires and three-dimensional bulklike InP nanoislands by thermally modifying the shape of silicon nanotips surrounded by the silicon dioxide layer during the thermal cleaning of the substrate. The structural and optical characterization of nanowires indicates the coexistence of both zincblende and wurtzite InP crystal phases in nanowires. The two different crystal structures were aligned with a type-II band alignment. The luminescence from InP nanowires was measured up to 300 K, which reveals their promising optical quality for integrated photonics and optoelectronic applications.
(55) A 10-100-GHz Wideband Amplifier with Low-Impedance Coupled Lines in SiGe BiCMOS
D. Kim, H. Son, J. Kim, J. Lee, Y. Zhao, R. Al Hadi, M. Kaynak, M.-C.F. Chang, J.-S. Rieh
IEEE Microwave and Wireless Technology Letters (MWTL) 33(9),1313 (2023)
DOI: 10.1109/LMWT.2023.3288114
This letter presents a mm-wave wideband amplifier implemented in a 130-nm SiGe BiCMOS technology operating up to 100 GHz. For the wideband operation, a new wideband technique based on low-impedance coupled line structure was proposed and adopted to the amplifier in combination with other bandwidth extension techniques. The enhancement of the amplifier bandwidth with the low-impedance coupled lines employed at the input and output matching networks is introduced in detail along with methodologies for actual implementation. The fabricated amplifier showed a peak gain of 13.2 dB with a 3-dB bandwidth of 90 GHz, covering from 10 to 100 GHz. The power consumption of the amplifier is 117 mW. The chip size is 865 × 344 μm2 excluding probing pads.
(56) Investigation of the Impact of Amorphous Silicon Layers Deposited by PECVD and HDP-CVD on Oxide Precipitation in Silicon
G. Kissinger, D. Kot, F. Bärwolf, M. Lisker
Materials Science in Semiconductor Processing 164, 107614 (2023)
DOI: 10.1016/j.mssp.2023.107614, (Future Silicon Wafers)
The effect of deposited a-Si layers with different layer stress on oxide precipitation was investigated in order to find out if intrinsic point defects affecting oxide precipitation are generated at the interface a-Si/Si and if possibly hydrogen affects the oxide precipitation. A thermal cycle of nucleation at 650 °C for 4 h or 8 h followed by stabilization at 780 °C for 3 h, and growth at 1000 °C for 16 h was applied. It was found that there are no signs for the injection of intrinsic point defects from the interface a-Si/Si into the Si substrate during the applied thermal treatment. However if a-Si is deposited on 1000 nm silicon oxide, deposited previously from TEOS in a plasma process, silicon self-interstitials seem to be injected from the interface silicon oxide/Si into the silicon substrate retarding oxide precipitation in the initial stage of nucleation annealing at 650 °C. There are also no signs of any impact of the layer stress on oxide precipitation or self-interstitial injection. The concentration of hydrogen in the layers can be controlled via the RF bias power. The hydrogen concentration is reduced markedly already during annealing at 650 °C. Part of the hydrogen diffuses into the silicon substrate and enhances oxide precipitation if its initial concentration in the layers is higher than 1.5 × 1022 cm−3. For a-Si deposited on 1000 nm silicon oxide, the enhancement effect appears for hydrogen concentrations in the layer higher than approximately 2.8 × 1022 cm−3.
(57) Resiliency in Digital Processing Systems
M. Krstic, M. Andjelkovic, J.-C. Chen, L. Lu, A. Veronesi, M. Ulbricht
Proc. 33rd IEEE International Conference on Microelectronics (MIEL 2023), 19 (2023)
DOI: 10.1109/MIEL58498.2023.10315819, (Scale4Edge)
(58) Ultra-Fast Germanium Photodiodes
St. Lischke, A. Peczek, D. Steckler, J. Morgan, A. Beling, L. Zimmermann
Proc. Conference on Lasers and Electro-Optics (CLEO 2023), SM4G.5 (2023)
DOI: 10.1364/CLEO_SI.2023.SM4G.5, (DFG EPIDAC)
(59) Ultra-Fast Germanium Photodiodes
St. Lischke, A. Peczek, D. Steckler, J. Morgan, A. Beling, L. Zimmermann
Proc. Conference on Lasers and Electro-Optics (CLEO 2023), SM4G.5 (2023)
DOI: 10.1364/CLEO_SI.2023.SM4G.5, (plaCMOS)
(60) Ultra-Fast Germanium Photodiodes
St. Lischke, A. Peczek, D. Steckler, J. Morgan, A. Beling, L. Zimmermann
Proc. Conference on Lasers and Electro-Optics (CLEO 2023), SM4G.5 (2023)
DOI: 10.1364/CLEO_SI.2023.SM4G.5, (DFG EPIC-Sense 2)
(61) Ultra-Fast Germanium Photodiodes
St. Lischke, A. Peczek, D. Steckler, J. Morgan, A. Beling, L. Zimmermann
Proc. Conference on Lasers and Electro-Optics (CLEO 2023), SM4G.5 (2023)
DOI: 10.1364/CLEO_SI.2023.SM4G.5, (DFG ULTRA 2)
(62) Plasma-Enhanced Atomic Layer Deposition of Silicon Nitride for Front-End-of-Line Applications
M. Lisker, M.K. Mahadevaiah, K. Dorai Swamy Reddy
Journal of Vacuum Science and Technology A 41(4), 042406 (2023)
DOI: 10.1116/6.0002424
SiN deposition at low temperatures using the plasma-enhanced atomic layer deposition (PEALD) process is gaining momentum. A high-quality SiN layer deposited using a lower thermal budget and low wet etch rates are desired for front-end-of-line applications in semiconductor industries. In this study, deposition of PEALD SiN is investigated by utilizing a highly reactive trisilylamine silicon precursor and three different reaction partners for a nitrogen precursor. The quality of PEALD SiN layers is compared with the reference standard, low-pressure chemical vapor deposition SiN layers. The properties of different SiN layers are interpreted using FTIR and XPS material characterization techniques. Furthermore, the wet etch rates of as-deposited and annealed PEALD SiN layers are investigated. Finally, the conformality of PEALD SiN layers is assessed in trench and horizontal high aspect ratio structures.
(63) Vertical GeSn Nanowire MOSFETs for CMOS Beyond Silicon
M. Liu, Y. Junk, Y. Han, D. Yang, J.H. Bae, M. Frauenrath, J.-M. Hartmann, Z. Ikonic, F. Bärwolf, A. Mai, D. Grützmacher, J. Knoch, D.M. Buca, Q.-T. Zhao
Communications Engineering 2, 7 (2023)
DOI: 10.1038/s44172-023-00059-2, (SiGeSn NanoFETs)
The continued downscaling of silicon CMOS technology presents challenges for achieving the required low power consumption. While high mobility channel materials hold promise for improved device performance at low power levels, a material system which enables both high mobility n-FETs and p-FETs, that is compatible with Si technology and can be readily integrated into existing fabrication lines is required. Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transconductance is increased to 850 µS/µm by exploiting the small band gap of GeSn as source yielding high injection velocities, the mobility in n-FETs is increased 2.5-fold compared to a Ge reference device, by using GeSn as channel material. The potential of the material system for a future beyond Si CMOS logic and quantum computing applications is demonstrated via a GeSn inverter and steep switching at cryogenic temperatures, respectively.
(64) Strain Relaxation from Annealing of SiGe Heterostructures for Qubits
Y. Liu, K.-P. Gradwoh, C.-H. Lu, K. Dadzis, Y. Yamamoto, L. Becker, P. Storck, T. Remmele, T. Boeck, C. Richter, M. Albrecht
Journal of Applied Physics 134(3), 035302 (2023)
DOI: 10.1063/5.0155448
The misfit dislocation formation related to plastic strain relaxation in Si or Ge quantum well layers in SiGe heterostructures for spin qubits tends to negatively affect the qubit behaviors. Therefore, it is essential to understand and then suppress the misfit dislocation formation in the quantum well layers in order to achieve high-performance qubits. In this work, we studied the misfit dislocation propagation kinetics and interactions by annealing the strained Si or Ge layers grown by molecular beam epitaxy. The annealing temperatures are from 500 to 600 °C for Si layers and from 300 to 400 °C for Ge layers. The misfit dislocations were investigated by electron channeling contrast imaging. Our results show that the misfit dislocation propagation is a thermally activated process. Alongside, the blocking and unblocking interactions during misfit dislocations were also observed. The blocking interactions will reduce the strain relaxation according to theoretical calculation. These observations imply that it is possible to suppress the misfit dislocation formation kinetically by reducing the temperatures during the SiGe heterostructure epitaxy and post-epitaxy processes for developing well-functional SiGe-based spin qubits.
(65) Growth of 28Si Quantum Well Layers for Qubits by a Hybrid MBE/CVD Technique
Y. Liu, K.-P. Gradwohl, C.-H. Lu, Y. Yamamoto, T. Remmele, C. Corley-Wiciak, T. Teubner, C. Richter, M. Albrecht, T. Boeck
ECS Journal of Solid State Science and Technology 12(2), 024006 (2023)
DOI: 10.1149/2162-8777/acb734
Isotopically enriched 28Si quantum well layers in SiGe/Si/SiGe heterostructures are an excellent material platform for electron spin qubits. Here, we report the fabrication of 28SiGe/28Si/28SiGe heterostructures for qubits by a hybrid molecular beam epitaxy (MBE) / chemical vapour deposition (CVD) growth, where the thick relaxed SiGe substrates are realised by a reduced-pressure CVD and the 28SiGe/28Si/28SiGe stacks are grown by MBE. We achieve a fully strained 28Si quantum well layer in such heterostructures with a 29Si concentration as low as 200 ppm within the MBE grown layers and conclude that 29Si primarily originates from the residual natural Si vapour in the MBE chamber. A reliable surface preparation combining ex-situ wet chemical cleaning and in-situ annealing and atomic hydrogen irradiation offers epitaxy ready CVD grown SiGe substrates with low carbon and oxygen impurities. Furthermore, we also present our studies about the growth temperature effect on the misfit dislocation formation in this heterostructure. This shows that the misfit dislocation formation is significantly suppressed at a low MBE growth temperature, such as 350°C.
(66) Development of a 200 mm Wafer Silicon Nitride PIC Environment for Graphene Electro-Absorption Modulators
R. Lukose, M. Lisker, P.K. Dubey, M.A.I. Raju, A. Peczek, A. Kroh, M. Lukosius, A. Mai
Proc. 55th International Conference on Solid State Devices and Materials (SSDM 2023), 403 (2023)
(2D-EPL)
(67) Integration of Memristive Devices into a 130 nm CMOS Baseline Technology
M.K. Mahadevaiah, M. Lisker, M. Fraschke, St. Marschmeyer, E. Perez, E. Perez-Bosch Quesada, Ch. Wenger, A. Mai
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Integration of Memristive Devices into a 130 nm CMOS Baseline Technology, Springer Series on Bio- and Neurosystems (SSDM) 16, Springer, 177 (2023)
DOI: 10.1007/978-3-031-36705-2_7, (NeuroMem)
(68) Integration of Memristive Devices into a 130 nm CMOS Baseline Technology
M.K. Mahadevaiah, M. Lisker, M. Fraschke, St. Marschmeyer, E. Perez, E. Perez-Bosch Quesada, Ch. Wenger, A. Mai
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Integration of Memristive Devices into a 130 nm CMOS Baseline Technology, Springer Series on Bio- and Neurosystems (SSDM) 16, Springer, 177 (2023)
DOI: 10.1007/978-3-031-36705-2_7, (FMD)
(69) Integration of Memristive Devices into a 130 nm CMOS Baseline Technology
M.K. Mahadevaiah, M. Lisker, M. Fraschke, St. Marschmeyer, E. Perez, E. Perez-Bosch Quesada, Ch. Wenger, A. Mai
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Integration of Memristive Devices into a 130 nm CMOS Baseline Technology, Springer Series on Bio- and Neurosystems (SSDM) 16, Springer, 177 (2023)
DOI: 10.1007/978-3-031-36705-2_7, (Neutronics)
(70) SiGe- and Ge-based Devices as Key Enabler of High Performance RF Electronic and Photonic Technologies
A. Mai
Proc. 13th International WorkShop on New Group IV Semiconductor Nanoelectronics (2023), abstr. book 1 (2023)
(71) Room Temperature Light Emission from Superatom-Like Ge-Core/Si-Shell Quantum Dots
K. Makihara, Y. Yamamoto, Y. Imai, N. Taoka, M.A. Schubert, B. Tillack, S. Miyazaki
Nanomaterials 13(9), 1475 (2023)
DOI: 10.3390/nano13091475
We have demonstrated the high–density formation of super–atom–like Si quantum dots with Ge–core on ultrathin SiO2 with control of high–selective chemical–vapor deposition and applied them to an active layer of light–emitting diodes (LEDs). Through luminescence measurements, we have reported characteristics carrier confinement and recombination properties in the Ge–core, reflecting the type II energy band discontinuity between the Si–clad and Ge–core. Additionally, under forward bias conditions over a threshold bias for LEDs, electroluminescence becomes observable at room temperature in the near–infrared region and is attributed to radiative recombination between quantized states in the Ge–core with a deep potential well for holes caused by electron/hole simultaneous injection from the gate and substrate, respectively. The results will lead to the development of Si–based light–emitting devices that are highly compatible with Si–ultra–large–scale integration processing, which has been believed to have extreme difficulty in realizing silicon photonics.
(72) TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance
D. Maldonado, A. Cantudo, E. Perez, R. Romero-Zaliz, E. Perez-Bosch Quesada, M.K. Mahadevaiah, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Frontiers in Neuroscience 17, 1271956 (2023)
DOI: 10.3389/fnins.2023.1271956, (KI-IoT)
We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.
(73) Gain Measurements of the First Proof-of-Concept PicoAD Prototype with a 55Fe X-Ray Radiative Source
M. Milanesio, G. Lacobucci, L. Paolozzi, M. Munker, R. Cardella, Y. Gurimskaya, F. Matinelli, A. Picardi, H. Rücker, A. Trusch, P. Valerio, F. Cadoux, R. Cardarelli, S. Debieux, Y. Favre, D. Ferrere, S. Gonzalez-Sevilla, R. Kotitsa, C. Magliocca, T. Moretti, M. Nessi, J. Saidi, M. Vicente Barreto Pinto, S. Zambito
Nuclear Instruments and Methods in Physics Research Section A 1046, 167807 (2023)
DOI: 10.1016/j.nima.2022.167807
The Picosecond Avalanche Detector is a multi-junction silicon pixel detector devised to enable charged-particle tracking with high spatial resolution and picosecond time-stamping capability. A proof-of-concept prototype of the PicoAD sensor has been produced by IHP microelectronics. Measurements with a 55Fe X-ray radioactive source show that the prototype is functional with an avalanche gain up to a maximum electron gain of 23.
(74) First 100 Gb/s Monolithically Integrated Electronic-Photonic Coherent Receiver with Direct Edge Coupling to Standard Single Mode Fiber Array
A. Osman, G. Winzer, Ch. Mai, A. Peczek, K. Voigt, W. Dorward, St. Lischke, M. Inac, A. Malignaggi, L. Zimmermann, I. Sourikopoulos, L. Stampoulidis
Proc. Optical Fiber Communication Conference (OFC 2023), M3I.3 (2023)
DOI: 10.1364/OFC.2023.M3I.3
(75) Preparation and Investigation of Micro-Transfer-Printable Single-Crystalline InP Coupons for Heterogeneous Integration of III-V on Si
I. Peracchi, C. Richter, T. Schulz, J. Martin, A. Kwasniewski, S. Kläger, C. Frank-Rotsch, P. Steglich, K. Stolze
Crystals (MDPI) 13(7), 1126 (2023)
DOI: 10.3390/cryst13071126
New requirements for high-frequency applications in wireless communication and sensor technologies need III-V compound semiconductors such as indium phosphide (InP) to complement silicon (Si)-based technologies. This study establishes the basis for a new approach to heterogeneous integration of III-V on Si aimed at the transfer of single-crystalline InP coupons on Si via micro-transfer printing (μTP). The InP coupons will act as high-quality virtual substrates that allow selective homo-epitaxy. We present the chemical-mechanical polishing-based preparation and structural characterization of µm-thin (001) InP platelets, starting from high-quality 4-inch bulk crystals and micro-patterning into transferable coupons of several hundred µm2. The obtained InP platelets exhibit the desired thickness—below 10 ± 1 µm—and low surface roughness—<0.3 nm—on both sides, meeting the precondition for µTP and epitaxy. X-ray rocking curve measurements provide accurate spatial maps of the total strain, which indicate small strain variations in the µm-thin InP sample. Rocking curve mappings of the (0 0 4) reflection reveal half-widths below 16 arcsec in the majority of the sample area after thinning that is similar to commercially available InP bulk substrates. Pole figure measurements show no evidence of stress-induced micro-twinning or stacking faults. Overall, minor indications of crystal quality degradation in the product platelets, compared with the bulk samples, were detected.
(76) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (MIMEC)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(77) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (KI-PRO)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(78) Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale
E. Perez, D. Maldonado, E. Perez-Bosch Quesada, M.K. Mahadevaiah, F. Jimenez-Molinos, Ch. Wenger, J.B. Rodan
IEEE Transactions on Electron Devices 70(1), 360 (2023)
DOI: 10.1109/TED.2021.3072868, (KI-IoT)
The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.
(79) A 142 GHz 4/5 Dual-Modulus Prescaler for Wideband and Low Noise Frequency Synthesizers in 130 nm SiGe:C BiCMOS
L. Polzin, M. van Delden, N. Pohl, H. Rücker, T. Musch
Proc. IEEE MTT-S International Microwave Symposium (IMS 2023), Tu3E-3 (2023)
(80) A 142-GHz 4/5 Dual-Modulus Prescaler for Wideband and Low Noise Frequency Synthesizers in 130-nm SiGe:C BiCMOS
L. Polzin, M. van Delden, N. Pohl, H. Rücker, T. Musch
IEEE Microwave and Wireless Technology Letters (MWTL) 33(6), 867 (2023)
DOI: 10.1109/LMWT.2023.3265861
In this contribution, the simulation and measurement results of a 4/5 dual-modulus prescaler, operating from dc to 142 GHz with a power consumption of 144 mW, are presented. For a division ratio of 4, the maximum operation frequency of 166 GHz is even higher. The prescaler is the core of a fully programmable dual-modulus frequency divider, which is a crucial component of modern measurement systems. The effect of the physical lengths and the resulting internal delays on the prescaler’s performance is analyzed. Furthermore, the voltage level of the fully differential emitter-coupled logic (ECL) is optimized in terms of phase noise and maximum operating frequency. The monolithic microwave integrated circuit (MMIC) is realized in a 130-nm SiGe:C BiCMOS technology with fT/ fmax = 470/650 GHz.
(81) Broadband Hetero-Integration of InP Chiplets on SiGe BiCMOS for mm-Wave MMICs up to 325 GHz
M. Rausch, M. Wietstruck, C. Stölmacker, R. Doerner, G. Fischer, S. Knigge, H. Yacoub, W. Heinrich
Proc. IEEE MTT-S International Microwave Symposium (IMS 2023), 466 (2023)
DOI: 10.1109/IMS37964.2023.10188164, (T-KOS)
(82) Titanium Nitride Plasmonic Nanohole Arrays for CMOS-Compatible Integrated Refractive Index Sensing: Influence of Layer Thickness on Optical Properties
S. Reiter, W. Han, Ch. Mai, D. Spirito, J. Jose, M.H. Zoellner, O. Fursenko, M.A. Schubert, Ch. Wenger, I.A. Fischer
Plasmonics 18, 831 (2023)
DOI: 10.1007/s11468-023-01810-3, (iCampus II)
The combination of nanohole arrays with photodetectors can be a strategy for the large-scale fabrication of miniaturized and cost-effective refractive index sensors on the Si platform. However, complementary metal–oxide–semiconductor (CMOS) fabrication processes place restrictions in particular on the material that can be used for the fabrication of the structures. Here, we focus on using the CMOS compatible transition metal nitride Titanium Nitride (TiN) for the fabrication of nanohole arrays (NHAs). We investigate the optical properties of TiN NHAs with different TiN thicknesses (50 nm, 100 nm, and 150 nm) fabricated using high-precision industrial processes for possible applications in integrated, plasmonic refractive index sensors. Reflectance measurements show pronounced Fano-shaped resonances, with resonance wavelengths between 950 and 1200 nm, that can be attributed to extraordinary optical transmission (EOT) through the NHAs. Using the measured material permittivity as an input, the measured spectra are reproduced by simulations with a large degree of accuracy: Simulated and measured resonance wavelengths deviate by less than 10 nm, with an average deviation of 4 nm observed at incidence angles of 30° and 40°. Our experimental results demonstrate that an increase in the thickness of the TiN layer from 50 to 150 nm leads to a sensitivity increase from 614.5 nm/RIU to 765.4 nm/RIU, which we attribute to a stronger coupling between individual LSPRs at the hole edges with spatially extended SPPs. Our results can be used to increase the performance of TiN NHAs for applications in on-chip plasmonic refractive index sensors.
(83) Evaluation of Si and Ge Segregation from Si0.2Ge0.8(111) through Al and Ag Layer
T. Sakai, A. Ohta, N. Taoka, J. Yuhara, K. Makihara, Y. Yamamoto, W.-C. Wen, S. Miyazaki
Proc. 55th International Conference on Solid State Devices and Materials (SSDM 2023), 33 (2023)
(84) Robust Si/Ge Heterostructure Metasurfaces as Building Blocks for Wavelength-Selective Photodetectors
J. Schlipf, F. Berkmann, Y. Yamamoto, M. Reichenbach, M. Veleski, Y. Kawaguchi, F. Mörz, J.W. Tomm, D. Weißhaupt, I.A. Fischer
Applied Physics Letters 122(12), 121701 (2023)
DOI: 10.1063/5.0134458
We present a design for silicon-compatible vertical Germanium pin photodiodes structured into all-dielectric metasurfaces. Proof-of-principle metasurfaces are fabricated on silicon-on-insulator wafers in a top-down process. Simulations and measurements of the spectroscopic properties, specifically the absorption, show high spectral selectivity, and absorption efficiencies as large as those in bulk Germanium layers with about four times the Ge layer thicknesses. Our metasurface structures can be tuned to the target wavelength through tailoring of the lateral geometry. Possible applications include spectroscopy and hyperspectral imaging, with several metasurfaces for different wavelength ranges integrated with readout circuitry into a low-cost electronic–photonic integrated circuit.
(85) A Differential SiGe HBT Doherty Power Amplifier for Automotive Radar at 79 GHz
J. Schoepfel, H. Rücker, N. Pohl
Proc. 23rd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2023), 44 (2023)
DOI: 10.1109/SiRF56960.2023.10046275, (SG13G3)
(86) 190 GBd PAM-4 Signal Generation using Analog Multiplexer IC with On-Chip Clock Multiplier
J. Schostak, T. Tannert, M. Grözing, V. Jungnickel, C. Schmidt, H. Rücker, M. Berroth, R. Freund
Proc. 18th European Microwave Integrated Circuits Conference (EuMIC 2023), 125 (2023)
DOI: 10.23919/EuMIC58042.2023.10288816, (SG13G3)
(87) Al-Al Waferbonding Process Development For Heterogeneous Integration
S. Schulze, T. Voß, P. Krüger, M. Wietstruck
ECS Transactions 112(19), 25 (2023)
DOI: 10.1149/11201.0025ecst, (FMD)
This paper presents a surface-activated Al-Al wafer bonding process for patterned 200 mm wafers that removes the native oxide in an argon plasma and enables high bond quality with accurate alignment at temperatures below 300°C. The study focuses on various factors that influence the final Al-Al bond in terms of contact resistance and shear strength. In addition to temperature, force and time during the actual bonding process, these include steps during the wafer fabrication that affect the Al bonding pads and the wafer bow. In addition, the impact of a post-bond cleaning process on the final bond result is analyzed. This work shows a low temperature Al-Al bonding process with high yield >90%, excellent bond strength >150 MPa and contact resistances in the mΩ range.
(88) Monolithically Integrated O-Band Coherent ROSA Featuring 2D Grating Couplers for Self-Homodyne Intra Data Center Links
P.M. Seiler, G. Georgieva, A. Peczek, M. Oberon, Ch. Mai, St. Lischke, A. Malignaggi, L. Zimmermann
IEEE Photonics Journal 15(3), 6601306 (2023)
DOI: 10.1109/JPHOT.2023.3272476
In this work, we present an O-band dual-polarization coherent receiver optical sub-assembly (cROSA), monolithically integrated in a 0.25 μ m BiCMOS technology. The receiver features 248 nm deep ultra violet compatible 2-dimensional grating couplers (2D-GRCs), and an adaptive polarization controller, suitable for mitigation of local oscillator induced power fading in self-homodyne transmission systems. The cROSA is evaluated in system experiments at 64 GBd quadrature-phase shift-keying. Experimental results are related to grating coupler induced polarization crosstalk through Monte-Carlo simulations. Second generation 2D-GRCs are proposed.
(89) On-Chip Refractive Index Sensors based on Plasmonic TiN Nanohole Ar-Rays
A. Sengül, S. Reiter, W. Han, Ch. Mai, D. Spirito, J. Jose, O. Fursenko, Ch. Wenger, I.A. Fischer
Proc. 10. MikroSystemTechnik Kongress (MST 2023), 336 (2023)
(iCampus II)
This work presents results on the design and fabrication of an integrated refractive index sensor based on plasmonic TiN nanohole arrays (NHAs) in combination with Ge photodetectors. We discuss optical properties of plasmonic TiN NHAs fabricated by using standard industrial processes and compare experimental results with FDTD simulations to identify parameters that boost sensing performance. We, furthermore, present results on combining those NHAs with Ge photodetectors using the ePIC process at the Leibniz Institute for High Performance Microelectronics (IHP), enabling the production of large PIN Ge-diodes on Si wafers. Our results can pave the way towards large-scale production of integrated refractive index sensors for applications ranging from environmental monitoring to point-of-care diagnostics.
(90) Subnanometer Control of the Heteroepitaxial Growth of Multimicrometer-Thick Ge/(Si,Ge) Quantum Cascade Structures
E.T. Simola, M. Montanari, C. Corley-Wiciak, L. Di Gaspare, L. Persichetti, M.H. Zoellner, M.A. Schubert, T. Venanzi, M.C. Trouche, L. Baldassarre, M. Ortolani, G. Nicotra, G. Capellini M. Virgilio, M. De Seta
Physical Review Applied 19(1), 014011 (2023)
DOI: 10.1103/PhysRevApplied.19.014011, (FLASH)
The fabrication of complex low-dimensional quantum devices requires the control of the heteroepitaxial growth at the subnanometer scale. This is particularly challenging when the total thickness of stacked layers of device-active material becomes extremely large and exceeds the multi-μm limit, as in the case of quantum cascade structures. Here, we use the ultrahigh-vacuum chemical vapor deposition technique for the growth of multi-μm-thick stacks of high Ge content strain-balanced Ge/SiGe tunneling heterostructures on Si substrates, designed to serve as the active material in a THz quantum cascade laser. By combining thorough structural investigation with THz spectroscopy absorption experiments and numerical simulations we show that the optimized deposition process can produce state-of-the-art threading dislocation density, ultrasharp interfaces, control of dopant atom position at the nanoscale, and reproducibility within 1% of the layer thickness and composition within the whole multilayer. We show that by using ultrahigh-vacuum chemical vapor deposition one achieves simultaneously a control of the epitaxy down to the sub-nm scale typical of the molecular beam epitaxy, and the high growth rate and technological relevance of chemical vapor deposition. Thus, this technique is a key enabler for the deposition of integrated THz devices and other complex quantum structures based on the Ge/SiGe material system.
(91) Ultralow-Power W-Band Low-Noise Amplifier Design in 130-nm SiGe BiCMOS
K. Smirnova, Ch. Bohn, M. Kaynak, A.Ç. Ulusoy
IEEE Microwave and Wireless Technology Letters (MWTL) 33(8), 1171 (2023)
DOI: 10.1109/LMWT.2023.3279574
This letter presents a power consumption reduction aspect for a 100-GHz low-noise amplifier (LNA). Two designs implemented in 0.13-µm SiGe bipolar complementary metal oxide semiconductor (BiCMOS) technology demonstrate stateof-the-art performance, whereas PDC is reduced from 23.5 mW for the standard version to 3.8 mW for the low-power version. Two circuits exhibit a measured gain of 22 and 16 dB and a noise figure (NF) of 4 and 6.3 dB at 100 GHz. An input 1-dB compression point for the standard and the low-power version is −24.5 and −26.5 dBm, respectively. The occupied integrated circuit (IC) area in both cases is 0.018 and 0.014 mm2 excluding the pads, which proves to be the most compact design among previously reported in the frequency range of interest.
(92) High-Speed Optical Transceiver Integrated Chipset and Module for On-Board VCSEL-based Satellite Optical Interconnects
L. Sourikopoulos, G. Winzer, A. Peczek, M. Inac, P. Ostrovskyy, K. Tittelbach-Helmrich, G. Panic, G. Fischer, L. Zimmermann, Y. Franz, S. Jones, P. Kushner, U. Marvet, A. Lujambio, N. Garcia, D. Poudereux, M. Bodega, J. Barbero, L. Stampoulidis
Proc. 14th International Conference on Space Optics (ICSO 2022), 127774K (2023)
DOI: 10.1117/12.2690846, (SIPhoDiAS)
(93) Germanium Fin Photodiode with 3dB-Bandwidth >110 GHz and High L-Band Responsivity
D. Steckler, St. Lischke, A. Kroh, A. Peczek, G. Georgieva, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), ThA2 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141946, (PEARLS)
(94) Germanium Fin Photodiode with 3dB-Bandwidth >110 GHz and High L-Band Responsivity
D. Steckler, St. Lischke, A. Kroh, A. Peczek, G. Georgieva, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), ThA2 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141946, (DFG ULTRA 2)
(95) Germanium Fin Photodiode with 3dB-Bandwidth >110 GHz and High L-Band Responsivity
D. Steckler, St. Lischke, A. Kroh, A. Peczek, G. Georgieva, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), ThA2 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141946, (DFG EPIC-Sense 2)
(96) Investigation of Doping Processes to Achieve Highly Doped Czochralski Germanium Ingots
A. Subramanian, N. Abrosimov, A. Gybin, C. Guguschev, U. Juda, A. Fiedler, F. Bärwolf, I. Costina, A. Kwasniewski, A. Dittmar, R. Radhakrishnan Sumathi
Journal of Electronic Materials 52, 5178 (2023)
DOI: 10.1007/s11664-023-10534-3
Highly doped germanium (HD-Ge) is a promising material for mid-infrared detectors, bio-sensors, and other devices. Bulk crystals with a doping concentration higher than 1018 cm−3 would be desirable for such device fabrication technologies. Hence, an effective method needs to be developed to dope germanium (Ge) ingots in the Czochralski (Cz) growth process. In this study, a total of 5 ingots were grown by the Cz technique: two undoped Ge ingots as a reference and three doped ingots with 1018, 1019, and 1020 atoms/cm3 respectively. To obtain a uniform p-type doping concentration along the crystal, co-doping of boron-gallium (B-Ga) via the Ge feed material was also attempted. Both B and Ga are p-type dopants, but with a large difference in their segregation behavior (contrary segregation profile) in Ge, and hence it is expected that the incorporation of dopants in the crystal would be uniform along the crystal length. The distribution of the dopants followed the Scheil-predicted profile. The etch pit density maps of the grown crystals showed an average dislocation density in the order of 105 cm−2. No increase in the overall etch pit count was observed with increasing dopant concentration in the crystal. The grown highly doped Ge crystals have a good structural quality as confirmed by x-ray diffraction rocking curve measurements.
(97) Unintentional P-Type Conductivity in Intrinsic Ge-Rich SiGe/Ge Heterostructures Grown on Si(001)
H. Tetzner, W. Seifert, O. Skibitzki, Y. Yamamoto, M. Lisker, M.M. Mirza, I.A. Fischer, D.J. Paul, M. De Seta, G. Capellini
Applied Physics Letters 122(24), 243503 (2023)
DOI: 10.1063/5.0152962, (FLASH)
In this work, we investigate the effective background charge density in intrinsic Si0.06Ge0.94/Ge plastically-relaxed heterostructures deposited on Si(001). Hall effect measurements and capacitance-voltage profiling reveal a p-type conductivity in the nominally intrinsic layer with a hole concentration in the mid 1015 cm-3 range at temperatures between 50 K and 200 K. Owing to a carrier freeze out below 50 K observed by Hall, we attribute the origin of these carriers to the ionization of shallow acceptor-like defect states above the valence band. In addition, one dominant hole trap located at mid-gap position is found by deep level transient spectroscopy. Carrier trapping kinetics measurements can be interpreted as due to a combination of point defects, likely trapped in the strain field of extended defects, i.e. the threading dislocation themselves.
(98) Production of Modified Nucleosides in a Continuous Enzyme Membrane Reactor
I. Thiele, H. Yehia, N. Krausch, M. Birkholz, M.N. Cruz Bournazou, A. Boing Sitanggang, M. Kraume, P. Neubauer, A. Kurreck
International Journal of Molecular Sciences (IJMS) 24(7), 6081 (2023)
DOI: 10.3390/ijms24076081, (Bioelectronics)
Nucleoside analogues are important compounds for the treatment of viral infections or 20 cancer. While (chemo-)enzymatic synthesis is a valuable alternative to traditional chemical methods, the feasibility of such processes is lowered by the high production cost of the biocatalyst. As continuous enzyme membrane reactors (EMR) allow the use of the biocatalysts until its full inactivation, they offer a valuable alternative to batch enzymatic reactions with freely dissolved enzyme. In contrast to enzyme immobilization approaches losses in enzyme activity are avoided. Therefore, we validated the applicability of EMRs for the synthesis of natural and dihalogenated nucleosides using one-pot transglycosylation reactions. Over a period of 55 days, 2‘-deoxyadenosine was produced continuously with a product yield > 90 %. The dihalogenated nucleoside analogues 2,6-di-chloropurine-2‘-deoxyribonucleoside and 6-chloro-2-fluoro-2‘-deoxyribonucleoside were also produced with high conversion but for shorter operation times of 14 and 5.5 days, respectively. The EMR performed with specific productivities comparable to batch reactions. However, in the EMR 220, 40 and 9 times more product per enzymatic unit was produced for 2‘-deoxyadenosine, 2,6-dichloropurine-2‘-deoxyribonucleoside and 6-chloro-2-fluoro-2‘-deoxyribonucleoside, respectively. The application of the EMR using freely dissolved enzymes facilitates a continuous process with integrated biocatalyst separation which reduces the overall cost of the biocatalyst and enhances the downstream processing of nucleoside production.
(99) One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing
M. Uhlmann, E. Perez-Bosch Quesada, M. Fritscher, E. Perez, M.A. Schubert, M. Reichenbach, P. Ostrovskyy, Ch. Wenger, G. Kahmen
Proc. 21st IEEE International New Circuits And Systems Conference (NEWCAS 2023), (2023)
DOI: 10.1109/NEWCAS57931.2023.10198073, (Neutronics)
(100) Verified Value Chains, Innovation and Competition
A. Weber, S. Guilley, R. Rathfelder, M. Stöttinger, C. Lüth, M. Malenko, T. Grawunder, S. Reith, A. Puccetti, J.-P. Seifert, N. Herfurth, H. Sankowski, G. Heiser
Proc. IEEE International Conference on Cyber Security and Resilience (CSR 2023), 470 (2023)
DOI: 10.1109/CSR57506.2023.10224911, (VE-HEP)
(101) Three-Dimensional Self-Ordered Multilayered Ge Nanodots on SiGe
W.-C. Wen, M.A. Schubert, M.H. Zoellner, B. Tillack, Y. Yamamoto
ECS Journal of Solid State Science and Technology 12(5), 055001 (2023)
DOI: 10.1149/2162-8777/acce06
Three-dimensional (3D) self-ordered Ge nanodots in cyclic epitaxial growth of Ge/SiGe superlattice on Si0.4Ge0.6 virtual substrate (VS) were fabricated by reduced pressure chemical vapor deposition. The Ge nanodots were formed by Stranski-Krastanov mechanism. By the Ge/SiGe superlattice deposition, dot-on-dot alignment and <100> alignment were obtained toward the vertical and lateral direction, respectively. Facets and growth mechanism of Ge nanodots and key factors of alignment were studied. Two types of Ge nanodots were observed, diamond-like nanodots composed of {105} and dome-like nanodots composed of {113} and {519} or {15 3 23} facets. The Ge nanodots tend to grow directly above the nanodots of the previous period as these regions show a relatively higher tensile strain induced by the buried nanodots. Thus, this dot-on-dot alignment is sensitive to the SiGe spacer thickness, and it degrades when the SiGe spacer becomes thicker. The Ge content of the SiGe spacer ranging from 45 to 52% affects the lateral alignment and the size uniformity of Ge nanodots because of the strain balance between the superlattice and the VS. By maintaining the strain balance, ordering of the 3D aligned Ge nanodots can be improved.
(102) Vertical Alignment Control of Self-Ordered Multilayered Ge Nanodots on SiGe
W.-C. Wen, M.A. Schubert, B. Tillack, Y. Yamamoto
Japanese Journal of Applied Physics 62(SC), SC1057 (2023)
DOI: 10.35848/1347-4065/acb05e
Self-ordered multilayered Ge nanodots with SiGe spacers on a Si0.4Ge0.6 virtual substrate are fabricated using reduced-pressure chemical vapor deposition, and the mechanism of vertical ordering is investigated. The process conditions of Ge and SiGe layer deposition are H2-GeH4 at 550 °C and H2-SiH4-GeH4 at 500 °C–550 °C, respectively. By depositing the SiGe at 550 °C or increasing Ge content, the SiGe surface becomes smooth, resulting in vertically aligned Ge nanodots to reduce strain energy. Ge nanodots prefer to grow on the nanodot where the SiGe is relatively tensile strained due to the buried Ge nanodot underneath. By depositing at 500 °C and lowering Ge content, checkerboard-like surface forms, and the following Ge nanodots grow at staggered positions to reduce surface energy. The Ge nanodots are laterally aligned along the elastically soft 〈100〉 direction without pre-structuring resulting from the strain distribution.
(103) Influence of Strain on Multilayer Ge Nanodot Formation on SiGe Virtual Substrate
W.-C. Wen, B. Tillack, Y. Yamamoto
Proc. 55th International Conference on Solid State Device and Materials (SSDM 2023), 519 (2023)
(104) Fabrication and Characteriyation of Germanium n-MOS and n-MOSFET with Thermally Oxidized Yttrium Gate Insulator: Formation of Underlaying Germanium Oxide and its Electrical Characteristics
W.-C. Wen, D. Wang, H. Nakashima, K. Yamamoto
Materials Science in Semiconductor Processing 162, 107504 (2023)
DOI: 10.1016/j.mssp.2023.107504
A high-quality insulating film on germanium is essential for germanium applications. In this study, we oxidized metal yttrium at 500–550 ◦C to generate an yttrium oxide (Y-oxide) layer on germanium. According to transmission electron microscopy images, Y-oxide comprised three layers, which were Y2O3, YGeO3, and GeOx from the top side. n-Type metal-oxide-semiconductor (n-MOS) capacitors and n-type MOS field-effect transistors (n-MOSFETs) with the Y-oxide gate insulator showed typical electrical characteristics. The n-MOS capacitor with the Y-oxide gate insulator had a lower interface state density (Dit) and border trap density (Nbt) than the n-MOS capacitor with a thermally oxidized GeOx insulator, suggesting that defects were terminated by Y atoms in the GeOx layer and GeOx/Ge interface. In contrast, the Dit–energy distribution and Nbt temperature dependence of the Y-oxide gate insulator were similar to those of the GeOx gate insulator, indicating that the defect signals originated in GeOx underlying YGeO3. The structural analysis showed that the temperature of metal yttrium oxidation affected only the GeOx thickness. Therefore, adjusting the conditions of metal yttrium oxidation may produce Y-oxidized gate stacks with a thinner GeOx layer or even direct contact of YGeO3 and Ge, which may result in different Dit values, Nbt values, and Nbt–temperature trends.
(105) Heterointegration of mm-Wave InP-HBT Power Amplifier Chiplets on SiGe-BiCMOS Chip
H. Yacoub, M. Rausch, C. Stölmacker, R. Dörner, M. Hossain, I. Ostermay, T. Moule, M. Wietstruck, S. Knigge, O. Krüger, W. Heinrich
Proc. 26th European Microwave Week (EuMW 2023), 169 (2023)
DOI: 10.23919/EuMIC58042.2023.10289026, (T-KOS)
(106) Heteroepitaxy of Group IV Materials for Future Device Application
Y. Yamamoto, W.-C. Wen, B. Tillack
Japanese Journal of Applied Physics 62(SC), SC0805 (2023)
DOI: 10.35848/1347-4065/acb1a6
Heteroepitxy of group IV materials (Si, SiGe, and Ge) has great potential for boosting Si-based novel device performance because of the possibility for strain, band gap/Fermi-level engineering, and applying emerging artificial materials such as a superlattice (SL) and nanodots. In order to control group IV heteroepitaxy processes, strain, interface, and surface energies are very essential parameters. They affect dislocation formation, interface steepness, reflow of deposited layers, and also surface reaction itself during the growth. Therefore, process control and crystallinity management of SiGe heteroepitaxy are difficult especially in the case of high Ge concentrations. In this paper, we review our results of abrupt SiGe/Si interface fabrication by introducing C-delta layers and the influence of strain on the surface reaction of SiGe. Three-dimensional self-ordered SiGe and Ge nanodot fabrication by proactively using strain and surface energies by depositing SiGe/Si and Ge/SiGe SL are also reviewed.
(107) High Crystallinity Ge Growth on Si (111) and Si (110) by Using Reduced Pressure Chemical Vapor Deposition
Y. Yamamoto, W.-C. Wen, M.A. Schubert, C. Corley-Wiciak, B. Tillack
ECS Journal of Solid State Science and Technology 12(2), 023014 (2023)
DOI: 10.1149/2162-8777/acbb9d
A method for high quality epitaxial growth of Ge on Si (111) and Si (110) is investigated by reduced pressure chemical vapor deposition. Two step Ge epitaxy (low temperature Ge seed and high temperature main Ge growth) with several cycles of annealing by interrupting the Ge growth (cyclic annealing) is performed. In the case of Ge seed layer growth below 350 °C for (111) and 400 °C for (110) orientation, huge surface roughening due to too high dislocation density is observed after the following annealing step. For both crystal orientations, a high crystallinity Ge seed layer is realized by combination of 450 °C growth with 800 °C annealing. Once the high-quality Ge seed layer is deposited, high crystal quality Ge can be grown at 600 °C on the seed layer for both crystal orientations. For the 5 µm thick Ge layer deposited with the cyclic annealing process at 800 °C, a Si diffusion length of ~400 nm from the interface, RMS roughness below 0.5 nm and threading dislocation density of 5×106 cm-2 are achieved for both (111) and (110) substrates
(108) Thin and Locally Dislocation-Free SiGe Virtual Substrate Fabrication by Lateral Selective Epitaxy
Y. Yamamoto, W.-C. Wen, M.A. Schubert, A.A. Corley-Wiciak, S. Sugawa, Y. Ito, R. Yokogawa, A. Ogura, B. Tillack
Proc. 55th International Conference on Solid State Devices and Materials (SSDM 2023), 527 (2023)
(109) Group-IV Heteroepitaxy for Novel and Emerging Device Applications
Y. Yamamoto, W-C. Wen, B. Tillack
Proc. 13th International WorkShop on New Group IV Semiconductor Nanoelectronics (2023), abstr. book 45 (2023)
(110) Redox-Based Bi-Layer Metal Oxide Memristive Devices
F. Zahari, S. Park, M.K. Mahadevaiah, Ch. Wenger, H. Kohlstedt, M. Ziegler
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Redox-Based Bi-Layer Metal Oxide Memristive Devices, Springer Series on Bio- and Neurosystems (SSBN) 16, Springer, 87 (2023)
DOI: 10.1007/978-3-031-36705-2_3, (NeuroMem)
(111) 20 ps Time Resolution with a Fully-Efficient Monolithic Silicon Pixel Detector without Internal Gain Layer
S. Zambito, M. Milanesio, T. Moretti, L. Paolozzi, M. Munker, R. Cardella, T. Kugathasan, F. Martinelli, A. Picardi, M. Elviretti, H. Rücker, A. Trusch, F. Cadoux, R. Cardarelli, S. Débieux, Y. Favre, C.A. Fenoglio, D. Ferrere, S. Gonzalez-Sevilla, L. Iodice, R. Kotitsa, C. Magliocca, M. Nessi, A. Pizarro-Medina, J. Sabater lglesias, J. Saidi, M.V. Barreto Pinto, G. Iacobucci
Journal of Instrumentation 18, P03047 (2023)
DOI: 10.1088/1748-0221/18/03/P03047
A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 μm thick epilayer of 350 Ωcm resistivity were used to produce a fully depleted sensor. Laboratory and testbeam measurements of the analog channels present in the pixel matrix show that the sensor has a 130 V wide bias-voltage operation plateau at which the efficiency is 99.8%. Although this prototype does not include an internal gain layer, the design optimised for timing of the sensor and the front-end electronics provides a time resolutions of 20 ps.
(112) Characterization of a D-Band Electric-Inductive-Capacitive Metamaterial-Based Transmission Line Phase Shifter
G.M. Zampa, A. Sonara, D. Mencarelli, L. Pierantoni, H.J. Christopher, Z. Cao, R. Al Hadi, M.-C.F. Chang, M. Kaynak
Proc. IEEE MTT-S International Microwave Symposium (IMS 2023), 721 (2023)
DOI: 10.1109/IMS37964.2023.10187973, (SMARTWAVE)
(113) Toward 2D Grating Coupler Enabled O-Band Coherent Links based on SiGe Photonic Electronic Technology
L. Zimmermann, P.M. Seiler, Ch. Mai, G. Georgieva
Japanese Journal of Applied Physics 62(SC), SC0807 (2023)
DOI: 10.35848/1347-4065/acb4fe, (DFG EPIC-Sense 2)
Coherent techniques for short reach intra-datacenter optical interconnects are currently intensely discussed. This article reports progress on previous work that analyzed the benefits of switching from C- to O-band optics with regard to digital signal processing. Here we study the feasibility of adapting a coherent approach to an established datacenter interconnect technology (PSM4). This PSM4-like implementation brings about the benefit of much improved resilience to laser drift, thus reducing or eliminating the need for a temperature stabilized laser, which is typically assumed a requirement for coherent transceivers. The analysis rests on simulation parameters derived in part from previous experimental realizations of coherent receivers in SiGe photonic BiCMOS technology. In addition, we make use of recent results regarding the optimization of O-band 2D grating couplers with respect to efficiency and low polarization dependence over a 20nm wavelength window. We identify such couplers as enabling building blocks for coherent PSM4-like implementations.
(114) Toward 2D Grating Coupler Enabled O-Band Coherent Links based on SiGe Photonic Electronic Technology
L. Zimmermann, P.M. Seiler, Ch. Mai, G. Georgieva
Japanese Journal of Applied Physics 62(SC), SC0807 (2023)
DOI: 10.35848/1347-4065/acb4fe, (PEARLS)
Coherent techniques for short reach intra-datacenter optical interconnects are currently intensely discussed. This article reports progress on previous work that analyzed the benefits of switching from C- to O-band optics with regard to digital signal processing. Here we study the feasibility of adapting a coherent approach to an established datacenter interconnect technology (PSM4). This PSM4-like implementation brings about the benefit of much improved resilience to laser drift, thus reducing or eliminating the need for a temperature stabilized laser, which is typically assumed a requirement for coherent transceivers. The analysis rests on simulation parameters derived in part from previous experimental realizations of coherent receivers in SiGe photonic BiCMOS technology. In addition, we make use of recent results regarding the optimization of O-band 2D grating couplers with respect to efficiency and low polarization dependence over a 20nm wavelength window. We identify such couplers as enabling building blocks for coherent PSM4-like implementations.
(115) Toward 2D Grating Coupler Enabled O-Band Coherent Links based on SiGe Photonic Electronic Technology
L. Zimmermann, P.M. Seiler, Ch. Mai, G. Georgieva
Japanese Journal of Applied Physics 62(SC), SC0807 (2023)
DOI: 10.35848/1347-4065/acb4fe, (DFG ULTRA 2)
Coherent techniques for short reach intra-datacenter optical interconnects are currently intensely discussed. This article reports progress on previous work that analyzed the benefits of switching from C- to O-band optics with regard to digital signal processing. Here we study the feasibility of adapting a coherent approach to an established datacenter interconnect technology (PSM4). This PSM4-like implementation brings about the benefit of much improved resilience to laser drift, thus reducing or eliminating the need for a temperature stabilized laser, which is typically assumed a requirement for coherent transceivers. The analysis rests on simulation parameters derived in part from previous experimental realizations of coherent receivers in SiGe photonic BiCMOS technology. In addition, we make use of recent results regarding the optimization of O-band 2D grating couplers with respect to efficiency and low polarization dependence over a 20nm wavelength window. We identify such couplers as enabling building blocks for coherent PSM4-like implementations.
F. Akhtar, J. Dabrowski, R. Lukose, Ch. Wenger, M.Lukosius
ACS Applied Materials & Interfaces 15(30), 36966 (2023)
DOI: 10.1021/acsami.3c05860, (2D-EPL)
For the fabrication of modern graphene devices, uniform growth of high-quality monolayer graphene on wafer scale is important. This work reports on the growth of large-scale graphene on semiconducting 8 inch Ge(110)/Si wafers by chemical vapor deposition and a DFT analysis of the growth process. Good graphene quality is indicated by the small FWHM (32 cm–1) of the Raman 2D band, low intensity ratio of the Raman D and G bands (0.06), and homogeneous SEM images and is confirmed by Hall measurements: high mobility (2700 cm2/Vs) and low sheet resistance (800 Ω/sq). In contrast to Ge(001), Ge(110) does not undergo faceting during the growth. We argue that Ge(001) roughens as a result of vacancy accumulation at pinned steps, easy motion of bonded graphene edges across (107) facets, and low energy cost to expand Ge area by surface vicinals, but on Ge(110), these mechanisms do not work due to different surface geometries and complex reconstruction.
(2) Towards Heterogeneous Integration of InP on Si via Micro Transfer Printing by Direct Adhesion
K. Anand, P. Steglich, J. Kreißl, L. Zimmermann, A. Mai
Proc. 10. MikroSystemTechnik Kongress (MST 2023), 430 (2023)
(PEARLS)
(3) Lateral Selective SiGe Growth for Local Dislocation-Free SiGe-on-Insulator Virtual Substrate Fabrication
K. Anand, M.A. Schubert, D. Spirito, A.A. Corley-Wiciak, C. Corley-Wiciak, W.M. Klesse, A. Mai, B. Tillack, Y. Yamamoto
ECS Journal of Solid State Science and Technology 12(2), 024003 (2023)
DOI: 10.1149/2162-8777/acb739
Dislocation-free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around ~1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850°C from side of SiO2 / Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ~40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ~0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ~1.4% along <010> direction, which is higher compared to that along <110> direction, is observed. The tensile strain is induced from both [110] and [-110] directions. Threading dislocations in the SiGe are located only ~400 nm from Si pillar and stacking faults are running towards <110> directions, resulting in wide dislocation-free area formation in SiGe along <010> due to horizontal aspect ratio trapping.
(4) A D-Band to J-Band Low-Noise Amplifier with High Gain-Bandwidth Product in an Advanced 130 nm SiGe BiCMOS Technology
M. Andree, J. Grzyb, B. Heinemann, U. Pfeiffer
Proc. IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2023), 137 (2023)
DOI: 10.1109/RFIC54547.2023.10186116
(5) Messverfahren zur Kontrolle tiefer Siliziumstrukturen für die 3D-Chip-Integration
J. Bauer, F. Villasmunta, F. Heinrich, C. Villinger, J. Reck, S. Peters, A. Treffer, Ch. Kuhnt, St. Marschmeyer, O. Fursenko, P. Steglich, A. Mai, S. Schrader, M. Regehly
Proc. 124. Jahrestagung der Deutschen Gesellschaft für angewandte Optik e.V. (DGaO 2023), B35 (2023)
(6) 200–330-GHz Substrate-Integrated Waveguide in BEOL of a SiGe BiCMOS Process
A. Bhutani, M. Kaynak, E. Bekker, T. Zwick
IEEE Microwave and Wireless Technology Letters (MWTL)
DOI: 10.1109/LMWT.2023.3283304
This letter shows the first 200–330-GHz substrate-integrated waveguide (SIW) to a grounded coplanar waveguide (GCPW) transition realized in backend-of-line (BEOL) of a SiGe BiCMOS process. The transition uses two rectangular slots and a GCPW stub, which convert a quasi-TE10 to quasi-TEM mode with the highest operating frequency of up to 330 GHz, largest operation bandwidth of 49%, and smallest transition length of 99μm for a silicon process-based SIW transition demonstrated to date. A back-to-back configuration with ground–signal–ground (GSG) pads on either end enables probe-based S-parameter measurement. The influence of the GSG pads is de-embedded by measuring a 50- Ω GCPW connected by a pair of the GSG pads. A comparison of the measured and de-embedded S-parameters with the electromagnetic simulation results show that the SIW–GCPW transition operates from 200 to 330 GHz (49% bandwidth) with an average insertion loss of ≈1.2 dB per transition.
(7) Implantable Microelectronics
M. Birkholz
Bioelectronics: Materials, Technologies, and Emerging Applications, 1st Edition, Editors: A. Kumar, R.K. Gupta, Chapter 21. Implantable Microelectronics, CRC Press 341 (2023)
DOI: 10.1201/9781003263265-21, (Bioelectronics)
(8) Sustainable Design of Online Biosensors
M. Birkholz, M. Kögler
Proc. 4th European Biosensor Symposium (EBS 2023), 88 (2023)
(Bioelectronics)
(9) A 100 GBd PAM-4 Combiner and Driver in SiGe BiCMOS
C. Bohn, M. Kaynak, T. Zwick, A.C. Ulusoy
IEEE Microwave and Wireless Technology Letters (MWTL) 33(9), 1337 (2023)
DOI: 10.1109/LMWT.2023.3293040
In this letter, we present an analog PAM-4 combiner and driver circuit based on a current steering output stage designed in a 130 nm SiGe BiCMOS technology. The circuit features an on-chip active balun with more than 67 GHz bandwidth. The output stage supports an adjustable PAM-4 level spacing. It consumes 315 mW and delivers 2 Vpp,diff in a 100 Ω load. Operation of up to 100 GBd has been verified by measured eye diagrams.
(10) Fabrication of Gate Electrodes for Scalable Quantum Computing using CMOS Industry Compatible E-Beam Lithography and Numerical Simulation of the Resulting Quantum Device
V. Brackmann, M. Neul, M. Friedrich, W. Langheinrich, M. Simon, S. Pregl, A. Demmler, N. Hanisch, M. Lederer, K. Zimmermann, J. Klos, F. Reichmann, Y. Yamamoto, M. Wislicenus, C. Dahl, L. Schreiber, H. Bluhm, B. Lilienthal-Uhlig
Proc. 38th Mask and Lithography Conference (ELMC 2023), 12802, 128020F (2023)
DOI: 10.1117/12.2675943, (QUASAR)
(11) Progress on SiGeSn Light Emitters and Detectors on Si
D. Buca, T. Liu, O. Concepción, M. El Kurdi, Y. Yamamoto, G. Capellini, G Isella, D. Grützmacher
Proc. 13th International WorkShop on New Group IV Semiconductor Nanoelectronics (2023), abstr. book 9 (2023)
(12) In-Orbit VNIR Sensor Quality Validation
J. Buschek, A. Eckardt, K. Manthey, K. Sengebusch, O. Schrey, D. Piechaczek, G. Kahmen
Proc. Sensors, Systems, and Next-Generation Satellites XXVII, 12729, 1272913 (2023)
DOI: 10.1117/12.2680166
(13) Characterization and Optimization of the Heat Dissipation Capability of a Chip-on-Board Package using Finite Element Methods
Z. Cao, M. Stocchi, M. Wietstruck, T. Mausolf, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 13(3), 346 (2023)
DOI: 10.1109/TCPMT.2023.3259199, (FLEXCOM)
The present study endeavors to investigate the thermal dissipation capability of a chip-on-board package by means of a comprehensive experimental and numerical analysis. For this purpose, a BiCMOS chip is designed and fabricated in conjunction with three different printed circuit board (PCB) configurations, including a single-sided board, a thermal via board, and a copper frame board. Transient thermal measurements are carried out on all three packages, and the results are subsequently transformed into cumulative structure functions. Then the finite element models are established for each package configuration, and their validity is confirmed through comparison with the experimental structure functions. The models are then characterized in accordance with the Joint Electron Device Engineering Council (JEDEC) 38-set boundary conditions, followed by a series of optimizations targeted toward the PCB, including the board stack-up and the board sizes. Parametric studies are performed to quantitatively assess the impact of these parameters on the thermal performance. Finally, the present study provides a comprehensive discussion of the optimal application scenarios for each board configuration, with a view to achieving good thermal performance. The findings of this study will contribute to the development of more thermally effective chip-on-board packages for high-performance electronic systems.
(14) D-Band Flip-Chip Packaging with Wafer-Level Cu-Pillar Bumps
Z. Cao, M. Stocchi, Ch. Wipf, J. Lehmann, L. Li, S. Tolunay Wipf, M. Wietstruck, C. Carta, M. Kaynak
Proc. 32th IEEE Conference on Electrical Performance on Electronic Packaging and Systems (EPEPS 2023), (2023)
DOI: 10.1109/EPEPS58208.2023.10314877, (FLEXCOM)
(15) Characterization and Optimization of the Heat Dissipation Capability of a Chip-on-Board Package using Finite Element Methods
Z. Cao, M. Stocchi, M. Wietstruck, T. Mausolf, C. Carta, M. Kaynak
IEEE Transactions on Components, Packaging and Manufacturing Technology 13(3), 346 (2023)
DOI: 10.1109/TCPMT.2023.3259199, (Hytech)
The present study endeavors to investigate the thermal dissipation capability of a chip-on-board package by means of a comprehensive experimental and numerical analysis. For this purpose, a BiCMOS chip is designed and fabricated in conjunction with three different printed circuit board (PCB) configurations, including a single-sided board, a thermal via board, and a copper frame board. Transient thermal measurements are carried out on all three packages, and the results are subsequently transformed into cumulative structure functions. Then the finite element models are established for each package configuration, and their validity is confirmed through comparison with the experimental structure functions. The models are then characterized in accordance with the Joint Electron Device Engineering Council (JEDEC) 38-set boundary conditions, followed by a series of optimizations targeted toward the PCB, including the board stack-up and the board sizes. Parametric studies are performed to quantitatively assess the impact of these parameters on the thermal performance. Finally, the present study provides a comprehensive discussion of the optimal application scenarios for each board configuration, with a view to achieving good thermal performance. The findings of this study will contribute to the development of more thermally effective chip-on-board packages for high-performance electronic systems.
(16) An Advanced Finite Element Model of the Cu Pillar Solder Reflow Assembly
Z. Cao, B. Pekkolay, A. Okur, B. Heusdens, C. Carta, M. Kaynak
Proc. 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2023), (2023)
DOI: 10.1109/EuroSimE56861.2023.10100808, (FLEXCOM)
(17) An Advanced Finite Element Model of the Cu Pillar Solder Reflow Assembly
Z. Cao, B. Pekkolay, A. Okur, B. Heusdens, C. Carta, M. Kaynak
Proc. 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2023), (2023)
DOI: 10.1109/EuroSimE56861.2023.10100808, (SMARTWAVE)
(18) Study on the Metal-Graphene Contact Resistance Achieved with One-Dimensional Contact Architecture
D. Capista, R. Lukose, F. Majnoon, M. Lisker, Ch. Wenger, M. Lukosius
Proc. IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), 118 (2023)
(Graphen)
(19) Study on the Metal-Graphene Contact Resistance Achieved with One-Dimensional Contact Architecture
D. Capista, R. Lukose, F. Majnoon, M. Lisker, Ch. Wenger, M. Lukosius
Proc. IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), 118 (2023)
(2D-EPL)
(20) A Wideband W-Band Frequency Tripler with a Novel Mode-Selective Filter for High Harmonic Rejection
A. Chandra-Prabhu, J. Grzyb, P. Hillger, B. Heinemann, H. Rücker, U. Pfeiffer
Proc. 18th European Microwave Integrated Circuits Conference (EuMIC 2023), 197 (2023)
DOI: 10.23919/EuMIC58042.2023.10288850, (SG13G3)
(21) Structural and Electrical Characterization of Cerium-Tin Oxide Heterolayers for Hydrogen Sensing
C.A. Chavarin, I. Costina, Ch. Wenger, M. Ratzke,C. Morales Sanchez, Y. Kosto, I. Flege, I.A. Fischer
Proc. 10. MikroSystemTechnik Kongress (MST 2023), 1 (2023)
(iCampus II)
(22) Isothermal Heteroepitaxy of Ge1-xSnx Structures for Electronic and Photonic Applications
O. Concepción, N.B. Søgaard, J.-H. Bae, Y. Yamamoto, A.T. Tiedemann, Z. Ikonic, G. Capellini, Q.T. Zhao, D. Grützmacher, D. Buca
ACS Applied Electronic Materials 5(4), 2268 (2023)
DOI: 10.1021/acsaelm.3c00112, (DFG GeSn Laser)
Epitaxy of semiconductor-based quantum well structures is a challenging task since it requires precise control of the deposition at the submonolayer scale. In the case of Ge1–xSnx alloys, the growth is particularly demanding since the lattice strain and the process temperature greatly impact the composition of the epitaxial layers. In this paper, the realization of high-quality pseudomorphic Ge1–xSnx layers with Sn content ranging from 6 at. % up to 15 at. % using isothermal processes in an industry-compatible reduced-pressure chemical vapor deposition reactor is presented. The epitaxy of Ge1–xSnx layers has been optimized for a standard process offering a high Sn concentration at a large process window. By varying the N2 carrier gas flow, isothermal heterostructure designs suitable for quantum transport and spintronic devices are obtained.
(23) Si-Ge-Sn Heterostructures Grown by Chemical Vapor Deposition for Electronic and Photonic Devices
O. Concepción, Y. Yamamoto, G. Capellini, M. El-Kurdi, Q.-T. Zhao, D. Buca, D. Grützmacher
Proc. 55th International Conference on Solid State Devices and Materials (SSDM 2023), 517 (2023)
(24) Lattice Deformation at the Submicron Scale: X-Ray Nanobeam Measurements of Elastic Strain in Electron Shuttling Devices
C. Corley-Wiciak, M.H. Zoellner, I. Zaitsev, K. Anand, E. Zatterin, Y. Yamamoto, A.A. Corley-Wiciak, F. Reichmann, W. Langheinrich, L.R. Schreiber, C.L. Manganelli, M. Virgilio, C. Richter, G. Capellini
Physical Review Applied 20(2), 0247056 (2023)
DOI: 10.1103/PhysRevApplied.20.024056, (QLSI)
The lattice strain induced by metal electrodes can impair the functionality of advanced quantum devices operating with electron or hole spins. Here we investigate the deformation induced by CMOS-manufactured titanium nitride electrodes on the lattice of a buried, 10 nm-thick Si/SiGe Quantum Well by means of nanobeam Scanning X-ray Diffraction Microscopy. We were able to measure TiN electrode-induced local modulations of the strain tensor components in the range of 2 – 8 × 10−4 with 50 nm lateral resolution. We have evaluated that these strain fluctuations are reflected into local modulations of the potential of the conduction band minimum larger than 2 meV, which is close to the orbital energy of an electrostatic quantum dot. We observe that the sign of the strain modulations at a given depth of the quantum well layer depends on the lateral dimensions of the electrodes. Since our work explores the impact of device geometry on the strain-induced energy landscape, it enables further optimization of the design of scaled CMOS-processed quantum devices.
(25) Lattice Deformation at the Submicron Scale: X-Ray Nanobeam Measurements of Elastic Strain in Electron Shuttling Devices
C. Corley-Wiciak, M.H. Zoellner, I. Zaitsev, K. Anand, E. Zatterin, Y. Yamamoto, A.A. Corley-Wiciak, F. Reichmann, W. Langheinrich, L.R. Schreiber, C.L. Manganelli, M. Virgilio, C. Richter, G. Capellini
Physical Review Applied 20(2), 0247056 (2023)
DOI: 10.1103/PhysRevApplied.20.024056, (SiGeQuant)
The lattice strain induced by metal electrodes can impair the functionality of advanced quantum devices operating with electron or hole spins. Here we investigate the deformation induced by CMOS-manufactured titanium nitride electrodes on the lattice of a buried, 10 nm-thick Si/SiGe Quantum Well by means of nanobeam Scanning X-ray Diffraction Microscopy. We were able to measure TiN electrode-induced local modulations of the strain tensor components in the range of 2 – 8 × 10−4 with 50 nm lateral resolution. We have evaluated that these strain fluctuations are reflected into local modulations of the potential of the conduction band minimum larger than 2 meV, which is close to the orbital energy of an electrostatic quantum dot. We observe that the sign of the strain modulations at a given depth of the quantum well layer depends on the lateral dimensions of the electrodes. Since our work explores the impact of device geometry on the strain-induced energy landscape, it enables further optimization of the design of scaled CMOS-processed quantum devices.
(26) Lattice Deformation at the Submicron Scale: X-Ray Nanobeam Measurements of Elastic Strain in Electron Shuttling Devices
C. Corley-Wiciak, M.H. Zoellner, I. Zaitsev, K. Anand, E. Zatterin, Y. Yamamoto, A.A. Corley-Wiciak, F. Reichmann, W. Langheinrich, L.R. Schreiber, C.L. Manganelli, M. Virgilio, C. Richter, G. Capellini
Physical Review Applied 20(2), 0247056 (2023)
DOI: 10.1103/PhysRevApplied.20.024056, (QUASAR)
The lattice strain induced by metal electrodes can impair the functionality of advanced quantum devices operating with electron or hole spins. Here we investigate the deformation induced by CMOS-manufactured titanium nitride electrodes on the lattice of a buried, 10 nm-thick Si/SiGe Quantum Well by means of nanobeam Scanning X-ray Diffraction Microscopy. We were able to measure TiN electrode-induced local modulations of the strain tensor components in the range of 2 – 8 × 10−4 with 50 nm lateral resolution. We have evaluated that these strain fluctuations are reflected into local modulations of the potential of the conduction band minimum larger than 2 meV, which is close to the orbital energy of an electrostatic quantum dot. We observe that the sign of the strain modulations at a given depth of the quantum well layer depends on the lateral dimensions of the electrodes. Since our work explores the impact of device geometry on the strain-induced energy landscape, it enables further optimization of the design of scaled CMOS-processed quantum devices.
(27) Nanoscale Mapping of the 3D Strain Tensor in a Germanium Quantum Well Hosting a Functional Spin Qubit Device
C. Corley-Wiciak, C. Richter, M.H. Zoellner, I. Zaitev, C.L. Manganelli, E. Zatterin, T.U. Schülli, A.A. Corley-Wiciak, J. Katzer, F. Reichmann, W.M. Klesse, N.W. Hendrickx, A. Sammak, M. Veldhorst, G. Scappucci, M. Virgilio, G. Capellini
ACS Applied Materials & Interfaces 15(2), 3119 (2023)
DOI: 10.1021/acsami.2c17395, (QUASAR)
A strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by Synchrotron-based Scanning X-ray Diffraction Microscopy to determine all its Bravais lattice parameters.
This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approx. 50 nm. Two different spatial scales governing the strain field fluctuations in the proximity of the qubits are observed over < 100 nm and > 1μm respectively. The short-ranged fluctuations have a typical bandwidth of 2 · 10−4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations it is estimated that this strain fluctuation is increased up to 6·10−4 at cryogenic temperature. The longer-ranged fluctuations are of the 10−3 order, and are associated to misfit dislocations in the plastically-relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 μeV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material related inhomogeneities may feed into further modelling for the optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.
(28) Nanoscale Mapping of the 3D Strain Tensor in a Germanium Quantum Well Hosting a Functional Spin Qubit Device
C. Corley-Wiciak, C. Richter, M.H. Zoellner, I. Zaitev, C.L. Manganelli, E. Zatterin, T.U. Schülli, A.A. Corley-Wiciak, J. Katzer, F. Reichmann, W.M. Klesse, N.W. Hendrickx, A. Sammak, M. Veldhorst, G. Scappucci, M. Virgilio, G. Capellini
ACS Applied Materials & Interfaces 15(2), 3119 (2023)
DOI: 10.1021/acsami.2c17395, (QLSI)
A strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by Synchrotron-based Scanning X-ray Diffraction Microscopy to determine all its Bravais lattice parameters.
This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approx. 50 nm. Two different spatial scales governing the strain field fluctuations in the proximity of the qubits are observed over < 100 nm and > 1μm respectively. The short-ranged fluctuations have a typical bandwidth of 2 · 10−4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations it is estimated that this strain fluctuation is increased up to 6·10−4 at cryogenic temperature. The longer-ranged fluctuations are of the 10−3 order, and are associated to misfit dislocations in the plastically-relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 μeV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material related inhomogeneities may feed into further modelling for the optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.
(29) Nanoscale Mapping of the 3D Strain Tensor in a Germanium Quantum Well Hosting a Functional Spin Qubit Device
C. Corley-Wiciak, C. Richter, M.H. Zoellner, I. Zaitev, C.L. Manganelli, E. Zatterin, T.U. Schülli, A.A. Corley-Wiciak, J. Katzer, F. Reichmann, W.M. Klesse, N.W. Hendrickx, A. Sammak, M. Veldhorst, G. Scappucci, M. Virgilio, G. Capellini
ACS Applied Materials & Interfaces 15(2), 3119 (2023)
DOI: 10.1021/acsami.2c17395, (SiGeQuant)
A strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by Synchrotron-based Scanning X-ray Diffraction Microscopy to determine all its Bravais lattice parameters.
This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approx. 50 nm. Two different spatial scales governing the strain field fluctuations in the proximity of the qubits are observed over < 100 nm and > 1μm respectively. The short-ranged fluctuations have a typical bandwidth of 2 · 10−4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations it is estimated that this strain fluctuation is increased up to 6·10−4 at cryogenic temperature. The longer-ranged fluctuations are of the 10−3 order, and are associated to misfit dislocations in the plastically-relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 μeV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material related inhomogeneities may feed into further modelling for the optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.
(30) Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
A. Datsuk, P. Ostrovskyy, F. Vater, C. Wieden
Proc. 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), (2023)
DOI: 10.1109/VLSI-SoC57769.2023.10321846, (Design Kit)
(31) SiGe BiCMOS Technology with Embedded Microchannels based on Cu Pillar PCB Integration Enabling Sub-THz Microfluidic Sensor Applications
E.C. Durmaz, C. Heine, Z. Cao, J. Lehmann, D. Kissinger, M. Wietstruck
Proc. IEEE International 3D System Integration Conference (3DIC 2023), (2023)
DOI: 10.1109/3DIC57175.2023.10155073, (DFG-THz LoC)
(32) Low-Temperature Monitoring with Implantation and Alloying
L. Ende, M. Grund, U. Schwarz, C. Preiss, V. Götz, S. Ramasubramanian, J. Niess, W. Lerch, A. Scheit
MRS Advances 7, 1525 (2023)
DOI: 10.1557/s43580-022-00459-0
Rapid thermal processing is one of the key thermal processes in semiconductor manufacturing. The temperatures and times at which they are carried out range from very low to extremely high temperatures for very short or long durations depending on the application. As the temperature–time cycle has changed radically over the years, manufacturing equipments need to be monitored for the stability of the manufacturing process. This paper examines and presents especially the complex monitoring process for low temperature processing by a defined implantation condition and an alloying method capable of monitoring processes at temperatures below 600 °C to ensure the process requirements of the manufacturing flow.
(33) Prototyping Reconfigurable RRAM-based AI Accelerators using the RISC-V Ecosystem and Digital Twins
M. Fritscher, A. Veronesi, A. Baroni, J. Wen, T. Spätling, M.K. Mahadevaiah, N. Herfurth, E. Perez, M. Ulbricht, M. Reichenbach, A. Hagelauer, M. Krstic
Proc. 1st International Conference on High Performance Computing (ISC High Performance 2023), in: Lecture Notes in Computer Science, Springer, LNCS 13999, 500 (2023)
DOI: 10.1007/978-3-031-40843-4_37, (KI-PRO)
(34) Prototyping Reconfigurable RRAM-based AI Accelerators using the RISC-V Ecosystem and Digital Twins
M. Fritscher, A. Veronesi, A. Baroni, J. Wen, T. Spätling, M.K. Mahadevaiah, N. Herfurth, E. Perez, M. Ulbricht, M. Reichenbach, A. Hagelauer, M. Krstic
Proc. 1st International Conference on High Performance Computing (ISC High Performance 2023), in: Lecture Notes in Computer Science, Springer, LNCS 13999, 500 (2023)
DOI: 10.1007/978-3-031-40843-4_37, (KI-IoT)
(35) Prototyping Reconfigurable RRAM-based AI Accelerators using the RISC-V Ecosystem and Digital Twins
M. Fritscher, A. Veronesi, A. Baroni, J. Wen, T. Spätling, M.K. Mahadevaiah, N. Herfurth, E. Perez, M. Ulbricht, M. Reichenbach, A. Hagelauer, M. Krstic
Proc. 1st International Conference on High Performance Computing (ISC High Performance 2023), in: Lecture Notes in Computer Science, Springer, LNCS 13999, 500 (2023)
DOI: 10.1007/978-3-031-40843-4_37, (iCampus II)
(36) Prototyping Reconfigurable RRAM-based AI Accelerators using the RISC-V Ecosystem and Digital Twins
M. Fritscher, A. Veronesi, A. Baroni, J. Wen, T. Spätling, M.K. Mahadevaiah, N. Herfurth, E. Perez, M. Ulbricht, M. Reichenbach, A. Hagelauer, M. Krstic
Proc. 1st International Conference on High Performance Computing (ISC High Performance 2023), in: Lecture Notes in Computer Science, Springer, LNCS 13999, 500 (2023)
DOI: 10.1007/978-3-031-40843-4_37, (VE-HEP)
(37) Prototyping Reconfigurable RRAM-based AI Accelerators using the RISC-V Ecosystem and Digital Twins
M. Fritscher, A. Veronesi, A. Baroni, J. Wen, T. Spätling, M.K. Mahadevaiah, N. Herfurth, E. Perez, M. Ulbricht, M. Reichenbach, A. Hagelauer, M. Krstic
Proc. 1st International Conference on High Performance Computing (ISC High Performance 2023), in: Lecture Notes in Computer Science, Springer, LNCS 13999, 500 (2023)
DOI: 10.1007/978-3-031-40843-4_37, (6G-RIC)
(38) Toward FEOL Integration of SiN Waveguides into a Photonic BiCMOS Process
F. Goetz, St. Lischke, G. Georgieva, A. Peczek, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), WC5 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141964, (PEARLS)
(39) Toward FEOL Integration of SiN Waveguides into a Photonic BiCMOS Process
F. Goetz, St. Lischke, G. Georgieva, A. Peczek, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), WC5 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141964, (DFG ULTRA 2)
(40) On Cold Operation of an SiGe HBT as a Broadband Low-NEP THz Direct Detector
J. Grzyb, M. Andree, B. Heinemann, H. Rücker, U. Pfeiffer
Proc. 48th International Conference on Infrared, Millimeter and Terahertz Waves (IRMMW-THz 2023), (2023)
DOI: 10.1109/IRMMW-THz57677.2023.10299102
(41) Thermal Analysis and Design of a Ka-Band Power Amplifier in 130 nm SiGe BiCMOS
A. Haag, M. Kaynak, A.C. Ulusoy
Proc. 23rd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2023), 47 (2023)
DOI: 10.1109/SiRF56960.2023.10046279
(42) Strongly Enhanced Sensitivities of CMOS Compatible Plasmonic Titanium Nitride Nanohole Arrays for Refractive Index Sensing under Oblique Incidence
W. Han, S. Reiter, J. Schlipf, Ch. Mai, D. Spirito, J. Jose, Ch. Wenger, I.A. Fischer
Optics Express 31(11), 17389 (2023)
DOI: 10.1364/OE.481993, (iCampus)
TiN is a complementary metal-oxide-semiconductor (CMOS) compatible material with large potential for the fabrication of plasmonic structures suited for device integration. However, the comparatively large optical losses can be detrimental for application. This work reports a CMOS compatible TiN nanohole array (NHA) on top of a multilayer stack for potential use in integrated refractive index sensing with high sensitivities. The stack, consisting of the TiN NHA on a silicon dioxide (SiO2) layer with Si as substrate (TiN NHA/SiO2/Si), is prepared using an industrial CMOS compatible process. The TiN NHA/SiO2/Si shows Fano resonances in reflectance spectra under oblique excitation, which are very well reproduced by simulation using both finite difference time domain (FDTD) and rigorous coupled-wave analysis (RCWA) methods. Our systematic simulation-based investigation of the sensitivity of the TiN NHA/SiO2/Si stack under varied conditions reveals that very large sensitivities up to 2305 nm per refractive index unit (nm RIU–1) are predicted when the refractive index of superstrate is similar to that of the SiO2 layer. We analyze in detail how the interplay between plasmonic and photonic resonances such as surface plasmon polaritons (SPPs), localized surface plasmon resonances (LSPRs), Rayleigh Anomalies (RAs), and photonic microcavity modes (Fabry-Pérot resonances) contributes to this result. This work not only reveals the tunability of TiN nanostructures for plasmonic applications but also paves the way to explore efficient devices for sensing in broad conditions.
(43) MBE-Based Growth of Sn-Rich Quantum Wells and Dots at Low Sn Deposition Rates
A. Hayat, D. Spirito, A.A. Corley-Wiciak, M.A. Schubert, M. Masood, F. Reichmann, M. Ratzke, G. Capellini, I.A. Fischer
Materials Science in Semiconductor Processing 165, 107693 (2023)
DOI: 10.1016/j.mssp.2023.107693
Alloying Ge with Sn is a possible route towards obtaining a direct bandgap material that can be integrated with Si technology for optoelectronic device applications. Low-dimensional structures such as GeSn quantum wells or islands are of particular interest, since those applications can benefit from quantum confinement effects. Here, we investigate the formation of Sn-rich quantum wells and islands formed by the deposition of few MLs of Sn on Ge and their overgrowth with Ge both based on a morphological characterization of the samples as well as photoluminescence measurements. We find that a low substrate temperature as well as a low deposition rate have an impact on the critical layer thickness at which the onset of Sn island formation can be observed and discuss the implications both for the samples grown and future research efforts.
(44) Silicon Photonic Supported by Dielectrophoresis for Detecting Microbes
A. Henriksson, M. Altmann, P. Neubauer, M. Birkholz
Proc. 4th European Biosensor Symposium (EBS 2023), 116 (2023)
(Bioelectronics)
(45) Reliable Backside IC Preparation Down to STI Level Using Chemical Mechanical Polishing (CMP) with Highly Selective Slurry
N. Herfurth, A.A. Adesunkanmi, G. Zwicker, C. Boit
Proc. 49th International Symposium for Testing and Failure Analysis (ISTFA 2023), 265 (2023)
DOI: 10.31399/asm.cp.istfa2023p0265
(46) Selective Electrodeposition of Indium Microstructures on Silicon and their Conversion into InAs and InSb Semiconductors
K.E. Hnida-Gut, M. Sousa, P. Tiwari, H. Schmid
Discover Nano 18, 4 (2023)
DOI: 10.1186/s11671-023-03778-9
The idea of benefitting from the properties of III-V semiconductors and silicon on the same substrate has been occupying the minds of scientists for several years. Although the principle of III-V integration on a silicon-based platform is simple, it is often challenging to perform due to demanding requirements for sample preparation rising from a mismatch in physical properties between those semiconductor groups (e.g. different lattice constants and thermal expansion coefficients), high cost of device-grade materials formation and their post-processing. In this paper, we demonstrate the deposition of group-III metal and III-V semiconductors in microfabricated template structures on silicon as a strategy for heterogeneous device integration on Si. The metal (indium) is selectively electrodeposited in a 2-electrode galvanostatic configuration with the working electrode (WE) located in each template, resulting in well-defined In structures of high purity. The semiconductors InAs and InSb are obtained by vapour phase diffusion of the corresponding group-V element (As, Sb) into the liquified In confined in the template. We discuss in detail the morphological and structural characterization of the synthesized In, InAs and InSb crystals as well as chemical analysis through scanning electron microscopy (SEM), scanning transmission electron microscopy (TEM/STEM), and energy-dispersive X-ray spectroscopy (EDX). The proposed integration path combines the advantage of the mature top-down lithography technology to define device geometries and employs economic electrodeposition (ED) and vapour phase processes to directly integrate difficult-to-process materials on a silicon platform.
(47) Formation of One-Dimensionally Self–Aligned Si–QDs and their Local Electron Charging Properties
Y. Imai, K. Makihara , Y. Yamamoto, W.-C. Wen, M.A. Schubert, J. Baek, R. Tsuji, N. Taoka, A. Ohta, S. Miyazaki
Proc. 55th International Conferene on Solid State Devices and Materials (SSDM 2023), 523 (2023)
(48) Tunable and Highly Power Efficient Traveling Wave Amplifier in SiGe BiCMOS for Optical Modulators
M. Inac, F. Korndörfer, F. Gerfers, A. Malignaggi
Proc. Radio Wireless Week (RWW 2023), 58 (2023)
DOI: 10.1109/SiRF56960.2023.10046248
(49) DC-Coupled Ultra Broadband Differential to Single-Ended Active Balun in 130-nm SiGe BiCMOS Technology
F. Iseini, A. Malignaggi, F. Korndörfer, G. Kahmen
IEEE Microwave and Wireless Components Letters 33(3), 307 (2023)
DOI: 10.1109/LMWC.2022.3216347, (100G)
The dc-coupled (DCC) broadband operation is a fundamental requirement in many applications, especially in optical communication systems. However, circuits allowing differential to single-ended conversion in a DCC fashion are very rare to be found in the literature. In this letter, a novel differential to single-ended ultrabroadband DCC balun in a 130-nm SiGe BiCMOS technology featuring ft/fmax of 300/500 GHz is presented. A circuit analysis and a performance comparison between the proposed balun and two other configurations which are commonly used to convert a differential signal to a single-ended one is carried out. The design of the mentioned balun is described focusing on the trade-offs between gain, bandwidth (BW) and linearity. Measurement results show how the presented topology can achieve a low-frequency power gain of −7 dB and a 1 dB BW of 80 GHz, along with a total harmonic distortion (THD) of 7%.
(50) Determining Graphene and Substrate Quality from the Coupled Hall Mobility Measurements and Theoretical Modeling
K. Japec, M. Matić, R. Lukose, M. Lisker, M. Lukosius, M. Poljak
46th MIPRO ICT and Electronics Convention (MIPRO 2023), 179 (2023)
DOI: 10.23919/MIPRO57284.2023.10159692, (GRONGER)
(51) A Si Photonic BiCMOS Coherent QPSK Transmitter Based on Parallel-Dual Ring Modulators
Y. Jo, Y. Ji, M. Kim, H.-K. Kim, M.-H. Kim, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), WC4 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141915
(52) Monte-Carlo Characterization of Si Ring Modulator PAM-4 Eye Diagram Performance
Y. Jo, Y. Ji, M. Kim, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
Japanese Journal of Applied Physics 62(6), 066502 (2023)
DOI: 10.35848/1347-4065/acd3cb
The eye diagram performance of the Si ring modulator (RM) is Monte-Carlo characterized with the RM equivalent circuit model. Inter-die statistical distributions of Si-RM model parameters are determined from simple RM optical transmission and electrical reflection coefficient measurement, and the correlated model parameter sets are randomly generated for Monte-Carlo simulation of 40-Gbps 4-level pulse amplitude modulation (PAM-4) eye diagrams within SPICE. From the resulting Monte-Carlo simulated eye diagrams, the yield for the Si RMs that satisfy optical modulation amplitude (OMA) and ratio of level mismatch (RLM) requirements can be corroborated with measurement. With these, the eye diagrams of Si electronic-photonic integrated PAM-4 transmitter with RMs and driver electronics are Monte-Carlo characterized. This approach allows the extension of the standard Si IC characterization technique to the electronic-photonic ICs and can produce better-performing solutions with better yields in the design stage.
(53) Vertical Gate-All-Around SiGeSn/GeSn/SiGeSn Nanowire nFETs
Y. Junk, O. Concepción, M. Frauenrath, F. Bärwolf, A. Mai, J.-M. Hartmann, D. Grützmacher, D. Buca, Q.-T. Zhao
Proc. 55th International Conference on Solid State Devices and Materials (SSDM 2023), 649 (2023)
(54) Monolithic Integration of InP Nanowires with CMOS Fabricated Silicon Nanotips Wafer
A. Kamath, O. Skibitzki, D. Spirito, S. Dadgostar, I.M. Martinez, M. Schmidbauer, C. Richter, A. Kwasniewski, J. Serrano, J. Jimenez, C. Golz, M.A. Schubert, J.W. Tomm, N. Gang, F. Hatami
Physical Review Materials 7(10), 103801 (2023)
DOI: 10.1103/PhysRevMaterials.7.103801, (NHEQuanLEA)
The integration of both optical and electronic components on a single chip, despite several challenges, holds the promise of compatibility with complementary metal-oxide semiconductor (CMOS) technology and high scalability. Among all candidate materials, III-V semiconductors exhibit great potential for optoelectronics and quantum-optics based devices, such as light emitters and harvesters. The control over geometry, and dimensionality of the III-V nanostructures, enables one to modify the band structures, and hence provide a powerful tool for tailoring the optoelectronic properties of III-V compounds. One of the most creditable approaches towards such growth control is the combination of using a patterned wafer and the self-assembled epitaxy. This work presents monolithically integrated catalyst-free InP nanowires grown selectively on Si nanotip-patterned, CMOS compatible (001) Si substrates using gas-source molecular-beam epitaxy. We use nanoheteroepitaxy approach to selectively grow InP nanowires on Si nanotips, which holds benefits due to its peculiar substrate design. In addition, our methodology allows the switching of dimensionality of the InP structures between one-dimensional nanowires and three-dimensional bulklike InP nanoislands by thermally modifying the shape of silicon nanotips surrounded by the silicon dioxide layer during the thermal cleaning of the substrate. The structural and optical characterization of nanowires indicates the coexistence of both zincblende and wurtzite InP crystal phases in nanowires. The two different crystal structures were aligned with a type-II band alignment. The luminescence from InP nanowires was measured up to 300 K, which reveals their promising optical quality for integrated photonics and optoelectronic applications.
(55) A 10-100-GHz Wideband Amplifier with Low-Impedance Coupled Lines in SiGe BiCMOS
D. Kim, H. Son, J. Kim, J. Lee, Y. Zhao, R. Al Hadi, M. Kaynak, M.-C.F. Chang, J.-S. Rieh
IEEE Microwave and Wireless Technology Letters (MWTL) 33(9),1313 (2023)
DOI: 10.1109/LMWT.2023.3288114
This letter presents a mm-wave wideband amplifier implemented in a 130-nm SiGe BiCMOS technology operating up to 100 GHz. For the wideband operation, a new wideband technique based on low-impedance coupled line structure was proposed and adopted to the amplifier in combination with other bandwidth extension techniques. The enhancement of the amplifier bandwidth with the low-impedance coupled lines employed at the input and output matching networks is introduced in detail along with methodologies for actual implementation. The fabricated amplifier showed a peak gain of 13.2 dB with a 3-dB bandwidth of 90 GHz, covering from 10 to 100 GHz. The power consumption of the amplifier is 117 mW. The chip size is 865 × 344 μm2 excluding probing pads.
(56) Investigation of the Impact of Amorphous Silicon Layers Deposited by PECVD and HDP-CVD on Oxide Precipitation in Silicon
G. Kissinger, D. Kot, F. Bärwolf, M. Lisker
Materials Science in Semiconductor Processing 164, 107614 (2023)
DOI: 10.1016/j.mssp.2023.107614, (Future Silicon Wafers)
The effect of deposited a-Si layers with different layer stress on oxide precipitation was investigated in order to find out if intrinsic point defects affecting oxide precipitation are generated at the interface a-Si/Si and if possibly hydrogen affects the oxide precipitation. A thermal cycle of nucleation at 650 °C for 4 h or 8 h followed by stabilization at 780 °C for 3 h, and growth at 1000 °C for 16 h was applied. It was found that there are no signs for the injection of intrinsic point defects from the interface a-Si/Si into the Si substrate during the applied thermal treatment. However if a-Si is deposited on 1000 nm silicon oxide, deposited previously from TEOS in a plasma process, silicon self-interstitials seem to be injected from the interface silicon oxide/Si into the silicon substrate retarding oxide precipitation in the initial stage of nucleation annealing at 650 °C. There are also no signs of any impact of the layer stress on oxide precipitation or self-interstitial injection. The concentration of hydrogen in the layers can be controlled via the RF bias power. The hydrogen concentration is reduced markedly already during annealing at 650 °C. Part of the hydrogen diffuses into the silicon substrate and enhances oxide precipitation if its initial concentration in the layers is higher than 1.5 × 1022 cm−3. For a-Si deposited on 1000 nm silicon oxide, the enhancement effect appears for hydrogen concentrations in the layer higher than approximately 2.8 × 1022 cm−3.
(57) Resiliency in Digital Processing Systems
M. Krstic, M. Andjelkovic, J.-C. Chen, L. Lu, A. Veronesi, M. Ulbricht
Proc. 33rd IEEE International Conference on Microelectronics (MIEL 2023), 19 (2023)
DOI: 10.1109/MIEL58498.2023.10315819, (Scale4Edge)
(58) Ultra-Fast Germanium Photodiodes
St. Lischke, A. Peczek, D. Steckler, J. Morgan, A. Beling, L. Zimmermann
Proc. Conference on Lasers and Electro-Optics (CLEO 2023), SM4G.5 (2023)
DOI: 10.1364/CLEO_SI.2023.SM4G.5, (DFG EPIDAC)
(59) Ultra-Fast Germanium Photodiodes
St. Lischke, A. Peczek, D. Steckler, J. Morgan, A. Beling, L. Zimmermann
Proc. Conference on Lasers and Electro-Optics (CLEO 2023), SM4G.5 (2023)
DOI: 10.1364/CLEO_SI.2023.SM4G.5, (plaCMOS)
(60) Ultra-Fast Germanium Photodiodes
St. Lischke, A. Peczek, D. Steckler, J. Morgan, A. Beling, L. Zimmermann
Proc. Conference on Lasers and Electro-Optics (CLEO 2023), SM4G.5 (2023)
DOI: 10.1364/CLEO_SI.2023.SM4G.5, (DFG EPIC-Sense 2)
(61) Ultra-Fast Germanium Photodiodes
St. Lischke, A. Peczek, D. Steckler, J. Morgan, A. Beling, L. Zimmermann
Proc. Conference on Lasers and Electro-Optics (CLEO 2023), SM4G.5 (2023)
DOI: 10.1364/CLEO_SI.2023.SM4G.5, (DFG ULTRA 2)
(62) Plasma-Enhanced Atomic Layer Deposition of Silicon Nitride for Front-End-of-Line Applications
M. Lisker, M.K. Mahadevaiah, K. Dorai Swamy Reddy
Journal of Vacuum Science and Technology A 41(4), 042406 (2023)
DOI: 10.1116/6.0002424
SiN deposition at low temperatures using the plasma-enhanced atomic layer deposition (PEALD) process is gaining momentum. A high-quality SiN layer deposited using a lower thermal budget and low wet etch rates are desired for front-end-of-line applications in semiconductor industries. In this study, deposition of PEALD SiN is investigated by utilizing a highly reactive trisilylamine silicon precursor and three different reaction partners for a nitrogen precursor. The quality of PEALD SiN layers is compared with the reference standard, low-pressure chemical vapor deposition SiN layers. The properties of different SiN layers are interpreted using FTIR and XPS material characterization techniques. Furthermore, the wet etch rates of as-deposited and annealed PEALD SiN layers are investigated. Finally, the conformality of PEALD SiN layers is assessed in trench and horizontal high aspect ratio structures.
(63) Vertical GeSn Nanowire MOSFETs for CMOS Beyond Silicon
M. Liu, Y. Junk, Y. Han, D. Yang, J.H. Bae, M. Frauenrath, J.-M. Hartmann, Z. Ikonic, F. Bärwolf, A. Mai, D. Grützmacher, J. Knoch, D.M. Buca, Q.-T. Zhao
Communications Engineering 2, 7 (2023)
DOI: 10.1038/s44172-023-00059-2, (SiGeSn NanoFETs)
The continued downscaling of silicon CMOS technology presents challenges for achieving the required low power consumption. While high mobility channel materials hold promise for improved device performance at low power levels, a material system which enables both high mobility n-FETs and p-FETs, that is compatible with Si technology and can be readily integrated into existing fabrication lines is required. Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transconductance is increased to 850 µS/µm by exploiting the small band gap of GeSn as source yielding high injection velocities, the mobility in n-FETs is increased 2.5-fold compared to a Ge reference device, by using GeSn as channel material. The potential of the material system for a future beyond Si CMOS logic and quantum computing applications is demonstrated via a GeSn inverter and steep switching at cryogenic temperatures, respectively.
(64) Strain Relaxation from Annealing of SiGe Heterostructures for Qubits
Y. Liu, K.-P. Gradwoh, C.-H. Lu, K. Dadzis, Y. Yamamoto, L. Becker, P. Storck, T. Remmele, T. Boeck, C. Richter, M. Albrecht
Journal of Applied Physics 134(3), 035302 (2023)
DOI: 10.1063/5.0155448
The misfit dislocation formation related to plastic strain relaxation in Si or Ge quantum well layers in SiGe heterostructures for spin qubits tends to negatively affect the qubit behaviors. Therefore, it is essential to understand and then suppress the misfit dislocation formation in the quantum well layers in order to achieve high-performance qubits. In this work, we studied the misfit dislocation propagation kinetics and interactions by annealing the strained Si or Ge layers grown by molecular beam epitaxy. The annealing temperatures are from 500 to 600 °C for Si layers and from 300 to 400 °C for Ge layers. The misfit dislocations were investigated by electron channeling contrast imaging. Our results show that the misfit dislocation propagation is a thermally activated process. Alongside, the blocking and unblocking interactions during misfit dislocations were also observed. The blocking interactions will reduce the strain relaxation according to theoretical calculation. These observations imply that it is possible to suppress the misfit dislocation formation kinetically by reducing the temperatures during the SiGe heterostructure epitaxy and post-epitaxy processes for developing well-functional SiGe-based spin qubits.
(65) Growth of 28Si Quantum Well Layers for Qubits by a Hybrid MBE/CVD Technique
Y. Liu, K.-P. Gradwohl, C.-H. Lu, Y. Yamamoto, T. Remmele, C. Corley-Wiciak, T. Teubner, C. Richter, M. Albrecht, T. Boeck
ECS Journal of Solid State Science and Technology 12(2), 024006 (2023)
DOI: 10.1149/2162-8777/acb734
Isotopically enriched 28Si quantum well layers in SiGe/Si/SiGe heterostructures are an excellent material platform for electron spin qubits. Here, we report the fabrication of 28SiGe/28Si/28SiGe heterostructures for qubits by a hybrid molecular beam epitaxy (MBE) / chemical vapour deposition (CVD) growth, where the thick relaxed SiGe substrates are realised by a reduced-pressure CVD and the 28SiGe/28Si/28SiGe stacks are grown by MBE. We achieve a fully strained 28Si quantum well layer in such heterostructures with a 29Si concentration as low as 200 ppm within the MBE grown layers and conclude that 29Si primarily originates from the residual natural Si vapour in the MBE chamber. A reliable surface preparation combining ex-situ wet chemical cleaning and in-situ annealing and atomic hydrogen irradiation offers epitaxy ready CVD grown SiGe substrates with low carbon and oxygen impurities. Furthermore, we also present our studies about the growth temperature effect on the misfit dislocation formation in this heterostructure. This shows that the misfit dislocation formation is significantly suppressed at a low MBE growth temperature, such as 350°C.
(66) Development of a 200 mm Wafer Silicon Nitride PIC Environment for Graphene Electro-Absorption Modulators
R. Lukose, M. Lisker, P.K. Dubey, M.A.I. Raju, A. Peczek, A. Kroh, M. Lukosius, A. Mai
Proc. 55th International Conference on Solid State Devices and Materials (SSDM 2023), 403 (2023)
(2D-EPL)
(67) Integration of Memristive Devices into a 130 nm CMOS Baseline Technology
M.K. Mahadevaiah, M. Lisker, M. Fraschke, St. Marschmeyer, E. Perez, E. Perez-Bosch Quesada, Ch. Wenger, A. Mai
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Integration of Memristive Devices into a 130 nm CMOS Baseline Technology, Springer Series on Bio- and Neurosystems (SSDM) 16, Springer, 177 (2023)
DOI: 10.1007/978-3-031-36705-2_7, (NeuroMem)
(68) Integration of Memristive Devices into a 130 nm CMOS Baseline Technology
M.K. Mahadevaiah, M. Lisker, M. Fraschke, St. Marschmeyer, E. Perez, E. Perez-Bosch Quesada, Ch. Wenger, A. Mai
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Integration of Memristive Devices into a 130 nm CMOS Baseline Technology, Springer Series on Bio- and Neurosystems (SSDM) 16, Springer, 177 (2023)
DOI: 10.1007/978-3-031-36705-2_7, (FMD)
(69) Integration of Memristive Devices into a 130 nm CMOS Baseline Technology
M.K. Mahadevaiah, M. Lisker, M. Fraschke, St. Marschmeyer, E. Perez, E. Perez-Bosch Quesada, Ch. Wenger, A. Mai
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Integration of Memristive Devices into a 130 nm CMOS Baseline Technology, Springer Series on Bio- and Neurosystems (SSDM) 16, Springer, 177 (2023)
DOI: 10.1007/978-3-031-36705-2_7, (Neutronics)
(70) SiGe- and Ge-based Devices as Key Enabler of High Performance RF Electronic and Photonic Technologies
A. Mai
Proc. 13th International WorkShop on New Group IV Semiconductor Nanoelectronics (2023), abstr. book 1 (2023)
(71) Room Temperature Light Emission from Superatom-Like Ge-Core/Si-Shell Quantum Dots
K. Makihara, Y. Yamamoto, Y. Imai, N. Taoka, M.A. Schubert, B. Tillack, S. Miyazaki
Nanomaterials 13(9), 1475 (2023)
DOI: 10.3390/nano13091475
We have demonstrated the high–density formation of super–atom–like Si quantum dots with Ge–core on ultrathin SiO2 with control of high–selective chemical–vapor deposition and applied them to an active layer of light–emitting diodes (LEDs). Through luminescence measurements, we have reported characteristics carrier confinement and recombination properties in the Ge–core, reflecting the type II energy band discontinuity between the Si–clad and Ge–core. Additionally, under forward bias conditions over a threshold bias for LEDs, electroluminescence becomes observable at room temperature in the near–infrared region and is attributed to radiative recombination between quantized states in the Ge–core with a deep potential well for holes caused by electron/hole simultaneous injection from the gate and substrate, respectively. The results will lead to the development of Si–based light–emitting devices that are highly compatible with Si–ultra–large–scale integration processing, which has been believed to have extreme difficulty in realizing silicon photonics.
(72) TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance
D. Maldonado, A. Cantudo, E. Perez, R. Romero-Zaliz, E. Perez-Bosch Quesada, M.K. Mahadevaiah, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Frontiers in Neuroscience 17, 1271956 (2023)
DOI: 10.3389/fnins.2023.1271956, (KI-IoT)
We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.
(73) Gain Measurements of the First Proof-of-Concept PicoAD Prototype with a 55Fe X-Ray Radiative Source
M. Milanesio, G. Lacobucci, L. Paolozzi, M. Munker, R. Cardella, Y. Gurimskaya, F. Matinelli, A. Picardi, H. Rücker, A. Trusch, P. Valerio, F. Cadoux, R. Cardarelli, S. Debieux, Y. Favre, D. Ferrere, S. Gonzalez-Sevilla, R. Kotitsa, C. Magliocca, T. Moretti, M. Nessi, J. Saidi, M. Vicente Barreto Pinto, S. Zambito
Nuclear Instruments and Methods in Physics Research Section A 1046, 167807 (2023)
DOI: 10.1016/j.nima.2022.167807
The Picosecond Avalanche Detector is a multi-junction silicon pixel detector devised to enable charged-particle tracking with high spatial resolution and picosecond time-stamping capability. A proof-of-concept prototype of the PicoAD sensor has been produced by IHP microelectronics. Measurements with a 55Fe X-ray radioactive source show that the prototype is functional with an avalanche gain up to a maximum electron gain of 23.
(74) First 100 Gb/s Monolithically Integrated Electronic-Photonic Coherent Receiver with Direct Edge Coupling to Standard Single Mode Fiber Array
A. Osman, G. Winzer, Ch. Mai, A. Peczek, K. Voigt, W. Dorward, St. Lischke, M. Inac, A. Malignaggi, L. Zimmermann, I. Sourikopoulos, L. Stampoulidis
Proc. Optical Fiber Communication Conference (OFC 2023), M3I.3 (2023)
DOI: 10.1364/OFC.2023.M3I.3
(75) Preparation and Investigation of Micro-Transfer-Printable Single-Crystalline InP Coupons for Heterogeneous Integration of III-V on Si
I. Peracchi, C. Richter, T. Schulz, J. Martin, A. Kwasniewski, S. Kläger, C. Frank-Rotsch, P. Steglich, K. Stolze
Crystals (MDPI) 13(7), 1126 (2023)
DOI: 10.3390/cryst13071126
New requirements for high-frequency applications in wireless communication and sensor technologies need III-V compound semiconductors such as indium phosphide (InP) to complement silicon (Si)-based technologies. This study establishes the basis for a new approach to heterogeneous integration of III-V on Si aimed at the transfer of single-crystalline InP coupons on Si via micro-transfer printing (μTP). The InP coupons will act as high-quality virtual substrates that allow selective homo-epitaxy. We present the chemical-mechanical polishing-based preparation and structural characterization of µm-thin (001) InP platelets, starting from high-quality 4-inch bulk crystals and micro-patterning into transferable coupons of several hundred µm2. The obtained InP platelets exhibit the desired thickness—below 10 ± 1 µm—and low surface roughness—<0.3 nm—on both sides, meeting the precondition for µTP and epitaxy. X-ray rocking curve measurements provide accurate spatial maps of the total strain, which indicate small strain variations in the µm-thin InP sample. Rocking curve mappings of the (0 0 4) reflection reveal half-widths below 16 arcsec in the majority of the sample area after thinning that is similar to commercially available InP bulk substrates. Pole figure measurements show no evidence of stress-induced micro-twinning or stacking faults. Overall, minor indications of crystal quality degradation in the product platelets, compared with the bulk samples, were detected.
(76) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (MIMEC)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(77) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (KI-PRO)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(78) Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale
E. Perez, D. Maldonado, E. Perez-Bosch Quesada, M.K. Mahadevaiah, F. Jimenez-Molinos, Ch. Wenger, J.B. Rodan
IEEE Transactions on Electron Devices 70(1), 360 (2023)
DOI: 10.1109/TED.2021.3072868, (KI-IoT)
The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.
(79) A 142 GHz 4/5 Dual-Modulus Prescaler for Wideband and Low Noise Frequency Synthesizers in 130 nm SiGe:C BiCMOS
L. Polzin, M. van Delden, N. Pohl, H. Rücker, T. Musch
Proc. IEEE MTT-S International Microwave Symposium (IMS 2023), Tu3E-3 (2023)
(80) A 142-GHz 4/5 Dual-Modulus Prescaler for Wideband and Low Noise Frequency Synthesizers in 130-nm SiGe:C BiCMOS
L. Polzin, M. van Delden, N. Pohl, H. Rücker, T. Musch
IEEE Microwave and Wireless Technology Letters (MWTL) 33(6), 867 (2023)
DOI: 10.1109/LMWT.2023.3265861
In this contribution, the simulation and measurement results of a 4/5 dual-modulus prescaler, operating from dc to 142 GHz with a power consumption of 144 mW, are presented. For a division ratio of 4, the maximum operation frequency of 166 GHz is even higher. The prescaler is the core of a fully programmable dual-modulus frequency divider, which is a crucial component of modern measurement systems. The effect of the physical lengths and the resulting internal delays on the prescaler’s performance is analyzed. Furthermore, the voltage level of the fully differential emitter-coupled logic (ECL) is optimized in terms of phase noise and maximum operating frequency. The monolithic microwave integrated circuit (MMIC) is realized in a 130-nm SiGe:C BiCMOS technology with fT/ fmax = 470/650 GHz.
(81) Broadband Hetero-Integration of InP Chiplets on SiGe BiCMOS for mm-Wave MMICs up to 325 GHz
M. Rausch, M. Wietstruck, C. Stölmacker, R. Doerner, G. Fischer, S. Knigge, H. Yacoub, W. Heinrich
Proc. IEEE MTT-S International Microwave Symposium (IMS 2023), 466 (2023)
DOI: 10.1109/IMS37964.2023.10188164, (T-KOS)
(82) Titanium Nitride Plasmonic Nanohole Arrays for CMOS-Compatible Integrated Refractive Index Sensing: Influence of Layer Thickness on Optical Properties
S. Reiter, W. Han, Ch. Mai, D. Spirito, J. Jose, M.H. Zoellner, O. Fursenko, M.A. Schubert, Ch. Wenger, I.A. Fischer
Plasmonics 18, 831 (2023)
DOI: 10.1007/s11468-023-01810-3, (iCampus II)
The combination of nanohole arrays with photodetectors can be a strategy for the large-scale fabrication of miniaturized and cost-effective refractive index sensors on the Si platform. However, complementary metal–oxide–semiconductor (CMOS) fabrication processes place restrictions in particular on the material that can be used for the fabrication of the structures. Here, we focus on using the CMOS compatible transition metal nitride Titanium Nitride (TiN) for the fabrication of nanohole arrays (NHAs). We investigate the optical properties of TiN NHAs with different TiN thicknesses (50 nm, 100 nm, and 150 nm) fabricated using high-precision industrial processes for possible applications in integrated, plasmonic refractive index sensors. Reflectance measurements show pronounced Fano-shaped resonances, with resonance wavelengths between 950 and 1200 nm, that can be attributed to extraordinary optical transmission (EOT) through the NHAs. Using the measured material permittivity as an input, the measured spectra are reproduced by simulations with a large degree of accuracy: Simulated and measured resonance wavelengths deviate by less than 10 nm, with an average deviation of 4 nm observed at incidence angles of 30° and 40°. Our experimental results demonstrate that an increase in the thickness of the TiN layer from 50 to 150 nm leads to a sensitivity increase from 614.5 nm/RIU to 765.4 nm/RIU, which we attribute to a stronger coupling between individual LSPRs at the hole edges with spatially extended SPPs. Our results can be used to increase the performance of TiN NHAs for applications in on-chip plasmonic refractive index sensors.
(83) Evaluation of Si and Ge Segregation from Si0.2Ge0.8(111) through Al and Ag Layer
T. Sakai, A. Ohta, N. Taoka, J. Yuhara, K. Makihara, Y. Yamamoto, W.-C. Wen, S. Miyazaki
Proc. 55th International Conference on Solid State Devices and Materials (SSDM 2023), 33 (2023)
(84) Robust Si/Ge Heterostructure Metasurfaces as Building Blocks for Wavelength-Selective Photodetectors
J. Schlipf, F. Berkmann, Y. Yamamoto, M. Reichenbach, M. Veleski, Y. Kawaguchi, F. Mörz, J.W. Tomm, D. Weißhaupt, I.A. Fischer
Applied Physics Letters 122(12), 121701 (2023)
DOI: 10.1063/5.0134458
We present a design for silicon-compatible vertical Germanium pin photodiodes structured into all-dielectric metasurfaces. Proof-of-principle metasurfaces are fabricated on silicon-on-insulator wafers in a top-down process. Simulations and measurements of the spectroscopic properties, specifically the absorption, show high spectral selectivity, and absorption efficiencies as large as those in bulk Germanium layers with about four times the Ge layer thicknesses. Our metasurface structures can be tuned to the target wavelength through tailoring of the lateral geometry. Possible applications include spectroscopy and hyperspectral imaging, with several metasurfaces for different wavelength ranges integrated with readout circuitry into a low-cost electronic–photonic integrated circuit.
(85) A Differential SiGe HBT Doherty Power Amplifier for Automotive Radar at 79 GHz
J. Schoepfel, H. Rücker, N. Pohl
Proc. 23rd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2023), 44 (2023)
DOI: 10.1109/SiRF56960.2023.10046275, (SG13G3)
(86) 190 GBd PAM-4 Signal Generation using Analog Multiplexer IC with On-Chip Clock Multiplier
J. Schostak, T. Tannert, M. Grözing, V. Jungnickel, C. Schmidt, H. Rücker, M. Berroth, R. Freund
Proc. 18th European Microwave Integrated Circuits Conference (EuMIC 2023), 125 (2023)
DOI: 10.23919/EuMIC58042.2023.10288816, (SG13G3)
(87) Al-Al Waferbonding Process Development For Heterogeneous Integration
S. Schulze, T. Voß, P. Krüger, M. Wietstruck
ECS Transactions 112(19), 25 (2023)
DOI: 10.1149/11201.0025ecst, (FMD)
This paper presents a surface-activated Al-Al wafer bonding process for patterned 200 mm wafers that removes the native oxide in an argon plasma and enables high bond quality with accurate alignment at temperatures below 300°C. The study focuses on various factors that influence the final Al-Al bond in terms of contact resistance and shear strength. In addition to temperature, force and time during the actual bonding process, these include steps during the wafer fabrication that affect the Al bonding pads and the wafer bow. In addition, the impact of a post-bond cleaning process on the final bond result is analyzed. This work shows a low temperature Al-Al bonding process with high yield >90%, excellent bond strength >150 MPa and contact resistances in the mΩ range.
(88) Monolithically Integrated O-Band Coherent ROSA Featuring 2D Grating Couplers for Self-Homodyne Intra Data Center Links
P.M. Seiler, G. Georgieva, A. Peczek, M. Oberon, Ch. Mai, St. Lischke, A. Malignaggi, L. Zimmermann
IEEE Photonics Journal 15(3), 6601306 (2023)
DOI: 10.1109/JPHOT.2023.3272476
In this work, we present an O-band dual-polarization coherent receiver optical sub-assembly (cROSA), monolithically integrated in a 0.25 μ m BiCMOS technology. The receiver features 248 nm deep ultra violet compatible 2-dimensional grating couplers (2D-GRCs), and an adaptive polarization controller, suitable for mitigation of local oscillator induced power fading in self-homodyne transmission systems. The cROSA is evaluated in system experiments at 64 GBd quadrature-phase shift-keying. Experimental results are related to grating coupler induced polarization crosstalk through Monte-Carlo simulations. Second generation 2D-GRCs are proposed.
(89) On-Chip Refractive Index Sensors based on Plasmonic TiN Nanohole Ar-Rays
A. Sengül, S. Reiter, W. Han, Ch. Mai, D. Spirito, J. Jose, O. Fursenko, Ch. Wenger, I.A. Fischer
Proc. 10. MikroSystemTechnik Kongress (MST 2023), 336 (2023)
(iCampus II)
This work presents results on the design and fabrication of an integrated refractive index sensor based on plasmonic TiN nanohole arrays (NHAs) in combination with Ge photodetectors. We discuss optical properties of plasmonic TiN NHAs fabricated by using standard industrial processes and compare experimental results with FDTD simulations to identify parameters that boost sensing performance. We, furthermore, present results on combining those NHAs with Ge photodetectors using the ePIC process at the Leibniz Institute for High Performance Microelectronics (IHP), enabling the production of large PIN Ge-diodes on Si wafers. Our results can pave the way towards large-scale production of integrated refractive index sensors for applications ranging from environmental monitoring to point-of-care diagnostics.
(90) Subnanometer Control of the Heteroepitaxial Growth of Multimicrometer-Thick Ge/(Si,Ge) Quantum Cascade Structures
E.T. Simola, M. Montanari, C. Corley-Wiciak, L. Di Gaspare, L. Persichetti, M.H. Zoellner, M.A. Schubert, T. Venanzi, M.C. Trouche, L. Baldassarre, M. Ortolani, G. Nicotra, G. Capellini M. Virgilio, M. De Seta
Physical Review Applied 19(1), 014011 (2023)
DOI: 10.1103/PhysRevApplied.19.014011, (FLASH)
The fabrication of complex low-dimensional quantum devices requires the control of the heteroepitaxial growth at the subnanometer scale. This is particularly challenging when the total thickness of stacked layers of device-active material becomes extremely large and exceeds the multi-μm limit, as in the case of quantum cascade structures. Here, we use the ultrahigh-vacuum chemical vapor deposition technique for the growth of multi-μm-thick stacks of high Ge content strain-balanced Ge/SiGe tunneling heterostructures on Si substrates, designed to serve as the active material in a THz quantum cascade laser. By combining thorough structural investigation with THz spectroscopy absorption experiments and numerical simulations we show that the optimized deposition process can produce state-of-the-art threading dislocation density, ultrasharp interfaces, control of dopant atom position at the nanoscale, and reproducibility within 1% of the layer thickness and composition within the whole multilayer. We show that by using ultrahigh-vacuum chemical vapor deposition one achieves simultaneously a control of the epitaxy down to the sub-nm scale typical of the molecular beam epitaxy, and the high growth rate and technological relevance of chemical vapor deposition. Thus, this technique is a key enabler for the deposition of integrated THz devices and other complex quantum structures based on the Ge/SiGe material system.
(91) Ultralow-Power W-Band Low-Noise Amplifier Design in 130-nm SiGe BiCMOS
K. Smirnova, Ch. Bohn, M. Kaynak, A.Ç. Ulusoy
IEEE Microwave and Wireless Technology Letters (MWTL) 33(8), 1171 (2023)
DOI: 10.1109/LMWT.2023.3279574
This letter presents a power consumption reduction aspect for a 100-GHz low-noise amplifier (LNA). Two designs implemented in 0.13-µm SiGe bipolar complementary metal oxide semiconductor (BiCMOS) technology demonstrate stateof-the-art performance, whereas PDC is reduced from 23.5 mW for the standard version to 3.8 mW for the low-power version. Two circuits exhibit a measured gain of 22 and 16 dB and a noise figure (NF) of 4 and 6.3 dB at 100 GHz. An input 1-dB compression point for the standard and the low-power version is −24.5 and −26.5 dBm, respectively. The occupied integrated circuit (IC) area in both cases is 0.018 and 0.014 mm2 excluding the pads, which proves to be the most compact design among previously reported in the frequency range of interest.
(92) High-Speed Optical Transceiver Integrated Chipset and Module for On-Board VCSEL-based Satellite Optical Interconnects
L. Sourikopoulos, G. Winzer, A. Peczek, M. Inac, P. Ostrovskyy, K. Tittelbach-Helmrich, G. Panic, G. Fischer, L. Zimmermann, Y. Franz, S. Jones, P. Kushner, U. Marvet, A. Lujambio, N. Garcia, D. Poudereux, M. Bodega, J. Barbero, L. Stampoulidis
Proc. 14th International Conference on Space Optics (ICSO 2022), 127774K (2023)
DOI: 10.1117/12.2690846, (SIPhoDiAS)
(93) Germanium Fin Photodiode with 3dB-Bandwidth >110 GHz and High L-Band Responsivity
D. Steckler, St. Lischke, A. Kroh, A. Peczek, G. Georgieva, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), ThA2 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141946, (PEARLS)
(94) Germanium Fin Photodiode with 3dB-Bandwidth >110 GHz and High L-Band Responsivity
D. Steckler, St. Lischke, A. Kroh, A. Peczek, G. Georgieva, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), ThA2 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141946, (DFG ULTRA 2)
(95) Germanium Fin Photodiode with 3dB-Bandwidth >110 GHz and High L-Band Responsivity
D. Steckler, St. Lischke, A. Kroh, A. Peczek, G. Georgieva, L. Zimmermann
Proc. IEEE Silicon Photonics Conference (SiPhotonics 2023), ThA2 (2023)
DOI: 10.1109/SiPhotonics55903.2023.10141946, (DFG EPIC-Sense 2)
(96) Investigation of Doping Processes to Achieve Highly Doped Czochralski Germanium Ingots
A. Subramanian, N. Abrosimov, A. Gybin, C. Guguschev, U. Juda, A. Fiedler, F. Bärwolf, I. Costina, A. Kwasniewski, A. Dittmar, R. Radhakrishnan Sumathi
Journal of Electronic Materials 52, 5178 (2023)
DOI: 10.1007/s11664-023-10534-3
Highly doped germanium (HD-Ge) is a promising material for mid-infrared detectors, bio-sensors, and other devices. Bulk crystals with a doping concentration higher than 1018 cm−3 would be desirable for such device fabrication technologies. Hence, an effective method needs to be developed to dope germanium (Ge) ingots in the Czochralski (Cz) growth process. In this study, a total of 5 ingots were grown by the Cz technique: two undoped Ge ingots as a reference and three doped ingots with 1018, 1019, and 1020 atoms/cm3 respectively. To obtain a uniform p-type doping concentration along the crystal, co-doping of boron-gallium (B-Ga) via the Ge feed material was also attempted. Both B and Ga are p-type dopants, but with a large difference in their segregation behavior (contrary segregation profile) in Ge, and hence it is expected that the incorporation of dopants in the crystal would be uniform along the crystal length. The distribution of the dopants followed the Scheil-predicted profile. The etch pit density maps of the grown crystals showed an average dislocation density in the order of 105 cm−2. No increase in the overall etch pit count was observed with increasing dopant concentration in the crystal. The grown highly doped Ge crystals have a good structural quality as confirmed by x-ray diffraction rocking curve measurements.
(97) Unintentional P-Type Conductivity in Intrinsic Ge-Rich SiGe/Ge Heterostructures Grown on Si(001)
H. Tetzner, W. Seifert, O. Skibitzki, Y. Yamamoto, M. Lisker, M.M. Mirza, I.A. Fischer, D.J. Paul, M. De Seta, G. Capellini
Applied Physics Letters 122(24), 243503 (2023)
DOI: 10.1063/5.0152962, (FLASH)
In this work, we investigate the effective background charge density in intrinsic Si0.06Ge0.94/Ge plastically-relaxed heterostructures deposited on Si(001). Hall effect measurements and capacitance-voltage profiling reveal a p-type conductivity in the nominally intrinsic layer with a hole concentration in the mid 1015 cm-3 range at temperatures between 50 K and 200 K. Owing to a carrier freeze out below 50 K observed by Hall, we attribute the origin of these carriers to the ionization of shallow acceptor-like defect states above the valence band. In addition, one dominant hole trap located at mid-gap position is found by deep level transient spectroscopy. Carrier trapping kinetics measurements can be interpreted as due to a combination of point defects, likely trapped in the strain field of extended defects, i.e. the threading dislocation themselves.
(98) Production of Modified Nucleosides in a Continuous Enzyme Membrane Reactor
I. Thiele, H. Yehia, N. Krausch, M. Birkholz, M.N. Cruz Bournazou, A. Boing Sitanggang, M. Kraume, P. Neubauer, A. Kurreck
International Journal of Molecular Sciences (IJMS) 24(7), 6081 (2023)
DOI: 10.3390/ijms24076081, (Bioelectronics)
Nucleoside analogues are important compounds for the treatment of viral infections or 20 cancer. While (chemo-)enzymatic synthesis is a valuable alternative to traditional chemical methods, the feasibility of such processes is lowered by the high production cost of the biocatalyst. As continuous enzyme membrane reactors (EMR) allow the use of the biocatalysts until its full inactivation, they offer a valuable alternative to batch enzymatic reactions with freely dissolved enzyme. In contrast to enzyme immobilization approaches losses in enzyme activity are avoided. Therefore, we validated the applicability of EMRs for the synthesis of natural and dihalogenated nucleosides using one-pot transglycosylation reactions. Over a period of 55 days, 2‘-deoxyadenosine was produced continuously with a product yield > 90 %. The dihalogenated nucleoside analogues 2,6-di-chloropurine-2‘-deoxyribonucleoside and 6-chloro-2-fluoro-2‘-deoxyribonucleoside were also produced with high conversion but for shorter operation times of 14 and 5.5 days, respectively. The EMR performed with specific productivities comparable to batch reactions. However, in the EMR 220, 40 and 9 times more product per enzymatic unit was produced for 2‘-deoxyadenosine, 2,6-dichloropurine-2‘-deoxyribonucleoside and 6-chloro-2-fluoro-2‘-deoxyribonucleoside, respectively. The application of the EMR using freely dissolved enzymes facilitates a continuous process with integrated biocatalyst separation which reduces the overall cost of the biocatalyst and enhances the downstream processing of nucleoside production.
(99) One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing
M. Uhlmann, E. Perez-Bosch Quesada, M. Fritscher, E. Perez, M.A. Schubert, M. Reichenbach, P. Ostrovskyy, Ch. Wenger, G. Kahmen
Proc. 21st IEEE International New Circuits And Systems Conference (NEWCAS 2023), (2023)
DOI: 10.1109/NEWCAS57931.2023.10198073, (Neutronics)
(100) Verified Value Chains, Innovation and Competition
A. Weber, S. Guilley, R. Rathfelder, M. Stöttinger, C. Lüth, M. Malenko, T. Grawunder, S. Reith, A. Puccetti, J.-P. Seifert, N. Herfurth, H. Sankowski, G. Heiser
Proc. IEEE International Conference on Cyber Security and Resilience (CSR 2023), 470 (2023)
DOI: 10.1109/CSR57506.2023.10224911, (VE-HEP)
(101) Three-Dimensional Self-Ordered Multilayered Ge Nanodots on SiGe
W.-C. Wen, M.A. Schubert, M.H. Zoellner, B. Tillack, Y. Yamamoto
ECS Journal of Solid State Science and Technology 12(5), 055001 (2023)
DOI: 10.1149/2162-8777/acce06
Three-dimensional (3D) self-ordered Ge nanodots in cyclic epitaxial growth of Ge/SiGe superlattice on Si0.4Ge0.6 virtual substrate (VS) were fabricated by reduced pressure chemical vapor deposition. The Ge nanodots were formed by Stranski-Krastanov mechanism. By the Ge/SiGe superlattice deposition, dot-on-dot alignment and <100> alignment were obtained toward the vertical and lateral direction, respectively. Facets and growth mechanism of Ge nanodots and key factors of alignment were studied. Two types of Ge nanodots were observed, diamond-like nanodots composed of {105} and dome-like nanodots composed of {113} and {519} or {15 3 23} facets. The Ge nanodots tend to grow directly above the nanodots of the previous period as these regions show a relatively higher tensile strain induced by the buried nanodots. Thus, this dot-on-dot alignment is sensitive to the SiGe spacer thickness, and it degrades when the SiGe spacer becomes thicker. The Ge content of the SiGe spacer ranging from 45 to 52% affects the lateral alignment and the size uniformity of Ge nanodots because of the strain balance between the superlattice and the VS. By maintaining the strain balance, ordering of the 3D aligned Ge nanodots can be improved.
(102) Vertical Alignment Control of Self-Ordered Multilayered Ge Nanodots on SiGe
W.-C. Wen, M.A. Schubert, B. Tillack, Y. Yamamoto
Japanese Journal of Applied Physics 62(SC), SC1057 (2023)
DOI: 10.35848/1347-4065/acb05e
Self-ordered multilayered Ge nanodots with SiGe spacers on a Si0.4Ge0.6 virtual substrate are fabricated using reduced-pressure chemical vapor deposition, and the mechanism of vertical ordering is investigated. The process conditions of Ge and SiGe layer deposition are H2-GeH4 at 550 °C and H2-SiH4-GeH4 at 500 °C–550 °C, respectively. By depositing the SiGe at 550 °C or increasing Ge content, the SiGe surface becomes smooth, resulting in vertically aligned Ge nanodots to reduce strain energy. Ge nanodots prefer to grow on the nanodot where the SiGe is relatively tensile strained due to the buried Ge nanodot underneath. By depositing at 500 °C and lowering Ge content, checkerboard-like surface forms, and the following Ge nanodots grow at staggered positions to reduce surface energy. The Ge nanodots are laterally aligned along the elastically soft 〈100〉 direction without pre-structuring resulting from the strain distribution.
(103) Influence of Strain on Multilayer Ge Nanodot Formation on SiGe Virtual Substrate
W.-C. Wen, B. Tillack, Y. Yamamoto
Proc. 55th International Conference on Solid State Device and Materials (SSDM 2023), 519 (2023)
(104) Fabrication and Characteriyation of Germanium n-MOS and n-MOSFET with Thermally Oxidized Yttrium Gate Insulator: Formation of Underlaying Germanium Oxide and its Electrical Characteristics
W.-C. Wen, D. Wang, H. Nakashima, K. Yamamoto
Materials Science in Semiconductor Processing 162, 107504 (2023)
DOI: 10.1016/j.mssp.2023.107504
A high-quality insulating film on germanium is essential for germanium applications. In this study, we oxidized metal yttrium at 500–550 ◦C to generate an yttrium oxide (Y-oxide) layer on germanium. According to transmission electron microscopy images, Y-oxide comprised three layers, which were Y2O3, YGeO3, and GeOx from the top side. n-Type metal-oxide-semiconductor (n-MOS) capacitors and n-type MOS field-effect transistors (n-MOSFETs) with the Y-oxide gate insulator showed typical electrical characteristics. The n-MOS capacitor with the Y-oxide gate insulator had a lower interface state density (Dit) and border trap density (Nbt) than the n-MOS capacitor with a thermally oxidized GeOx insulator, suggesting that defects were terminated by Y atoms in the GeOx layer and GeOx/Ge interface. In contrast, the Dit–energy distribution and Nbt temperature dependence of the Y-oxide gate insulator were similar to those of the GeOx gate insulator, indicating that the defect signals originated in GeOx underlying YGeO3. The structural analysis showed that the temperature of metal yttrium oxidation affected only the GeOx thickness. Therefore, adjusting the conditions of metal yttrium oxidation may produce Y-oxidized gate stacks with a thinner GeOx layer or even direct contact of YGeO3 and Ge, which may result in different Dit values, Nbt values, and Nbt–temperature trends.
(105) Heterointegration of mm-Wave InP-HBT Power Amplifier Chiplets on SiGe-BiCMOS Chip
H. Yacoub, M. Rausch, C. Stölmacker, R. Dörner, M. Hossain, I. Ostermay, T. Moule, M. Wietstruck, S. Knigge, O. Krüger, W. Heinrich
Proc. 26th European Microwave Week (EuMW 2023), 169 (2023)
DOI: 10.23919/EuMIC58042.2023.10289026, (T-KOS)
(106) Heteroepitaxy of Group IV Materials for Future Device Application
Y. Yamamoto, W.-C. Wen, B. Tillack
Japanese Journal of Applied Physics 62(SC), SC0805 (2023)
DOI: 10.35848/1347-4065/acb1a6
Heteroepitxy of group IV materials (Si, SiGe, and Ge) has great potential for boosting Si-based novel device performance because of the possibility for strain, band gap/Fermi-level engineering, and applying emerging artificial materials such as a superlattice (SL) and nanodots. In order to control group IV heteroepitaxy processes, strain, interface, and surface energies are very essential parameters. They affect dislocation formation, interface steepness, reflow of deposited layers, and also surface reaction itself during the growth. Therefore, process control and crystallinity management of SiGe heteroepitaxy are difficult especially in the case of high Ge concentrations. In this paper, we review our results of abrupt SiGe/Si interface fabrication by introducing C-delta layers and the influence of strain on the surface reaction of SiGe. Three-dimensional self-ordered SiGe and Ge nanodot fabrication by proactively using strain and surface energies by depositing SiGe/Si and Ge/SiGe SL are also reviewed.
(107) High Crystallinity Ge Growth on Si (111) and Si (110) by Using Reduced Pressure Chemical Vapor Deposition
Y. Yamamoto, W.-C. Wen, M.A. Schubert, C. Corley-Wiciak, B. Tillack
ECS Journal of Solid State Science and Technology 12(2), 023014 (2023)
DOI: 10.1149/2162-8777/acbb9d
A method for high quality epitaxial growth of Ge on Si (111) and Si (110) is investigated by reduced pressure chemical vapor deposition. Two step Ge epitaxy (low temperature Ge seed and high temperature main Ge growth) with several cycles of annealing by interrupting the Ge growth (cyclic annealing) is performed. In the case of Ge seed layer growth below 350 °C for (111) and 400 °C for (110) orientation, huge surface roughening due to too high dislocation density is observed after the following annealing step. For both crystal orientations, a high crystallinity Ge seed layer is realized by combination of 450 °C growth with 800 °C annealing. Once the high-quality Ge seed layer is deposited, high crystal quality Ge can be grown at 600 °C on the seed layer for both crystal orientations. For the 5 µm thick Ge layer deposited with the cyclic annealing process at 800 °C, a Si diffusion length of ~400 nm from the interface, RMS roughness below 0.5 nm and threading dislocation density of 5×106 cm-2 are achieved for both (111) and (110) substrates
(108) Thin and Locally Dislocation-Free SiGe Virtual Substrate Fabrication by Lateral Selective Epitaxy
Y. Yamamoto, W.-C. Wen, M.A. Schubert, A.A. Corley-Wiciak, S. Sugawa, Y. Ito, R. Yokogawa, A. Ogura, B. Tillack
Proc. 55th International Conference on Solid State Devices and Materials (SSDM 2023), 527 (2023)
(109) Group-IV Heteroepitaxy for Novel and Emerging Device Applications
Y. Yamamoto, W-C. Wen, B. Tillack
Proc. 13th International WorkShop on New Group IV Semiconductor Nanoelectronics (2023), abstr. book 45 (2023)
(110) Redox-Based Bi-Layer Metal Oxide Memristive Devices
F. Zahari, S. Park, M.K. Mahadevaiah, Ch. Wenger, H. Kohlstedt, M. Ziegler
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Redox-Based Bi-Layer Metal Oxide Memristive Devices, Springer Series on Bio- and Neurosystems (SSBN) 16, Springer, 87 (2023)
DOI: 10.1007/978-3-031-36705-2_3, (NeuroMem)
(111) 20 ps Time Resolution with a Fully-Efficient Monolithic Silicon Pixel Detector without Internal Gain Layer
S. Zambito, M. Milanesio, T. Moretti, L. Paolozzi, M. Munker, R. Cardella, T. Kugathasan, F. Martinelli, A. Picardi, M. Elviretti, H. Rücker, A. Trusch, F. Cadoux, R. Cardarelli, S. Débieux, Y. Favre, C.A. Fenoglio, D. Ferrere, S. Gonzalez-Sevilla, L. Iodice, R. Kotitsa, C. Magliocca, M. Nessi, A. Pizarro-Medina, J. Sabater lglesias, J. Saidi, M.V. Barreto Pinto, G. Iacobucci
Journal of Instrumentation 18, P03047 (2023)
DOI: 10.1088/1748-0221/18/03/P03047
A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 μm thick epilayer of 350 Ωcm resistivity were used to produce a fully depleted sensor. Laboratory and testbeam measurements of the analog channels present in the pixel matrix show that the sensor has a 130 V wide bias-voltage operation plateau at which the efficiency is 99.8%. Although this prototype does not include an internal gain layer, the design optimised for timing of the sensor and the front-end electronics provides a time resolutions of 20 ps.
(112) Characterization of a D-Band Electric-Inductive-Capacitive Metamaterial-Based Transmission Line Phase Shifter
G.M. Zampa, A. Sonara, D. Mencarelli, L. Pierantoni, H.J. Christopher, Z. Cao, R. Al Hadi, M.-C.F. Chang, M. Kaynak
Proc. IEEE MTT-S International Microwave Symposium (IMS 2023), 721 (2023)
DOI: 10.1109/IMS37964.2023.10187973, (SMARTWAVE)
(113) Toward 2D Grating Coupler Enabled O-Band Coherent Links based on SiGe Photonic Electronic Technology
L. Zimmermann, P.M. Seiler, Ch. Mai, G. Georgieva
Japanese Journal of Applied Physics 62(SC), SC0807 (2023)
DOI: 10.35848/1347-4065/acb4fe, (DFG EPIC-Sense 2)
Coherent techniques for short reach intra-datacenter optical interconnects are currently intensely discussed. This article reports progress on previous work that analyzed the benefits of switching from C- to O-band optics with regard to digital signal processing. Here we study the feasibility of adapting a coherent approach to an established datacenter interconnect technology (PSM4). This PSM4-like implementation brings about the benefit of much improved resilience to laser drift, thus reducing or eliminating the need for a temperature stabilized laser, which is typically assumed a requirement for coherent transceivers. The analysis rests on simulation parameters derived in part from previous experimental realizations of coherent receivers in SiGe photonic BiCMOS technology. In addition, we make use of recent results regarding the optimization of O-band 2D grating couplers with respect to efficiency and low polarization dependence over a 20nm wavelength window. We identify such couplers as enabling building blocks for coherent PSM4-like implementations.
(114) Toward 2D Grating Coupler Enabled O-Band Coherent Links based on SiGe Photonic Electronic Technology
L. Zimmermann, P.M. Seiler, Ch. Mai, G. Georgieva
Japanese Journal of Applied Physics 62(SC), SC0807 (2023)
DOI: 10.35848/1347-4065/acb4fe, (PEARLS)
Coherent techniques for short reach intra-datacenter optical interconnects are currently intensely discussed. This article reports progress on previous work that analyzed the benefits of switching from C- to O-band optics with regard to digital signal processing. Here we study the feasibility of adapting a coherent approach to an established datacenter interconnect technology (PSM4). This PSM4-like implementation brings about the benefit of much improved resilience to laser drift, thus reducing or eliminating the need for a temperature stabilized laser, which is typically assumed a requirement for coherent transceivers. The analysis rests on simulation parameters derived in part from previous experimental realizations of coherent receivers in SiGe photonic BiCMOS technology. In addition, we make use of recent results regarding the optimization of O-band 2D grating couplers with respect to efficiency and low polarization dependence over a 20nm wavelength window. We identify such couplers as enabling building blocks for coherent PSM4-like implementations.
(115) Toward 2D Grating Coupler Enabled O-Band Coherent Links based on SiGe Photonic Electronic Technology
L. Zimmermann, P.M. Seiler, Ch. Mai, G. Georgieva
Japanese Journal of Applied Physics 62(SC), SC0807 (2023)
DOI: 10.35848/1347-4065/acb4fe, (DFG ULTRA 2)
Coherent techniques for short reach intra-datacenter optical interconnects are currently intensely discussed. This article reports progress on previous work that analyzed the benefits of switching from C- to O-band optics with regard to digital signal processing. Here we study the feasibility of adapting a coherent approach to an established datacenter interconnect technology (PSM4). This PSM4-like implementation brings about the benefit of much improved resilience to laser drift, thus reducing or eliminating the need for a temperature stabilized laser, which is typically assumed a requirement for coherent transceivers. The analysis rests on simulation parameters derived in part from previous experimental realizations of coherent receivers in SiGe photonic BiCMOS technology. In addition, we make use of recent results regarding the optimization of O-band 2D grating couplers with respect to efficiency and low polarization dependence over a 20nm wavelength window. We identify such couplers as enabling building blocks for coherent PSM4-like implementations.
