Publications 2021

Script list Publications

(1) Non-Isothermal Phase-Field Simulations of Laser-Written In-Plane SiGe Heterostructures for Photonic Applications
O. Aktas, Y. Yamamoto, M. Kaynak, A.C. Peacock
Communication Physics 4, 132 (2021)
DOI: /10.1038/s42005-021-00632-1
Advanced solid-state devices, including lasers and modulators, require semiconductor heterostructures for nanoscale engineering of the electronic bandgap and refractive index. However, existing epitaxial growth methods are limited to fabrication of vertical heterostructures grown layer by layer. Here, we report the use of finite-element-method-based phase-field modelling with thermocapillary convection to investigate laser inscription of in-plane heterostructures within silicon-germanium films. The modelling is supported by experimental work using epitaxially-grown Si0.5Ge0.5 layers. The phase-field simulations reveal that various in-plane heterostructures with single or periodic interfaces can be fabricated by controlling phase segregation through modulation of the scan speed, power, and beam position. Optical simulations are used to demonstrate the potential for two devices: graded-index waveguides with Ge-rich (>70%) cores, and waveguide Bragg gratings with nanoscale periods (100–500 nm). Periodic heterostructure formation via sub-millisecond modulation of the laser parameters opens a route for post-growth fabrication of in-plane quantum wells and superlattices in semiconductor alloy films.

(2) Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
E. Amini, K. Bartels, C. Boit, M. Eggert, N. Herfurth, T. Kiyan, T. Krachenfels, J.-P. Seifert, S. Tajik
Proc. 39th VLSI Test Symposium (VTS 2021), (2021)
DOI: 10.1109/VTS50974.2021.9441006

(3) Fiber-to-Chip Light Coupling using a Graded-Index Lensed Fiber Collimator
S. Bondarenko, M. Hülsemann, A. Mai, P. Steglich
Optical Engineering 60(1), 014105 (2021)
DOI: 10.1117/1.OE.60.1.014105
Fiber-to-chip light coupling using a graded-index (GRIN) fiber collimator is investigated. Our experiments with grating couplers and strip waveguides fabricated in a photonic integrated circuit technology reveal that the peak coupling efficiency of a GRIN fiber collimator is 7.8 dB lower than that of a single-mode fiber. However, the 3-dB alignment tolerance is improved by a factor of about 5.7 giving rise to pluggable sensor solutions. This work opens a path toward a cost-effective and portable sensor platform based on pluggable photonic biosensors using GRIN fiber collimators.

(4) An Academic Framework for IC Physical Design Algorithms Development
D. Bulakh, A. Korshunov, A. Datsuk
Proc. International Seminar on Electron Devices Design and Production (SED 2021), (2021)
DOI: 10.1109/SED51197.2021.9444528, (Design Kit)

(5) N-Type Ge/Si Antennas for THz Sensing
C.A. Chavarin, E. Hardt, S. Gruessing, O. Skibitzki, I. Costina, D. Spirito, W. Seifert, W.M. Klesse, C.L. Manganelli, C. You, J. Flesch, J. Piehler, M. Missori, L. Baldassarre, B. Witzigmann, G. Capellini
Optics Express 29(5), 7680 (2021)
(DFG-ESSENCE)
Ge-on-Si plasmonics holds the promise for compact and low-cost solutions in the manipulation of THz radiation. We discuss here the plasmonic properties of doped Ge bow-tie antennas made with a low-point cost CMOS mainstream technology. These antennas display resonances between 500 and 700 GHz, probed by THz Time Domain Spectroscopy. We show surface functionalization of the antennas with a thin layer of α-lipoic acid, that red-shifts the antenna resonances by about 20 GHz. Moreover, we show that also antennas covered with a protective silicon nitride cap layer exhibit a comparable red-shift when covered with the biolayer. This suggests that the electromagnetic fields at the hotspot extend well beyond the cap layer, enabling the possibility to use the antennas with an improved protection of the plasmonic material in conjunction with microfluidics.

(6) An Integrated Development Environment for Robust Interoperable PDK Implementation
A. Datsuk, C. Wieden, D. Bulakh, T. Krupkina
Proc. IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus 2021), 2067 (2021)
DOI: 10.1109/ElConRus51938.2021.9396695

(7) A 112 Gb/s Radiation-Hardened Mid-Board Optical Transceiver in 130-nm SiGe BiCMOS for Intra-Satellite Links
S. Giannakopoulos, I. Sourikopoulos, L. Stampoulidis, P. Ostrovskyy, F. Teply, K. Tittelbach-Helmrich, G. Panic, G. Fischer, A. Grabowski, H. Zirath, P. Ayzac, N. Venet, A. Maho, M. Sotom, S. Jones, G. Wood, I. Oxtoby
Frontiers in Physics 9, 672941 (2021)
DOI: 10.3389/fphy.2021.672941, (SIPhoDiAS)
We report the design of a 112 Gb/s radiation-hardened (RH) optical transceiver applicable to intra-satellite optical interconnects. The transceiver chipset comprises a vertical-cavity surface-emitting laser (VCSEL) driver and transimpedance amplifier (TIA) integrated circuits (ICs) with four channels per die, which are adapted for a flip-chip assembly into a mid-board optics (MBO) optical transceiver module. The ICs are designed in the IHP 130 nm SiGe BiCMOS process (SG13RH) leveraging proven robustness in radiation environments and high-speed performance featuring bipolar transistors (HBTs) with fT/fMAX values of up to 250/340 GHz. Besides hardening by technology, radiation-hardened-by-design (RHBD) components are used, including enclosed layout transistors (ELTs) and digital logic cells. We report design features of the ICs and the module, and provide performance data from post-layout simulations. We present radiation evaluation data on analog devices and digital cells, which indicate that the transceiver ICs will reliably operate at typical total ionizing dose (TID) levels and single event latch-up thresholds found in geostationary satellites.

(8) Performance Comparison of Broadband Traveling Wave Amplifiers in 130 nm SiGe:C SG13G2 and SG13G3 BiCMOS Technologies
M. Inac, A. Fatemi, F. Korndörfer, H. Rücker, F. Gerfers, A. Malignaggi
IEEE Microwave and Wireless Components Letters 31(6), 744 (2021)
DOI: 10.1109/LMWC.2021.3067099
In this letter, a comparison between two ultra-wideband traveling wave amplifiers (TWAs) designed in two different SiGe:C technologies consuming only 500 mW is presented. The first design utilizes the IHP’s 130-nm SiGe:C BiCMOS SG13G2 technology, featuring fT /fMAX =300  /500 GHz, while the second design uses the IHP’s 130-nm SiGe:C BiCMOS SG13G3 technology, featuring fT /fMAX =470/700 GHz. For a fair comparison, the same architecture has been used for the design of both amplifiers. On-wafer measurements of the SG13G2 amplifier show 15.3 dB gain and 87.4 GHz bandwidth, while the design in SG13G3 technology reaches 16.9 dB gain and more than 110 GHz bandwidth. There is a 1% difference in the output power efficiency where it is 4.1% and 5.1% on SG13G2 and SG13G3 technologies, respectively. In both cases, time-domain measurements show a reliable 120 Gbps non-return-to-zero (NRZ) operation. The presented SG13G3-based TWA shows state-of-the-art performance among similar SiGe BiCMOS amplifiers.

(9) Silicon Electronic-Photonic Integrated 25-Gb/s Ring Modulator Transmitter with a Built-In Temperature Controller
M. Kim, M.-H. Kim, Y. Jo, H.-K. Kim, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
Photonics Research 9(4), 507 (2021)
DOI: 10.1364/PRJ.413407
We demonstrate a silicon electronic-photonic integrated 25-Gb/s non-return-to-zero transmitter that includes driver circuits, depletion-type Si ring modulator, Ge photodetector, temperature sensor, on-chip heater, and temperature controller, all monolithically integrated on 0.25-μm photonic BiCMOS technology platform. The integrated transmitter successfully provides stable and optimal 25-Gb/s modulation characteristics against any external temperature fluctuation.

(10) Terahertz Signal Source and Receiver Operating Near 600 GHz and their 3-D Imaging Application
J. Kim, D. Yoon, H. Son, D. Kim, J. Yoo, J. Yun, H.J. Ng, M. Kaynak, J.-S. Rieh
IEEE Transactions on Microwave Theory and Techniques 69(5), 2762 (2021)
DOI: 10.1109/TMTT.2021.3061596
In this article, a set of oscillators and a heterodyne image receiver operating near 600 GHz have been developed, each based on a 250-nm InP heterojunction bipolar transistor (HBT) technology and a 130-nm SiGe HBT technology, respectively. The oscillators are based on the common-base cross-coupled push-push topology, which employed coupled-line loads for improved output power and efficiency with a small area. The measured oscillation frequency ranges of the three oscillators with different coupled-line lengths were 628-682, 556-610, and 509-548 GHz, respectively, with a tuning capability achieved with bias variation. The maximum output power and the dc-to-RF efficiency achieved with the oscillators were -10 dBm and 0.19%, respectively. The heterodyne receiver, which consists of a mixer, an IF amplifier, and an IF detector, exhibited a maximum responsivity of 469 kV/W and a minimum noise equivalent power (NEP) of 0.64 pW/Hz1/2. A transmission-mode 3-D THz tomography imaging setup was established with one of the fabricated oscillators and the heterodyne receiver employed as the signal source and the image detector, respectively. With the imaging setup, a successful reconstruction of 3-D images of a target object was demonstrated based on the filtered back-projection algorithm.

(11) Si Photonic-Electronic Monolithically Integrated Optical Receiver with a Built-In Temperature-Controlled Wavelength Filter
H.-K. Kim, M. Kim, M.-H. Kim, Y. Jo, St. Lischke, Ch. Mai, L. Zimmermann, W. Choi
Optics Express 29(6), 9565 (2021)
DOI: 10.1364/OE.418222
We present a Si photonic-electronic integrated ring-resonator based optical receiver that contains a temperature-controlled ring-resonator filter (RRF), a Ge photodetector, and receiver circuits in a single chip. The temperature controller automatically determines the RRF temperature at which the maximum transmission of the desired WDM signal is achieved and maintains this condition against any temperature or input wavelength fluctuation. This Si photonic-electronic integrated circuit is realized with 0.25-µm photonic BiCMOS technology, and its operation is successfully confirmed with measurement.

(12) Plasmonics - High-Speed Photonics for Co-Integration with Electronics
U. Koch, C. Uhl, H. Hettrich, Y. Fedoryshyn, D. Moor, M. Baumann, C. Hoessbacher, W. Heni, B. Baeuerle, B.I. Bitachon, A. Josten, M. Ayata, H. Xu, D.L. Elder, L.R. Dalton, E. Mentovich, P. Bakopoulos, St. Lischke, A. Krüger, L. Zimmermann, D. Tsiokos, N. Pleros, M. Möller, J. Leuthold
Japanese Journal of Applied Physics 60(SB), SB0806 (2021)
DOI: 10.35848/1347-4065/abef13
New high-speed photonic technologies and co-integration with electronics are required to keep up with the demand of future optical communication systems. In this paper, plasmonics is presented as one of the most promising next-generation photonic technologies that already fulfils these requirements in proof-of-concept demonstrations. Plasmonics features not only modulators and detectors of highest speed, but also compactness, cost- and energy-efficiency, and compatibility with CMOS electronics. Recently, co-integration with electronics was demonstrated with record performances of 222 GBd in a hybrid InP electronic-plasmonic transmitter assembly and of 120 GBd with a monolithic BiCMOS electronic-plasmonic transmitter.

(13) Epitaxial GeSn/Ge Vertical Nanowires for P-Type Field-Effect Transistors with Enhanced Performance
M. Liu, D. Yang, A. Shkurmanov, J.H. Bae, V. Schlykow, J.-M. Hartmann, Z. Ikonic, F. Bärwolf, I. Costina, A. Mai, J. Knoch, D. Grützmacher, D. Buca, Q.-T. Zhao
ACS Applied Nano Materials 4(1), 94 (2021)
DOI: 10.1021/acsanm.0c02368
Harvesting the full potential of single-crystal semiconductor nanowires (NWs) for advanced nanoscale field-effect transistors (FETs) requires a smart combination of charge control architecture and functional semiconductors. In this article, high-performance vertical gate-all-around NW p-type FETs (p-FETs) are presented. The device concept is based on advanced Ge0.92Sn0.08/Ge group IV epitaxial heterostructures, employing quasi–one-dimensional semiconductor NWs fabricated with a top-down approach. The advantage of using a heterostructure is the possibility of electronic band engineering with band offsets tunable by changing the semiconductor stoichiometry and elastic strain. The use of a Ge0.92Sn0.08 layer as the source in GeSn/Ge NW p-FETs results in a small subthreshold slope of 72 mV/dec and a high ION/IOFF ratio of 3 × 106. A ∼32% drive current enhancement is obtained compared to the vertical Ge homojunction NW control devices. More interestingly, the drain-induced barrier lowering is much smaller with GeSn instead of Ge as the source. The general improvement of the transistor’s key figures of merits originates from the valence band offset at the Ge0.92Sn0.08/Ge heterojunction, as well as from a smaller NiGeSn/GeSn contact resistivity.

(14) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (NeuroMem)

(15) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (Total Resilience)

(16) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (KI-PRO)

(17) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
(NeuroMem)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.

(18) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
(Total Resilience)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.

(19) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
(KI-PRO)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.

(20) A High-Gain SiGe BiCMOS LNA for 5G In-Band Full-Duplex Applications
T.A. Ozkan, A. Burak, I. Kalyoncu, M. Kaynak, Y. Gurbuz
Proc. 15th European Microwave Integrated Circuits Conference (EuMIC 2020), 53 (2021)

(21) A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells
S. Pechmann, T. Mai, M. Völkel, M.K. Mahadevaiah, E. Perez, E. Perez-Bosch Quesada, M. Reichenbach, Ch. Wenger, A. Hagelauer
Electronics (MDPI) 10(5), 530 (2021)
(KI-PRO)
In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.

(22) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (KI-PRO)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.

(23) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (Neutronics)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.

(24) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (Total Resilience)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.

(25) Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
E. Pérez-Bosch Quesada, R. Romero-Zaliz, E. Perez, M.K. Mahadevaiah, J. Reuben, M.A. Schubert, F. Jimenez-Molinos, J.B. Roldan, Ch. Wenger
Electronics (MDPI) 10(6), 645 (2021)
(KI-PRO)
In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.

(26) Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
E. Pérez-Bosch Quesada, R. Romero-Zaliz, E. Perez, M.K. Mahadevaiah, J. Reuben, M.A. Schubert, F. Jimenez-Molinos, J.B. Roldan, Ch. Wenger
Electronics (MDPI) 10(6), 645 (2021)
(NeuroMem)
In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.

(27) Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
E. Pérez-Bosch Quesada, R. Romero-Zaliz, E. Perez, M.K. Mahadevaiah, J. Reuben, M.A. Schubert, F. Jimenez-Molinos, J.B. Roldan, Ch. Wenger
Electronics (MDPI) 10(6), 645 (2021)
(Total Resilience)
In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.

(28) Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays
E. Perez, M.K. Mahadevaiah, E. Perez-Bosch Quesada, Ch. Wenger
IEEE Transactions on Electron Devices 68(6), 2693 (2021)
DOI: 10.1109/TED.2021.3072868, (Total Resilience)
Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm
to employ should be based on the specific application targeted for the RRAM array.

(29) Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays
E. Perez, M.K. Mahadevaiah, E. Perez-Bosch Quesada, Ch. Wenger
IEEE Transactions on Electron Devices 68(6), 2693 (2021)
DOI: 10.1109/TED.2021.3072868, (Neutronics)
Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm
to employ should be based on the specific application targeted for the RRAM array.

(30) Reliable Technology Evaluation of SiGe HBTs and MOSFETs: fMAX Estimation from Measured Data
B. Saha, S. Fregonese, B. Heinemann, P. Scheer, P. Chevalier, K. Aufinger, A. Chakravorty, T. Zimmer
IEEE Electron Device Letters 42(1), 14 (2021)
DOI: 10.1109/LED.2020.3040891, (Taranto)
Maximumoscillation frequency (fMAX) of mmwave transistors is one of the key figures of merit (FOMs) for evaluating the HF-performance of a given technology. However, accurate measurements of fMAX are very difficult. Determination of fMAX is significantly affected by the measurement uncertainties in the admittance (y) parameters. In order to get rid of the random measurement error and to obtain a reliable and stable fMAX value, the frequency dependent y-parameters are described by rational functions formulated from the small-signal hybrid -model of the transistor under investigation. The parameters of these functions are determined following a least square error technique that minimizes the functional error with the measured data. The approach is especially useful for a fast and reliable evaluation of fMAX value. Devices from two different SiGe and an FDSOI (Fully Depleted Silicon On Insulator) MOS technology are measured and stable fMAX values are estimated following this approach.

(31) JICG CMOS Transistors for Reduction of Total Ionizing Dose and Single Event Effects in a 130 nm Bulk SiGe BiCMOS Technology
R. Sorge, J. Schmidt, Ch. Wipf, F. Reimer, F. Teply, F. Korndörfer
Nuclear Instruments and Methods in Physics Research Section A 987, 164832 (2021)
DOI: 10.1016/j.nima.2020.164832, (Total Resilience)
We report on a novel radiation hardening by design (RHBD) approach for mitigation of total ionization dose (TID) induced drain leakage currents and single event transient (SET) in digital circuits fabricated in a 130 nm bulk SiGe BiCMOS technology. In order to avoid significant TID induced increase of drain leakage currents for NMOS transistors and channel pinch-off for PMOS transistors due to positive charges trapped at the lateral shallow trench insulator silicon interface we introduced junction isolation (JI) for the lateral MOS channel regions. The device construction measures applied also support to suppress the generation SETs. The tolerance of JI MOS transistors against TID induced drain leakage currents was verified up to a TID > 1.3 Mrad(Si). SET tests performed at four different inverter types varying in the arrangement the deep well in the layout. For CMOS inverters with isolated NMOS transistors a LET threshold > 130 MeV cm2 mg−1 was obtained.

(32) Silicon-Organic Hybrid Photonics: An Overview of Recent Advances, Electro-Optical Effects and CMOS-Integration Concepts
P. Steglich, Ch. Mai, C. Villringer, B. Dietzel, S. Bondarenko, V. Ksianzou, F. Villasmunta, C. Zesch, S. Pulwer, M. Burger, J. Bauer, F. Heinrich, S. Schrader, F. Vitale, F. De Matteis, P. Prosposito, M. Casalboni, A. Mai
Journal of Physics: Photonics 3(2), 022009 (2021)
DOI: 10.1088/2515-7647/abd7cf
In the last decades, much research effort has been invested to develop photonic integrated circuits and the silicon-on-insulator technology was established as reliable platform for highly scalable silicon-based electro-optical modulators. However, the device performance of such devices is restricted by the inherent material properties of silicon. A perspective approach to overcome these deficiencies is the integration of organic materials with exceptional high optical nonlinearities into a silicon-on-insulator photonic platform. Silicon-organic hybrid photonics has been shown to overcome drawbacks of silicon-based modulators in terms of operation speed, bandwidth and energy consumption. This work reviews recent advances in silicon-organic hybrid photonics and covers latest improvements of single components and device concepts. Special emphasis is given to the in-device performance of novel electro-optical polymers and the use of different electro-optical effects such as the linear and quadratic electro-optical effect as well as the electric field-induced linear electro-optical effect. Finally, the inherent challenges of implementing nonlinear optical polymers into a silicon photonic platform are discussed and a perspective for future directions is given.

(33) Analysis of BTO-on-Si-Waveguides for Energy-Efficient Electro-Optical Modulators
P. Steglich, A. Mai
Proc. SPIE Integrated Optics: Design, Devices, Systems and Applications VI (2021), 11775, 117750L (2021)
DOI: 10.1117/12.2592501

(34) A Monolithically Integrated Microfluidic Channel in a Silicon-based Photonic-Integrated-Circuit Technology for Biochemical Sensing
P. Steglich, M. Paul, Ch. Mai, A. Böhme, S. Bondarenko, M.G. Weller, A. Mai
Proc. SPIE Optical Sensors (2021), 11772, 1177206 (2021)
DOI: 10.1117/12.2588791

(35) Designs Break Bandwidth Record
U. Troppenz, J. Kreißl
Nature Photonics 15, 4 (2021)
DOI: 10.1038/s41566-020-00739-x
Two independent reports of directly modulated lasers with bandwidths of >60 GHz may help bring data rates beyond 200 Gb s–1 to low-cost optical communication systems. Key to the successes has been managing photonic feedback effects within the laser cavities.

(36) Quantitative Scanning Microwave Microscopy of Few-Layer Platinum Diselenide
X. Wang, K. Xiong, L. Li, J.C.M. Hwang, X. Jin, G. Fabi, M. Farina, O. Hartwig, M. Prechtl, G.S. Düsberg, A. Göritz, M. Wietstruck, M. Kaynak
Proc. 50th European Microwave Conference (EuMC 2020), 987 (2021)

(37) BiCMOS Through-Silicon Via (TSV) Signal Transition at 240/300 GHz for MM-Wave & Sub-THz Packaging and Heterogeneous Integration
M. Wietstruck, St. Marschmeyer, Ch. Wipf, M. Stocchi, M. Kaynak
Proc. 50th European Microwave Conference (EuMC 2020), 244 (2021)

(38) Threading Dislocation Reduction of Ge by Introducing a SiGe / Ge Superlattice
Y. Yamamoto, C. Corley, M.A. Schubert, M.H. Zoellner, B. Tillack
ECS Journal of Solid State Science and Technology 10(3), 034005 (2021)
DOI: 10.1149/2162-8777/abea5e
The influence of introducing a SiGe / Ge superlattice (SL) between Ge layers and Si sbstrate for the sake of the reduction of the threading dislocation density (TDD) without additional anealing is investigated. By introducing the SiGe / Ge SL, the TDD of the Ge surface becomes ~1/3. In the case of 2.8 μm thick Ge without introducing the SiGe / Ge SL, the TDD at the surface is 7.6×108 cm-2. A slight TDD reduction is observed by introducing a Si0.2Ge0.8 / Ge SL between the Si substrate and the Ge layer. By inserting 5, 10 and 20 cycles of Si0.2Ge0.8 / Ge, the TDD is reduced to 7.1×108, 5.9×108 and 5.3×108 cm-2, respectively. The lateral lattice parameters of these SLs are ~5.656Å, which is a smaller value compared to that of bulk Ge, indicating plastic relaxation by misfit dislocation (MD) formation. Further TDD reduction is realized with increasing Si concentration in the SiGe / Ge SL without changing the cycle of the SL. However, surface roughening due to pit formation occurs if the Si concentration in the SL is higher than 50% because of increased strain at the interfaces between SiGe and Ge. With increasing SiGe and Ge thickness ratio in the SL layer and maintaining periodicity and cycles, the TDD is reduced to 2.8×108 cm-2 without degrading the surface roughness. This improvement is related to a relaxation of the SiGe/Ge SL by plastic deformation.

(39) Threading Dislocation Reduction of Ge by Introducing a SiGe/Ge Superlattice
Y. Yamamoto, C. Corley, M.A. Schubert, M.H. Zoellner, B. Tillack
ECS Journal of Solid State Science and Technology 10(3), 034005 (2021)
DOI: 10.1149/2162-8777/abea5e
The influence of introducing a SiGe/Ge superlattice (SL) between Ge layers and Si substrate for the sake of the reduction of the threading dislocation density (TDD) without additional annealing is investigated. By introducing the SiGe/Ge SL and optimizing the layer stack, the TDD of the Ge layer becomes ~1/3. In the case of 2.8 μm thick Ge without introducing the SiGe/Ge SL, the TDD at the surface is 7.6 × 10cm−2. A slight TDD reduction is observed by introducing a Si0.2Ge0.8/Ge SL between the Si substrate and the Ge layer. By inserting 5, 10 and 20 cycles of Si0.2Ge0.8/Ge, the TDD is reduced to 7.1 × 108, 5.9 × 108 and 5.3 × 108 cm−2, respectively. The lateral lattice parameters of these SLs are ~5.656 Å, which is a smaller value compared to that of bulk Ge, indicating plastic relaxation by misfit dislocation formation. Further TDD reduction is realized with increasing Si concentration in the SiGe/Ge SL without changing the cycle of the SL. However, surface roughening due to pit formation occurs if the Si concentration in the SL is higher than 50% because of increased strain at the interfaces between SiGe and Ge. With increasing SiGe and Ge thickness ratio in the SL layer and maintaining periodicity and cycles, the TDD is reduced to 2.8 × 108 cm−2 without degrading the surface roughness. This improvement is related to a relaxation of the SiGe/Ge SL by plastic deformation.

(40) SiGe HBTs and BiCMOS Technology for Present and Future Millimeter-Wave Systems
T. Zimmer, J. Böck, F. Buchali, P. Chevalier, M. Collisi, B. Debaillie, M. Deng, P. Ferrari, S. Fregonese, C. Gaquiere, H. Ghanem, H. Hettrich, A. Karakuzulu, T. Maiwald, M. Margalef-Rovira, C. Maye, M. Möller, A. Mukherjee, H. Rücker, P. Sakalas, R. Schmid, K. Schneider, K. Schuh, W. Templ, A. Visweswaran, T. Zwick
IEEE Journal of Microwaves 1(1), 288 (2021)
DOI: 10.1109/JMW.2020.3031831
This paper gives an overall picture from BiCMOS technologies up to THz systems integration, which were developed in the European Research project TARANTO. The European high performance BiCMOS technology platforms are presented, which have special advantages for addressing applications in the submillimeter-wave and THz range. The status of the technology process is reviewed and the integration challenges are examined. A detailed discussion on millimeter-wave characterization and modeling is given with emphasis on harmonic distortion analysis, power and noise figure measurements up to 190 GHz and 325 GHz respectively and S-parameter measurements up to 500 GHz. The results of electrical compact models of active (HBTs) and passive components are presented together with benchmark circuit blocks for model verification. BiCMOS-enabled systems and applications with focus on future wireless communication systems and high-speed optical transmission systems up to resulting net data rates of 1.55 Tbit/s are presented.

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