Open Source PDK in 130nm BiCMOS, developed for Analog/Digital, Mixed Signal and RF ASIC Design
- Provide low threshold access to technology & PDK for chip designer, open EDA software developer & academic projects
- Simplify access to education material for chip designer
- Be a pioneer in demonstrating the possibilities of open source EDA software and convincing commercial fabs to support the open source approach
- Initiate cooperation's and joint projects with open source community
- Support chip design for small design projects/companies
- IHP Open Source PDK project goal is to provide a fully open source Process Design Kit and related data, which can be used to create manufacturable designs at IHP’s facility.
- Push German Microelectronic Academy – Develop Certified Design Courses & Design Infrastructure using open source software
- Support of open source design flow development with Free Area in MPW Runs (chip designs for non-economic activities, such as university education, research projects)
Within the project there will be two established open source digital design flows that can be used with the IHP Open Source PDK. While the OpenROAD flow is already supported, the setup for the OpenLane flow will be provided within 2024.
An open source analog flow based on xschem, ngspice and klayout is currently under development. To enable the development of RF designs QUCS-S and OpenEMS will be supported. A second flow that supports Magic is planned for 2025.
Current status – Early Access
The GitHub repository containing the PDK data for SG13G2 BiCMOS technology is already accessible. Next to this there is an independent GitHub repository for open source designs created with the IHP OpenPDK. User from open source community can use and contribute designs in this way easily.
The current PDK data is accessible as an early access version exclusively. Although the SG13G2 technology and the commercial PDK have already been used for development of many designs, the open-source PDK is not yet scheduled for production purpose at this time, but in development.
- 0.13 μm CMOS process
- SiGe:C npn-HBT’s
- up to 350 GHz transition frequency
- 450 GHz oscillation frequency
- 2 gate oxides:
- thin gate oxide for 1.2 V digital logic
- thick oxide for 3.3 V supply voltage
- NMOS, PMOS and isolated NMOS transistors
- poly silicon resistors
- MIM capacitors
- 5 thin metal layers
- 2 thick metal layers (2 and 3 μm thick)
- MIM layer
- LimitedBase cell set of standard logic cells
- LEF, Tech LEF
- SPICE Netlist
- SRAM cells in 6 configurations (64x64, 256x48, 256x64, 512x64, 1024x64, 2048x64)
- Primitive devices: GDSII
- KLayout: layer property & tech files, DRC rules (minimum rule set), parameterized cells
- xschem: device symbols, settings, testbenches
- ngspice/Xyce models of HBT/MOS/Passive devices
- OpenEMS: tutorials, scripts, documentation
- SG13G2 Process specification & Layout Rules
- HBT/MOS Measurement data
- GDS Test structures
- Project Roadmap Gantt chart
Contacting IHP (Open Source PDK)
If you would like more information about the open-source PDK and software development in SG13G2 technology or would like to support the project, please send an e-mail to <openpdk(at)ihp-microelectronics.com>.
Thanks to various publicly funded German projects:
The IHP Open Source PDK is released under the Apache 2.0 license.
The copyright details are:
Copyright 2023 IHP PDK Authors
Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
You may obtain a copy of the License at https://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.See the License for the specific language governing permissions and limitations under the License.