The Neuromorphic Hardware Group, as part of the System Architectures Department, targets the development of disruptive neuromorphic hardware adopting CMOS- and emerging technology-based circuits for implementing a wide range of edge AI applications. In more detail, the Group aims the design of highly reliable AI-architectures requiring high performance and quality with restrict constraints in terms of area and power consumption.
The Neuromorphic Hardware Group assumes a multidisciplinary & interdisciplinary approach that integrates activities related different subjects, such as device technology as well as circuit and architecture design for edge AI applications. The requirements and constraints associated to edge AI applications demand the integration of not only CMOS- but also emerging technology-based circuits and architectures. This heterogeneity increases significantly hardware design’s complexity. In this context, a holistic approach considering all lifecycles phases as well as assuming all abstraction levels, from device, through circuit and architecture, to system is considered mandatory in order to guarantee the implementation highly reliable neuromorphic hardware.
Finally, the Neuromorphic Hardware Group assumes a holistic approach based on a multidisciplinary & interdisciplinary perspective connecting activities from all IHP departments, Material Research, Technology, Circuit Design and Wireless Systems.
Research topics
- Neuromorphic hardware design including digital and analog CMOS- and emerging technology-based circuits
- Heterogeneous hardware integration for edge AI applications
- Neuromorphic Hardware Design flow
- Digital and analog Computation in Memory (CiM) architectures
- Emerging technology-based memories
- Manufacturing test strategies for high quality neuromorphic hardware
- Reliability- and power-aware design of neuromorphic hardware assuming device, circuit and architecture abstraction levels
- Lifecycle management strategies for neuromorphic hardware
- Fault mitigation and tolerance strategies for CMOS- and emerging technology-based circuits and architectures
- Reliability-aware AI application development assuming hardware characteristics and constrains
- Reliability assessment strategies for AI applications
- NNs and SNNs algorithms for computing-intensive applications
