Dependable Computing

The Dependable Computing Group develops robust, secure and fault-tolerant hardware systems for demanding edge and infrastructure applications such as satellite and space communication, 6G networks, autonomous systems, industrial robotics and medical technology.

In these domains, systems must deliver high performance while operating reliably and securely under radiation, aging, environmental stress and potential physical attacks. We therefore design dependability as an intrinsic system property — from circuit level to complete Systems on Chip with specialized accelerators and communication offload engines.

Main Targets

  • dependable and secure processor-based SoC platforms
  • co-design of fault tolerance, security and performance
  • automated “dependability-by-design” system generation
  • reliable accelerators for communication, sensing and AI
  • open and reusable hardware ecosystems

Research Topics

Architectures & Automation

  • adaptive multi-core and heterogeneous SoC architectures with focus on open-source platforms
  • resilient interconnects and DPU-style offload subsystems
  • generator-based flows with built-in hardening

Fault Tolerance

  • redundancy and selective hardening
  • radiation/aging mitigation and monitoring
  • fault injection and adaptive reconfiguration

Hardware Security

  • side-channel and fault-injection resistant crypto hardware
  • secure roots of trust and protected data paths
  • security-aware RTL and library methodologies

Group Development and Focus

The Dependable Computing Group combines expertise in hardware reliability and physical security across all abstraction levels — from device physics and circuit design to RTL implementation and system architecture. This enables a unified treatment of non-malicious hardware faults and adversarial attack mechanisms.

We develop resilient multi-core and heterogeneous SoC platforms in which hardening strategies, fault tolerance mechanisms and security countermeasures are integrated consistently from technology to architecture.

By aligning circuit-level effects, implementation techniques and architectural design, the group establishes a coherent engineering approach to dependable hardware platforms for advanced communication, sensing and edge computing systems.

Dr. Markus Ulbricht

IHP
Im Technologiepark 25
15236 Frankfurt (Oder)
Germany

Phone: +49 335 5625 467
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Secretary:
Heike Wasgien
Phone: +49 335 5625 342
Fax: +49 335 5625 671 
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Dalia Hayek
Phone: +49 335 5625 518
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Research results

Research results

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