The Dependable Computing Group develops robust, secure and fault-tolerant hardware systems for demanding edge and infrastructure applications such as satellite and space communication, 6G networks, autonomous systems, industrial robotics and medical technology.
In these domains, systems must deliver high performance while operating reliably and securely under radiation, aging, environmental stress and potential physical attacks. We therefore design dependability as an intrinsic system property, from circuit level to complete Systems on Chip with specialized accelerators and communication offload engines.
The Dependable Computing Group combines expertise in hardware reliability and physical security across all abstraction levels — from device physics and circuit design to RTL implementation and system architecture. This enables a unified treatment of non-malicious hardware faults and adversarial attack mechanisms.
Research Relevance and Application Areas
Dependable computing is becoming increasingly important as computing systems move into safety-critical, autonomous and highly distributed environments. In applications such as satellite and space communication, 6G networks, autonomous systems, industrial robotics and medical technology, hardware must continue to operate reliably and securely despite radiation, component aging, environmental stress, hardware faults and deliberate physical attacks.
Our research addresses these challenges by treating reliability, security and performance as interconnected system properties. By integrating hardening, fault tolerance and security mechanisms from technology and circuit level through to system architecture, we enable resilient and trustworthy hardware platforms for future communication, sensing, AI and edge computing applications.
Main Research Objectives
We develop resilient multi-core and heterogeneous SoC platforms in which hardening strategies, fault tolerance mechanisms and security countermeasures are integrated consistently from technology to architecture.
By aligning circuit-level effects, implementation techniques and architectural design, the group establishes a coherent engineering approach to dependable hardware platforms for advanced communication, sensing and edge computing systems.
Our main objectives include
- dependable and secure processor-based SoC platforms
- co-design of fault tolerance, security and performance
- automated “dependability-by-design” system generation
- reliable accelerators for communication, sensing and AI
- open and reusable hardware ecosystems
Research Areas
Architectures and Automation
The group investigates adaptive multi-core and heterogeneous SoC architectures with focus on open-source platforms, resilient interconnects and DPU-style offload subsystems, as well as generator-based flows with built-in hardening. It develops resilient multi-core and heterogeneous SoC platforms in which hardening strategies, fault tolerance mechanisms and security countermeasures are integrated consistently from technology to architecture.
Fault Tolerance
Research in fault tolerance focuses on redundancy and selective hardening, radiation/aging mitigation and monitoring, as well as fault injection and adaptive reconfiguration. These approaches support the development of hardware systems that can maintain reliable operation under physical degradation, environmental stress and hardware faults.
Hardware Security
Research in hardware security covers side-channel and fault-injection resistant crypto hardware, secure roots of trust and protected data paths, as well as security-aware RTL and library methodologies. The aim is to protect hardware platforms against physical attacks while integrating security consistently with reliability and performance requirements.
Cross-Layer Dependability
By aligning circuit-level effects, implementation techniques and architectural design, the group establishes a coherent engineering approach to dependable hardware platforms for advanced communication, sensing and edge computing systems. This cross-layer approach connects the group’s work on architectures, fault tolerance and hardware security across the complete hardware design stack.
Projects
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COREnext >> click here <<
COREnext builds a computing platform for 6G use cases to ensure European digital sovereignty and economic perspective in this societally critical domain. To surpass competing non-European offerings, COREnext anticipates future needs and focuses on two key gaps, which those vendors are not addressing: energy efficiency by employing use-case-specific disaggregated accelerators, and end-to-end trustworthiness from analogue interface to digital processing, by integrating hardware trust anchors to enforce isolation.
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Scale4Edge >> click here <<
Scale4Edge will create an ecosystem for a scalable and extendable edge-computing platform based on the RISC-V instruction set. The ecosystem will cover all relevant aspects, i.e. low-power, safety, security, reliability, verification, test, compiler, software libraries and debugging supplemented by specification, verification plans and documentation. It will therefore provide a fully scalable and customizable solution including support. This also comprises standard compliant design flows, partially open-source software, and covers safety and security of the platform as well as exhaustive evaluation and analysis of its development. The RISC-V platform of the ecosystem offers three implementation levels to the user: (l) CPU instruction level defined by the RISC-V-ISA standard, (2) Software level defined by C-standard and extensions like MISRA-C and (3) Operation system level with system services, resource allocation and configuration interfaces.
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Export-free Rad-hard Microcontroller for Space Applications ‒ MORAL >> click here <<
The MORAL project has two main goals. The first goal is to develop a completely European, ITAR (International Traffic in Arms Regulations) free microcontroller for space applications, focused on small satellites, flight control and payload computers for the purposes of mission control, earth observation, navigation and many other applications. The processor core of the microcontroller is based on a novel IHP peaktop architecture, including a novel European instruction set. The microcontroller will provide mechanisms for increased reliability and adaptability according to the needs of the space applications. Besides the microcontroller, the required ITAR-free middleware, RTOS (Real Time Operating System) and toolchain will also be available. Achievement of TRL 7 is planned. The second goal is to establish a new European company held by the core consortium partners involved in the project, which will target a trans-continental market. This new company, as the last stage of the evolution of the project, will bring the microcontroller and supporting services to the market. This company will produce the microcontroller, will precisely target the fast growing small satellite market, and thus, the company will bootstrap the European market for space applications.
