De­sign & Test Method­ol­ogy

The re­search group De­sign & Test Method­ol­ogy deals with top­ics in the areas of ASIC de­sign, test meth­ods on chip and wafer, and chip in­te­gra­tion in pack­age or on PCB. This group is fo­cused on pro­vid­ing the ser­vices to in­ter­nal or ex­ter­nal cus­tomers or work­ing on the ap­plied industry-​relevant projects.

Main tar­gets

• chip de­sign & test
• chip in­te­gra­tion

Re­search top­ics

• ASIC de­sign of com­plex dig­i­tal cir­cuits or circuit-​blocks
  • model-​based de­sign method­ol­ogy
  • asyn­chro­nous and GALS de­sign
  • rad­hard ASIC de­sign
  • test of dig­i­tal and mixed-​signal cir­cuits
• bare die mount­ing/wire bond­ing
• PCB As­sem­bly
• rad­hard dig­i­tal in­ter­faces
• rad­hard de­sign of dig­i­tal cir­cuits

Ser­vice

• ASIC de­sign
• test of dig­i­tal and mixed-​signal-SoCs
• PCB de­sign
• chip as­sem­bly