Publications 2023
Script list Publications
(1) Characterization and Modeling of Single Event Transient Propagation through Standard Logic Cells
M. Andjelkovic, M. Krstic
Proc. 35. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 19 (2023)
(6G-TakeOff)
In this paper, the propagation of Single Event Transients (SETs) through standard combinational gates is inves-tigated with electrical simulations. It was shown that significant SET broadening may occur across short combinational paths. By fitting the simulation results, a predictive model for estimating the SET pulse broadening and shrinking caused by individual logic gates has been derived. The proposed model estimates the propagated SET pulse width in terms of gate’s driving strength, load capacitance, supply voltage and temperature. The model was verified on selected short combinational paths, and the rela-tive error with respect to simulations was less than 12%.
(2) Image-Rejection Up-/Down-Converter LO Distribution Chain for 5G mm-Wave Phased-Array Systems
A. Franzese, N. Maletic, R. Negra, A. Malignaggi
Proc. IEEE Radio & Wireless Symposium (RWS 2023), 14 (2023)
DOI: 10.1109/RWS55624.2023.10046204, (Taranto)
(3) Multiple Bit Upset-Tolerant EDAC Approach for Robust Embedded Memory Systems Design
R. Goerl, P. Villa, L. Poehls, F. Vargas
Proc. 35. ITG/GMM/GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 61 (2023)
(4) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(Open 6G Hub)
(5) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(IHP - Humboldt-Universität Joint-Lab)
(6) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(AgileHyBeams (HU-B))
(7) Fully Parallel Fully Unrolled BP Decoding of LDPC and Polar Codes
A. Hasani, L. Lopacinski, M. Krstic, E. Grass
Proc. 21st IEEE Wireless Communications and Networking Conference (WCNC 2023), (2023)
DOI: 10.1109/WCNC55385.2023.10118633, (PSSS-FEC)
(8) NLP Powered Intent Based Network Management for Private 5G Networks
J. Mcnamara, D. Camps-Mur, M. Goodarzi, H. Frank, L. Chinchilla-Romero, F. Canellas, A. Fernández-Fernández, S. Yan
IEEE Access 11, 36642 (2023)
DOI: 10.1109/ACCESS.2023.3265894
Intent driven networking holds the promise of simplifying network operations by allowing operators to use declarative, instead of imperative, interfaces. Adoption of this technology for 5G and beyond networks is however still in its infancy, where the required architectures, platforms, interfaces and algorithms are still being discussed. In this work, we present the design and implementation of a novel intent based platform for private 5G networks powered by a Natural Language Processing (NLP) interface. We demonstrate how our platform simplifies network operations in three relevant private network use cases, including: i) an intent based slice provisioning use case, ii) an intent based positioning use case, and iii) an intent based service deployment use case. Finally, all use cases are benchmarked in terms of intent provisioning time.
(9) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (KI-PRO)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(10) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (MIMEC)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(11) Interference Leakage Minimization in RIS-Assisted MIMO Interference Channels
I. Santamaria, M. Soleymani, E. Jorswieck, J. Gutierrez Teran
Proc. International Conference on Acoustics, Speech, & Signal Processing (ICASSP 2023), (2023)
DOI: 10.1109/ICASSP49357.2023.10094656, (6G-RIC)
(12) Towards Reconfigurable CNN Accelerator for FPGA Implementation
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
IEEE Transactions on Circuits and Systems II 70(3), 12496 (2023)
DOI: 10.1109/TCSII.2023.3241154, (Open 6G Hub)
Convolutional Neural Networks (CNNs) have revolutionized many applications in recent years, especially in image classification, video processing, and pattern recognition. This success of CNNs has been a motivating factor for solving even more complex problems involving multiple data modalities. Traditionally, a single CNN accelerator has been optimized for just one task or has been used to perform correlated tasks. We leverage the CNNs capability to learn patterns and use one accelerator to perform multiple uncorrelated tasks from different modalities and achieve an average accuracy above 90%, which would otherwise require three accelerators. Two types of CNN architectures (i.e., fused and branched) are evaluated for three distinct tasks based on accuracy, quantization, pruning, hardware resource utilization, power, and latency. Capitalizing on this, we have further proposed a runtime reconfigurable CNN accelerator supporting fault-tolerant (FT), high-performance (HP), and de-stress (DS) modes.
(13) Towards Reconfigurable CNN Accelerator for FPGA Implementation
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
Proc. 14th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023), 206 (2023)
(Open 6G Hub)
(14) An Approach for Runtime Reconfigurability in Application-Specific CNN Accelerators
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
Proc. 35. ITG/GMM /GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 43 (2023)
(Open 6G Hub)
(15) Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis
M. Ulbricht, J.-C. Chen, L. Lu, M. Krstic, W. Müller
Proc. 35. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 9 (2023)
(Scale4Edge)
(16) COCHISA Approach: European Core-Chip for Space Applications
F. Vargas, C. Corrado, A. Malignaggi, M. Krstic, D. Verploegen, G. Mannocchi, M.Petri, P. Fontana, U. Lewark, R. Follmann, S. Rochette
Proc. 1st ESA/ESTEC Space Microwave Week (2023), (2023)
(COCHISA)
(17) Localization System Architecture for Enhanced Positioning in Industry 4.0 Applications
R. Vasist, V. Sark, M. Goodarzi, J. Gutierrez Teran, E. Grass
Proc. International Conference on Computing, Networking and Communications (ICNC 2023), 683 (2023)
DOI: 10.1109/ICNC57223.2023.10074001, (5G-CLARITY)
(18) Integrating AI Hardware in Academic Teaching: Experiences and Scope from Brandenburg and Bavaria
Z. Xiong, D. Stober, M. Krstić, O. Korup, M.I. Arango,H. Li, M. Werner
ISPRS Annals of the Photogrammetry, Remote Sensing and Spatial Information Sciences 75 (2023)
(BB-KI-Chips)
(19) Low Complexity Radar Gesture Recognition Using Synthetic Training Data
Y. Zhao, V. Sark, M. Krstic, E. Grass
Sensors (MDPI) 23(1), 308 (2023)
DOI: 10.3390/s23010308, (Open 6G Hub)
Developments in radio detection and ranging (radar) technology have made hand gesture recognition feasible. In heat map-based gesture recognition, feature images have a large size and require complex neural networks to extract information. Machine learning methods typically require large amounts of data and collecting hand gestures with radar is time- and energy-consuming. Therefore, a low computational complexity algorithm for hand gesture recognition based on a frequency-modulated continuous-wave (FMCW) radar and a synthetic hand gesture feature generator are proposed. In the low computational complexity algorithm, two-dimensional Fast Fourier Transform is implemented on the radar raw data to generate a range-Doppler matrix. After that, background modelling is applied to separate the dynamic object and the static background. Then a bin with the highest magnitude in the range-Doppler matrix is selected to locate the target and obtain its range and velocity. The bins at this location along the dimension of the antenna can be utilised to calculate the angle of the target using Fourier beam steering. In the synthetic generator, the Blender software is used to generate different hand gestures and trajectories and then the range, velocity and angle of targets are extracted directly from the trajectory. The experimental results demonstrate that the average recognition accuracy of the model on the test set can reach 89.13% when the synthetic data are used as the training set and the real data are used as the test set. This indicates that the generation of synthetic data can make a meaningful contribution in the pre-training phase
(20) Low Complexity Radar Gesture Recognition Using Synthetic Training Data
Y. Zhao, V. Sark, M. Krstic, E. Grass
Sensors (MDPI) 23(1), 308 (2023)
DOI: 10.3390/s23010308, (iCampus)
Developments in radio detection and ranging (radar) technology have made hand gesture recognition feasible. In heat map-based gesture recognition, feature images have a large size and require complex neural networks to extract information. Machine learning methods typically require large amounts of data and collecting hand gestures with radar is time- and energy-consuming. Therefore, a low computational complexity algorithm for hand gesture recognition based on a frequency-modulated continuous-wave (FMCW) radar and a synthetic hand gesture feature generator are proposed. In the low computational complexity algorithm, two-dimensional Fast Fourier Transform is implemented on the radar raw data to generate a range-Doppler matrix. After that, background modelling is applied to separate the dynamic object and the static background. Then a bin with the highest magnitude in the range-Doppler matrix is selected to locate the target and obtain its range and velocity. The bins at this location along the dimension of the antenna can be utilised to calculate the angle of the target using Fourier beam steering. In the synthetic generator, the Blender software is used to generate different hand gestures and trajectories and then the range, velocity and angle of targets are extracted directly from the trajectory. The experimental results demonstrate that the average recognition accuracy of the model on the test set can reach 89.13% when the synthetic data are used as the training set and the real data are used as the test set. This indicates that the generation of synthetic data can make a meaningful contribution in the pre-training phase
M. Andjelkovic, M. Krstic
Proc. 35. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 19 (2023)
(6G-TakeOff)
In this paper, the propagation of Single Event Transients (SETs) through standard combinational gates is inves-tigated with electrical simulations. It was shown that significant SET broadening may occur across short combinational paths. By fitting the simulation results, a predictive model for estimating the SET pulse broadening and shrinking caused by individual logic gates has been derived. The proposed model estimates the propagated SET pulse width in terms of gate’s driving strength, load capacitance, supply voltage and temperature. The model was verified on selected short combinational paths, and the rela-tive error with respect to simulations was less than 12%.
(2) Image-Rejection Up-/Down-Converter LO Distribution Chain for 5G mm-Wave Phased-Array Systems
A. Franzese, N. Maletic, R. Negra, A. Malignaggi
Proc. IEEE Radio & Wireless Symposium (RWS 2023), 14 (2023)
DOI: 10.1109/RWS55624.2023.10046204, (Taranto)
(3) Multiple Bit Upset-Tolerant EDAC Approach for Robust Embedded Memory Systems Design
R. Goerl, P. Villa, L. Poehls, F. Vargas
Proc. 35. ITG/GMM/GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 61 (2023)
(4) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(Open 6G Hub)
(5) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(IHP - Humboldt-Universität Joint-Lab)
(6) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(AgileHyBeams (HU-B))
(7) Fully Parallel Fully Unrolled BP Decoding of LDPC and Polar Codes
A. Hasani, L. Lopacinski, M. Krstic, E. Grass
Proc. 21st IEEE Wireless Communications and Networking Conference (WCNC 2023), (2023)
DOI: 10.1109/WCNC55385.2023.10118633, (PSSS-FEC)
(8) NLP Powered Intent Based Network Management for Private 5G Networks
J. Mcnamara, D. Camps-Mur, M. Goodarzi, H. Frank, L. Chinchilla-Romero, F. Canellas, A. Fernández-Fernández, S. Yan
IEEE Access 11, 36642 (2023)
DOI: 10.1109/ACCESS.2023.3265894
Intent driven networking holds the promise of simplifying network operations by allowing operators to use declarative, instead of imperative, interfaces. Adoption of this technology for 5G and beyond networks is however still in its infancy, where the required architectures, platforms, interfaces and algorithms are still being discussed. In this work, we present the design and implementation of a novel intent based platform for private 5G networks powered by a Natural Language Processing (NLP) interface. We demonstrate how our platform simplifies network operations in three relevant private network use cases, including: i) an intent based slice provisioning use case, ii) an intent based positioning use case, and iii) an intent based service deployment use case. Finally, all use cases are benchmarked in terms of intent provisioning time.
(9) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (KI-PRO)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(10) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (MIMEC)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(11) Interference Leakage Minimization in RIS-Assisted MIMO Interference Channels
I. Santamaria, M. Soleymani, E. Jorswieck, J. Gutierrez Teran
Proc. International Conference on Acoustics, Speech, & Signal Processing (ICASSP 2023), (2023)
DOI: 10.1109/ICASSP49357.2023.10094656, (6G-RIC)
(12) Towards Reconfigurable CNN Accelerator for FPGA Implementation
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
IEEE Transactions on Circuits and Systems II 70(3), 12496 (2023)
DOI: 10.1109/TCSII.2023.3241154, (Open 6G Hub)
Convolutional Neural Networks (CNNs) have revolutionized many applications in recent years, especially in image classification, video processing, and pattern recognition. This success of CNNs has been a motivating factor for solving even more complex problems involving multiple data modalities. Traditionally, a single CNN accelerator has been optimized for just one task or has been used to perform correlated tasks. We leverage the CNNs capability to learn patterns and use one accelerator to perform multiple uncorrelated tasks from different modalities and achieve an average accuracy above 90%, which would otherwise require three accelerators. Two types of CNN architectures (i.e., fused and branched) are evaluated for three distinct tasks based on accuracy, quantization, pruning, hardware resource utilization, power, and latency. Capitalizing on this, we have further proposed a runtime reconfigurable CNN accelerator supporting fault-tolerant (FT), high-performance (HP), and de-stress (DS) modes.
(13) Towards Reconfigurable CNN Accelerator for FPGA Implementation
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
Proc. 14th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023), 206 (2023)
(Open 6G Hub)
(14) An Approach for Runtime Reconfigurability in Application-Specific CNN Accelerators
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
Proc. 35. ITG/GMM /GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 43 (2023)
(Open 6G Hub)
(15) Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis
M. Ulbricht, J.-C. Chen, L. Lu, M. Krstic, W. Müller
Proc. 35. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 9 (2023)
(Scale4Edge)
(16) COCHISA Approach: European Core-Chip for Space Applications
F. Vargas, C. Corrado, A. Malignaggi, M. Krstic, D. Verploegen, G. Mannocchi, M.Petri, P. Fontana, U. Lewark, R. Follmann, S. Rochette
Proc. 1st ESA/ESTEC Space Microwave Week (2023), (2023)
(COCHISA)
(17) Localization System Architecture for Enhanced Positioning in Industry 4.0 Applications
R. Vasist, V. Sark, M. Goodarzi, J. Gutierrez Teran, E. Grass
Proc. International Conference on Computing, Networking and Communications (ICNC 2023), 683 (2023)
DOI: 10.1109/ICNC57223.2023.10074001, (5G-CLARITY)
(18) Integrating AI Hardware in Academic Teaching: Experiences and Scope from Brandenburg and Bavaria
Z. Xiong, D. Stober, M. Krstić, O. Korup, M.I. Arango,H. Li, M. Werner
ISPRS Annals of the Photogrammetry, Remote Sensing and Spatial Information Sciences 75 (2023)
(BB-KI-Chips)
(19) Low Complexity Radar Gesture Recognition Using Synthetic Training Data
Y. Zhao, V. Sark, M. Krstic, E. Grass
Sensors (MDPI) 23(1), 308 (2023)
DOI: 10.3390/s23010308, (Open 6G Hub)
Developments in radio detection and ranging (radar) technology have made hand gesture recognition feasible. In heat map-based gesture recognition, feature images have a large size and require complex neural networks to extract information. Machine learning methods typically require large amounts of data and collecting hand gestures with radar is time- and energy-consuming. Therefore, a low computational complexity algorithm for hand gesture recognition based on a frequency-modulated continuous-wave (FMCW) radar and a synthetic hand gesture feature generator are proposed. In the low computational complexity algorithm, two-dimensional Fast Fourier Transform is implemented on the radar raw data to generate a range-Doppler matrix. After that, background modelling is applied to separate the dynamic object and the static background. Then a bin with the highest magnitude in the range-Doppler matrix is selected to locate the target and obtain its range and velocity. The bins at this location along the dimension of the antenna can be utilised to calculate the angle of the target using Fourier beam steering. In the synthetic generator, the Blender software is used to generate different hand gestures and trajectories and then the range, velocity and angle of targets are extracted directly from the trajectory. The experimental results demonstrate that the average recognition accuracy of the model on the test set can reach 89.13% when the synthetic data are used as the training set and the real data are used as the test set. This indicates that the generation of synthetic data can make a meaningful contribution in the pre-training phase
(20) Low Complexity Radar Gesture Recognition Using Synthetic Training Data
Y. Zhao, V. Sark, M. Krstic, E. Grass
Sensors (MDPI) 23(1), 308 (2023)
DOI: 10.3390/s23010308, (iCampus)
Developments in radio detection and ranging (radar) technology have made hand gesture recognition feasible. In heat map-based gesture recognition, feature images have a large size and require complex neural networks to extract information. Machine learning methods typically require large amounts of data and collecting hand gestures with radar is time- and energy-consuming. Therefore, a low computational complexity algorithm for hand gesture recognition based on a frequency-modulated continuous-wave (FMCW) radar and a synthetic hand gesture feature generator are proposed. In the low computational complexity algorithm, two-dimensional Fast Fourier Transform is implemented on the radar raw data to generate a range-Doppler matrix. After that, background modelling is applied to separate the dynamic object and the static background. Then a bin with the highest magnitude in the range-Doppler matrix is selected to locate the target and obtain its range and velocity. The bins at this location along the dimension of the antenna can be utilised to calculate the angle of the target using Fourier beam steering. In the synthetic generator, the Blender software is used to generate different hand gestures and trajectories and then the range, velocity and angle of targets are extracted directly from the trajectory. The experimental results demonstrate that the average recognition accuracy of the model on the test set can reach 89.13% when the synthetic data are used as the training set and the real data are used as the test set. This indicates that the generation of synthetic data can make a meaningful contribution in the pre-training phase
