Publications 2023
Script list Publications
(1) Non-Profiled Semi-Supervised Horizontal Attack Against Elliptic Curve Scalar Multiplication using Support Vector Machines
M. Aftowicz, I. Kabin, Z. Dyka, P. Langendörfer
Proc. 26th Euromicro Conference Series on Digital System Design (DSD 2023), (2023)
(Total Resilience)
(2) Characterization and Modeling of Single Event Transient Propagation through Standard Logic Cells
M. Andjelkovic, M. Krstic
Proc. 35. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 19 (2023)
(6G-TakeOff)
In this paper, the propagation of Single Event Transients (SETs) through standard combinational gates is inves-tigated with electrical simulations. It was shown that significant SET broadening may occur across short combinational paths. By fitting the simulation results, a predictive model for estimating the SET pulse broadening and shrinking caused by individual logic gates has been derived. The proposed model estimates the propagated SET pulse width in terms of gate’s driving strength, load capacitance, supply voltage and temperature. The model was verified on selected short combinational paths, and the rela-tive error with respect to simulations was less than 12%.
(3) Towards a Smart Multi-Sensor Ionizing Radiation Monitoring System
M. Andjelkovic, J.-C. Chen, R.T. Syed, F. Vargas, M. Ulbricht, M. Krstic, S. Ilic, M. Marjanovic, S. Veljkovic, N. Mitrovic, D. Dankovic, G. Ristic, R. Duane, N. Vasovic, A. Jaksic, A. Palma, A. Lallena, M. Carvajal
Proc. 26th Euromicro Conference on Digital System Design (DSD 2023), (2023)
(ELICSIR)
(4) Organic 6G Networks: Vision, Requirements, and Research Approaches
M.-I. Corici, F. Eichhorn, R. Bless, M. Gundall, D. Lindenschmitt, B. Bloessl, M. Petrova, L. Wimmer, R. Kreuch, T. Magedanz, H.D. Schotten
IEEE Access 11, 70698 (2023)
DOI: 10.1109/ACCESS.2023.3293055, (Open 6G Hub)
Building upon the significant number of already published 6G position papers, we are concentrating on the immediate next steps toward turning the research vision of software-centric networks into reality. This is accomplished, by summarizing and assessing the various requirements documents and providing a significant number of specific research directions and approaches in order to fulfill them. This article complements the existing body of work, by focusing on future core networks and their infrastructures, yet maintaining a system-level perspective and progressing in the direction of scoping key technology elements and providing high-potential research approaches for them. Additionally, we rigorously discuss the impact that different technological advancements have on the other parts of the system, to provide a coherent, end-to-end network understanding. This is in strong contrast to current approaches, where from the challenges, each research direction becomes independent and, thus, its advances are potentially cancelled out by the next technology in the chain. By maintaining this system perspective, the adoption of the different technologies becomes easier, as they are developed in unison. To address the requirements in a coherent, holistic, and unified way, we extend our high-level architecture concept named “Organic 6G Networks” towards a comprehensive end-to-end system. A holistic software-centric system, adapting the latest software development advancements from the IT industry. The Organic 6G network provides support for building a streamlined software network architecture and offers the next step on the path towards the development and specification of future mobile networks.
(5) SiGe BiCMOS Technology with Embedded Microchannels based on Cu Pillar PCB Integration Enabling Sub-THz Microfluidic Sensor Applications
E.C. Durmaz, C. Heine, Z. Cao, J. Lehmann, D. Kissinger, M. Wietstruck
Proc. IEEE International 3D System Integration Conference (3DIC 2023), (2023)
DOI: 10.1109/3DIC57175.2023.10155073, (DFG-THz LoC)
(6) The Scale4Edge RISC-V Ecosystem
W. Ecker, P. Adelt, W. Mueller, R. Heckmann, M. Krstic, N. Bruns, R. Drechsler, G. Angst, R. Wimmer, A. Mauderer, D. Mueller-Gritschneder, B. Becker, P. Scholl, E. Jentzsch, J. Schlamelcher, K. Grüttner, P. Palomero Bernardo, O. Bringmann, A. Koch, J. Bormann, J. Partzsch, C. Mayr, W. Kunz
Proc. RISC-V Summit Europe (RSIC-V 2023), (2023)
(Scale4Edge)
(7) Image-Rejection Up-/Down-Converter LO Distribution Chain for 5G mm-Wave Phased-Array Systems
A. Franzese, N. Maletic, R. Negra, A. Malignaggi
Proc. IEEE Radio & Wireless Symposium (RWS 2023), 14 (2023)
DOI: 10.1109/RWS55624.2023.10046204, (Taranto)
(8) Bits, Flips and RISCs
N. Gerlin, E. Kaja, M. Ulbricht, F. Vargas, L. Lu, A. Breitenreiter, J.-C. Chen, M. Gomez, A. Tahiraga, S. Prebeck, E. Jentzsch, M. Krstic, W. Ecker
Proc. 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2023), 140 (2023)
DOI: 10.1109/LMWT.2023.3265861, (Scale4Edge)
(9) Multiple Bit Upset-Tolerant EDAC Approach for Robust Embedded Memory Systems Design
R. Goerl, P. Villa, L. Poehls, F. Vargas
Proc. 35. ITG/GMM/GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 61 (2023)
(10) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(Open 6G Hub)
(11) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(AgileHyBeams (HU-B))
(12) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(IHP - Humboldt-Universität Joint-Lab)
(13) Fully Parallel Fully Unrolled BP Decoding of LDPC and Polar Codes
A. Hasani, L. Lopacinski, M. Krstic, E. Grass
Proc. 21st IEEE Wireless Communications and Networking Conference (WCNC 2023), (2023)
DOI: 10.1109/WCNC55385.2023.10118633, (PSSS-FEC)
(14) Randomized Addressing Countermeasures are Inefficient against Address-Bit SCA
I. Kabin, Z. Dyka, P. Langendörfer
Proc. IEEE International Conference on Cyber Security and Resilience (CSR 2023), 580 (2023)
DOI: 10.1109/CSR57506.2023.10224968, (Total Resilience)
(15) Ultra-High Data-Rate Wireless Access & Sensing Demonstrators in D-Band
K. Krishnegowda, M. Scheide, C. Herold, M. Appel, L. Lopacinski, A. Malignaggi, C. Carta, E. Grass
Proc. European Conference on Networks and Communications & 6G Summit (EUCNC 2023), (2023)
(6G-RIC)
(16) Amplitude- and Phase-Modulated PSSS for Wide Bandwidth Mixed Analog-Digital Baseband Processors in THz Communication
L. Lopacinski, N. Maletic, R. Kraemer, A. Hasani, J. Gutiérrez Teran, M. Krstic, E. Grass
Proc. 97th IEEE Vehicular Technology Conference (VTC 2023), (2023)
DOI: 10.1109/VTC2023-Spring57618.2023.10199923, (PSSS-FEC)
(17) Amplitude- and Phase-Modulated PSSS for Wide Bandwidth Mixed Analog-Digital Baseband Processors in THz Communication
L. Lopacinski, N. Maletic, R. Kraemer, A. Hasani, J. Gutiérrez Teran, M. Krstic, E. Grass
Proc. 97th IEEE Vehicular Technology Conference (VTC 2023), (2023)
DOI: 10.1109/VTC2023-Spring57618.2023.10199923, (6G-RIC)
(18) NLP Powered Intent Based Network Management for Private 5G Networks
J. Mcnamara, D. Camps-Mur, M. Goodarzi, H. Frank, L. Chinchilla-Romero, F. Canellas, A. Fernández-Fernández, S. Yan
IEEE Access 11, 36642 (2023)
DOI: 10.1109/ACCESS.2023.3265894
Intent driven networking holds the promise of simplifying network operations by allowing operators to use declarative, instead of imperative, interfaces. Adoption of this technology for 5G and beyond networks is however still in its infancy, where the required architectures, platforms, interfaces and algorithms are still being discussed. In this work, we present the design and implementation of a novel intent based platform for private 5G networks powered by a Natural Language Processing (NLP) interface. We demonstrate how our platform simplifies network operations in three relevant private network use cases, including: i) an intent based slice provisioning use case, ii) an intent based positioning use case, and iii) an intent based service deployment use case. Finally, all use cases are benchmarked in terms of intent provisioning time.
(19) Techno-Economic Analysis Highlighting Aspects of 5G Network Deployments at Railway Environments
I. Mesogiti, E. Theodoropoulou, F. Setaki, G. Lyberopoulos, K. Stamatis, P.K. Chartsias, N. Makris, P. Flegkas, J. Gutiérrez Teran, C. Politi, C. Tranoris, M. Anastasopoulos, A. Tzanakaki
Proc. International Conference on Artificial Intelligence Applications and Innovations (AIAI 2022), in: Artificial Intelligence Applications and Innovations. AIAI 2023 IFIP WG 12.5 International Workshops, Springer, IFIPAICT 677, 139 (2023)
DOI: 10.1007/978-3-031-34171-7_11, (5G-VICTORI)
(20) GPS-Spoofing Attack Detection Mechanism for UAV Swarms
P. Mykytyn, M. Brzozowski, Z. Dyka, P. Langendörfer
Proc. 11th International Conference on Cyber-Physical Systems and Internet-of-Things (CPS&IoT 2023), 18 (2023)
DOI: 10.1109/MECO58584.2023.10154998, (iCampus)
(21) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (KI-PRO)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(22) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (MIMEC)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(23) Optical Fault Injection Attacks against Different Logic and Memory Cells
D. Petryk, Z. Dyka
Proc. 11th Prague Embedded Systems Workshop (PESW 2023), 24 (2023)
(Total Resilience)
(24) SNR Maximization in Beyond Diagonal RIS-assisted Single and Multiple Antenna Links
I. Santamaria, M. Soleymani, E. Jorswieck, J. Gutierrez Teran
IEEE Signal Processing Letters 30, 923 (2023)
DOI: 10.1109/LSP.2023.3296902, (6G-RIC)
Reconfigurable intelligent surface (RIS) architectures not limited to diagonal phase shift matrices have recently been considered to increase their flexibility in shaping the wireless channel. One of these beyond-diagonal RIS or BD-RIS architectures leads to a unitary and symmetric RIS matrix. In this letter, we consider the problem of maximizing the signal-to-noise ratio (SNR) in single and multiple antenna links assisted by a BD-RIS. The Max-SNR problem admits a closed-form solution based on the Takagi factorization of a certain complex and symmetric matrix. This allows us to solve the max-SNR problem for SISO, SIMO, and MISO channels.
(25) Interference Leakage Minimization in RIS-Assisted MIMO Interference Channels
I. Santamaria, M. Soleymani, E. Jorswieck, J. Gutierrez Teran
Proc. International Conference on Acoustics, Speech, & Signal Processing (ICASSP 2023), (2023)
DOI: 10.1109/ICASSP49357.2023.10094656, (6G-RIC)
(26) Intelligence and Motion Models of Continuum Robots: an Overview
O. Shamilyan, I. Kabin, Z. Dyka, O. Sudakov, A. Cherninsky, M. Brzozowski, P. Langendörfer
IEEE Access 11, 60988 (2023)
DOI: 10.1109/ACCESS.2023.3286300, (Total Resilience)
Many technical solutions are bio-inspired. Octopus-inspired robotic arms belong to continuum robots which are used in minimally invasive surgery or for technical system restoration in areas difficult-to-access. Continuum robot missions are bounded with their motions, whereby the motion of the robots is controlled by humans via wireless communication. In case of a lost connection, robot autonomy is required. Distributed control and distributed decision-making mechanisms based on artificial intelligence approaches can be a promising solution to achieve autonomy of technical systems and to increase their resilience. However these methods are not well investigated yet. Octopuses are the living example of natural distributed intelligence but their learning and decision-making mechanisms are also not fully investigated and understood yet. Mechanisms of Distributed Artificial Intelligence can be investigated using a physical continuum robot prototype that is able to perform some basic movements and combine them into sequences of motions by itself. For the experimental investigations a suitable physical prototype has to be selected, its motion control has to be implemented and automated. In this paper, we give an overview combining different fields of research, such as Distributed Artificial Intelligence and continuum robots based on 97 publications. We provide a detailed description of the basic motion control models of continuum robots based on the literature reviewed, discuss different aspects of autonomy and give an overview of physical prototypes of continuum robots.
(27) Successful Simple Side Channel Analysis: Vulnerability of an Atomic Pattern kP Algorithm Implemented with a Constant Time Crypto Library to Simple Electromagnetic Analysis Attacks
A.A. Sigourou, I. Kabin, P. Langendörfer, N. Sklavos, Z. Dyka
Proc. 12th Mediterranean Conference on Embedded Computing (MECO 2023), 167 (2023)
DOI: 10.1109/MECO58584.2023.10154940, (Total Resilience)
(28) Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation
T. Song, Z. Huang, D. Wang, M. Krstic
Journal of Electronic Testing 39, 189 (2023)
DOI: 10.1007/s10836-023-06057-8
As the ICs become more complex, the duration of high-cost specification tests is increasingly important, especially given the total IC expenditure. In our current work, we propose an adaptive test strategy for reducing the duration of delay testing. This method employs pattern permutation with an ML algorithm to improve the test efficiency, followed by an examination of the effect of test performance, temperature, and voltage on the recognition of path delay defects. SPICE simulations under different voltage and temperature conditions with 65-nm CMOS technology were used to validate it. According to the experimental outcomes, when compared to the random ordering method, the proposed method successfully achieves a nearly 7-fold improvement in test quality at identical testing duration or a 25% reduction in the duration at identical test quality. In addition, the method provides the tester with a thorough understanding of the test efficiency contributions.
(29) High-Speed Optical Transceiver Integrated Chipset and Module for On-Board VCSEL-based Satellite Optical Interconnects
L. Sourikopoulos, G. Winzer, A. Peczek, M. Inac, P. Ostrovskyy, K. Tittelbach-Helmrich, G. Panic, G. Fischer, L. Zimmermann, Y. Franz, S. Jones, P. Kushner, U. Marvet, A. Lujambio, N. Garcia, D. Poudereux, M. Bodega, J. Barbero, L. Stampoulidis
Proc. 14th International Conference on Space Optics (ICSO 2022), 127774K (2023)
DOI: 10.1117/12.2690846, (SIPhoDiAS)
(30) Towards Reconfigurable CNN Accelerator for FPGA Implementation
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
IEEE Transactions on Circuits and Systems II 70(3), 12496 (2023)
DOI: 10.1109/TCSII.2023.3241154, (Open 6G Hub)
Convolutional Neural Networks (CNNs) have revolutionized many applications in recent years, especially in image classification, video processing, and pattern recognition. This success of CNNs has been a motivating factor for solving even more complex problems involving multiple data modalities. Traditionally, a single CNN accelerator has been optimized for just one task or has been used to perform correlated tasks. We leverage the CNNs capability to learn patterns and use one accelerator to perform multiple uncorrelated tasks from different modalities and achieve an average accuracy above 90%, which would otherwise require three accelerators. Two types of CNN architectures (i.e., fused and branched) are evaluated for three distinct tasks based on accuracy, quantization, pruning, hardware resource utilization, power, and latency. Capitalizing on this, we have further proposed a runtime reconfigurable CNN accelerator supporting fault-tolerant (FT), high-performance (HP), and de-stress (DS) modes.
(31) Towards Reconfigurable CNN Accelerator for FPGA Implementation
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
Proc. 14th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023), 206 (2023)
(Open 6G Hub)
(32) A Survey on Fault-Tolerant Methodologies for Deep Neural Networks
R.T. Syed, M. Ulbricht, K. Piotrowski, M. Krstic
Measurement Automation Robotics (Pomiary Automatyka Robotyka) 27(2), 89 (2023)
DOI: 10.14313/PAR_248/89, (Space Region)
A significant rise in Artificial Intelligence (AI) has impacted many applications around us, so much so that AI has now been increasingly used in safety-critical applications. AI at the edge is the reality, which means performing the data computation closer to the source of the data, as opposed to performing it on the cloud. Safety-critical applications have strict reliability requirements; therefore, it is essential that AI models running on the edge (i.e., hardware) must fulfill the required safety standards. In the vast field of AI, Deep Neural Networks (DNNs) are the focal point of this survey as it has continued to produce extraordinary outcomes in various applications .i.e medical, automotive, aerospace, defense, etc. Traditional reliability techniques for DNNs implementation are not always practical, as they fail to exploit the unique characteristics of the DNNs. Furthermore, it is also essential to understand the targeted edge hardware because the impact of the faults can be different in ASICs and FPGAs. Therefore, in this survey, first, we have examined the impact of the fault in ASICs and FPGAs, and then we seek to provide a glimpse of the recent progress made towards the fault-tolerant DNNs. We have discussed several factors that can impact the reliability of the DNNs. Further, we have extended this discussion to shed light on many state-of-the-art fault mitigation techniques for DNNs.
(33) An Approach for Runtime Reconfigurability in Application-Specific CNN Accelerators
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
Proc. 35. ITG/GMM /GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 43 (2023)
(Open 6G Hub)
(34) The TETRISC SoC - A Resilient Quad-Core System based on Pulpissimo
M. Ulbricht, L. Lu, J.-C. Chen, M. Krstic
Proc. RISC-V Summit Europe (2023), (2023)
(Scale4Edge)
(35) The TETRISC SoC - A Resilient Quad-Core System based on the ResiliCell Approach
M. Ulbricht, L. Lu, J.-C. Chen, M. Krstic
Microelectronics Reliability 148, 115173 (2023)
DOI: 10.1016/j.microrel.2023.115173, (Scale4Edge)
Resilient systems require monitoring and prediction of environmental and intrinsic conditions and the ability to adapt to changing circumstances to optimize the trade-off between performance, power consumption, and fault tolerance. This paper presents an approach for enabling a design to achieve resilience. By using a range of reliability sensors and the novel ResiliCells, we have developed the TETRISC System-on-Chip (SoC), which is a multiprocessor system based on the PULPissimo platform. The TETRISC SoC can operate its four cores in different performance and fault tolerance modes based on real-time data, making it ideal for use cases with dynamically changing and reliability critical requirements, such as avionics or aerospace. Additional in-depth studies on possible optimizations demonstrate the flexibility of the ResiliCell approach.
(36) PULP Fiction No More - Dependable PULP Systems for Space
M. Ulbricht, Y. Tortorella, M. Rogenmoser, L. Lu, J.-C. Chen, F. Conti, M. Krstic, L. Benini
Proc. 28th IEEE European Test Symposium (ETS 2023), (2023)
DOI: 10.1109/ETS56758.2023.10174164, (Scale4Edge)
(37) Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis
M. Ulbricht, J.-C. Chen, L. Lu, M. Krstic, W. Müller
Proc. 35. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 9 (2023)
(Scale4Edge)
(38) Artificial Neural Network Accelerator for Classification of In-Field Conducted Noise in Integrated Circuits' DC Power Lines
F. Vargas, D. Borba, J.D. Benfica, R.T. Syed
Proc. 29th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2023), 212 (2023)
DOI: 10.1109/IOLTS59296.2023.10224874
(39) COCHISA Approach: European Core-Chip for Space Applications
F. Vargas, C. Corrado, A. Malignaggi, M. Krstic, D. Verploegen, G. Mannocchi, M. Petri, P. Fontana, U. Lewark, R. Follmann, S. Rochette
Proc. 1st ESA/ESTEC Space Microwave Week (2023), (2023)
(COCHISA)
(40) Localization System Architecture for Enhanced Positioning in Industry 4.0 Applications
R. Vasist, V. Sark, M. Goodarzi, J. Gutierrez Teran, E. Grass
Proc. International Conference on Computing, Networking and Communications (ICNC 2023), 683 (2023)
DOI: 10.1109/ICNC57223.2023.10074001, (5G-CLARITY)
(41) Media Services in Dense, Static and Mobile Environments Leveraging Edge Deployments
M.-E. Xezonaki, N. Psaromanolakis, P. K. Chartsias, K. Stamatis, D. Kritharidis, V. Theodorou, C. Politi, P. Papaioannou, C. Tranoris, S. Denazis, I. Mesogiti, E. Theodoropoulou, F. Setaki, G. Lyberopoulos, N. Makris, P. Flegkas, J. Gutierrez Teran, M. Anastassopoulos, A. Tzanakaki
Proc. IFIP International Conference on Artificial Intelligence Applications and Innovations (AIAI 2022), in: Artificial Intelligence Applications and Innovations. AIAI 2023 IFIP WG 12.5 International Workshops, Springer, IFIPAICT 677, 66 (2023)
DOI: 10.1007/978-3-031-34171-7_5, (5G-VICTORI)
(42) Development of AI-Hardware Related Curriculum for Universities in Brandenburg and Bavaria: Visions and Experiences from BB-KI Chips
Z. Xiong, M. Werner, O. Korup, M. Krstic
Proc. International Conference on Geomatics Education (ICGE 2023), abstr. 47 (2023)
(BB-KI-Chips)
(43) Integrating AI Hardware in Academic Teaching: Experiences and Scope from Brandenburg and Bavaria
Z. Xiong, D. Stober, M. Krstic, O. Korup, M.I. Arango,H. Li, M. Werner
ISPRS Annals of the Photogrammetry, Remote Sensing and Spatial Information Sciences X-5/W1-2023, 75 (2023)
DOI: 10.5194/isprs-annals-X-5-W1-2023-75-2023, (BB-KI-Chips)
The field of artificial intelligence (AI) has gained increasing importance in recent years due to its potential to sustain growth and prosperity in a disruptive way. However, the role of special hardware for AI is still underdeveloped, and dedicated AI-capable hardware is crucial for effective and efficient processing. Moreover, hardware aspects are often neglected in university teaching, which emphasizes theoretical foundations and algorithmic implementations. As a result, there is a need for courses that focus on AI hardware development and its diverse applications. In response to this need, the BB-KI Chips consortium aims to develop a series of hardware-oriented courses with real-world AI applications. This consortium includes the Technical University of Munich (TUM) and the University of Potsdam (UP), which both offer a wide range of courses that focus on AI basics, AI algorithmic development, general computer architectures, chip design, and as well applications of AI. In the BB-KI-CHIPS project, these different capacities are planned to be tightly integrated into a unified curriculum covering knowledge from chip design over AI algorithms and techniques to applications.
(44) Low Complexity Radar Gesture Recognition Using Synthetic Training Data
Y. Zhao, V. Sark, M. Krstic, E. Grass
Sensors (MDPI) 23(1), 308 (2023)
DOI: 10.3390/s23010308, (Open 6G Hub)
Developments in radio detection and ranging (radar) technology have made hand gesture recognition feasible. In heat map-based gesture recognition, feature images have a large size and require complex neural networks to extract information. Machine learning methods typically require large amounts of data and collecting hand gestures with radar is time- and energy-consuming. Therefore, a low computational complexity algorithm for hand gesture recognition based on a frequency-modulated continuous-wave (FMCW) radar and a synthetic hand gesture feature generator are proposed. In the low computational complexity algorithm, two-dimensional Fast Fourier Transform is implemented on the radar raw data to generate a range-Doppler matrix. After that, background modelling is applied to separate the dynamic object and the static background. Then a bin with the highest magnitude in the range-Doppler matrix is selected to locate the target and obtain its range and velocity. The bins at this location along the dimension of the antenna can be utilised to calculate the angle of the target using Fourier beam steering. In the synthetic generator, the Blender software is used to generate different hand gestures and trajectories and then the range, velocity and angle of targets are extracted directly from the trajectory. The experimental results demonstrate that the average recognition accuracy of the model on the test set can reach 89.13% when the synthetic data are used as the training set and the real data are used as the test set. This indicates that the generation of synthetic data can make a meaningful contribution in the pre-training phase
(45) Low Complexity Radar Gesture Recognition Using Synthetic Training Data
Y. Zhao, V. Sark, M. Krstic, E. Grass
Sensors (MDPI) 23(1), 308 (2023)
DOI: 10.3390/s23010308, (iCampus)
Developments in radio detection and ranging (radar) technology have made hand gesture recognition feasible. In heat map-based gesture recognition, feature images have a large size and require complex neural networks to extract information. Machine learning methods typically require large amounts of data and collecting hand gestures with radar is time- and energy-consuming. Therefore, a low computational complexity algorithm for hand gesture recognition based on a frequency-modulated continuous-wave (FMCW) radar and a synthetic hand gesture feature generator are proposed. In the low computational complexity algorithm, two-dimensional Fast Fourier Transform is implemented on the radar raw data to generate a range-Doppler matrix. After that, background modelling is applied to separate the dynamic object and the static background. Then a bin with the highest magnitude in the range-Doppler matrix is selected to locate the target and obtain its range and velocity. The bins at this location along the dimension of the antenna can be utilised to calculate the angle of the target using Fourier beam steering. In the synthetic generator, the Blender software is used to generate different hand gestures and trajectories and then the range, velocity and angle of targets are extracted directly from the trajectory. The experimental results demonstrate that the average recognition accuracy of the model on the test set can reach 89.13% when the synthetic data are used as the training set and the real data are used as the test set. This indicates that the generation of synthetic data can make a meaningful contribution in the pre-training phase
(46) Instantaneous 3D Velocity Estimation using Coordinated OFDM Radar Nodes
Y. Zhao, L.Wimmer, V. Sark, M. Krstic, E. Grass
Proc. 24th International Radar Symposium (IRS 2023), (2023)
DOI: 10.23919/IRS57608.2023.10172411, (Open 6G Hub)
(47) Instantaneous 3D Velocity Estimation using Coordinated OFDM Radar Nodes
Y. Zhao, L.Wimmer, V. Sark, M. Krstic, E. Grass
Proc. 24th International Radar Symposium (IRS 2023), (2023)
DOI: 10.23919/IRS57608.2023.10172411, (iCampus)
M. Aftowicz, I. Kabin, Z. Dyka, P. Langendörfer
Proc. 26th Euromicro Conference Series on Digital System Design (DSD 2023), (2023)
(Total Resilience)
(2) Characterization and Modeling of Single Event Transient Propagation through Standard Logic Cells
M. Andjelkovic, M. Krstic
Proc. 35. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 19 (2023)
(6G-TakeOff)
In this paper, the propagation of Single Event Transients (SETs) through standard combinational gates is inves-tigated with electrical simulations. It was shown that significant SET broadening may occur across short combinational paths. By fitting the simulation results, a predictive model for estimating the SET pulse broadening and shrinking caused by individual logic gates has been derived. The proposed model estimates the propagated SET pulse width in terms of gate’s driving strength, load capacitance, supply voltage and temperature. The model was verified on selected short combinational paths, and the rela-tive error with respect to simulations was less than 12%.
(3) Towards a Smart Multi-Sensor Ionizing Radiation Monitoring System
M. Andjelkovic, J.-C. Chen, R.T. Syed, F. Vargas, M. Ulbricht, M. Krstic, S. Ilic, M. Marjanovic, S. Veljkovic, N. Mitrovic, D. Dankovic, G. Ristic, R. Duane, N. Vasovic, A. Jaksic, A. Palma, A. Lallena, M. Carvajal
Proc. 26th Euromicro Conference on Digital System Design (DSD 2023), (2023)
(ELICSIR)
(4) Organic 6G Networks: Vision, Requirements, and Research Approaches
M.-I. Corici, F. Eichhorn, R. Bless, M. Gundall, D. Lindenschmitt, B. Bloessl, M. Petrova, L. Wimmer, R. Kreuch, T. Magedanz, H.D. Schotten
IEEE Access 11, 70698 (2023)
DOI: 10.1109/ACCESS.2023.3293055, (Open 6G Hub)
Building upon the significant number of already published 6G position papers, we are concentrating on the immediate next steps toward turning the research vision of software-centric networks into reality. This is accomplished, by summarizing and assessing the various requirements documents and providing a significant number of specific research directions and approaches in order to fulfill them. This article complements the existing body of work, by focusing on future core networks and their infrastructures, yet maintaining a system-level perspective and progressing in the direction of scoping key technology elements and providing high-potential research approaches for them. Additionally, we rigorously discuss the impact that different technological advancements have on the other parts of the system, to provide a coherent, end-to-end network understanding. This is in strong contrast to current approaches, where from the challenges, each research direction becomes independent and, thus, its advances are potentially cancelled out by the next technology in the chain. By maintaining this system perspective, the adoption of the different technologies becomes easier, as they are developed in unison. To address the requirements in a coherent, holistic, and unified way, we extend our high-level architecture concept named “Organic 6G Networks” towards a comprehensive end-to-end system. A holistic software-centric system, adapting the latest software development advancements from the IT industry. The Organic 6G network provides support for building a streamlined software network architecture and offers the next step on the path towards the development and specification of future mobile networks.
(5) SiGe BiCMOS Technology with Embedded Microchannels based on Cu Pillar PCB Integration Enabling Sub-THz Microfluidic Sensor Applications
E.C. Durmaz, C. Heine, Z. Cao, J. Lehmann, D. Kissinger, M. Wietstruck
Proc. IEEE International 3D System Integration Conference (3DIC 2023), (2023)
DOI: 10.1109/3DIC57175.2023.10155073, (DFG-THz LoC)
(6) The Scale4Edge RISC-V Ecosystem
W. Ecker, P. Adelt, W. Mueller, R. Heckmann, M. Krstic, N. Bruns, R. Drechsler, G. Angst, R. Wimmer, A. Mauderer, D. Mueller-Gritschneder, B. Becker, P. Scholl, E. Jentzsch, J. Schlamelcher, K. Grüttner, P. Palomero Bernardo, O. Bringmann, A. Koch, J. Bormann, J. Partzsch, C. Mayr, W. Kunz
Proc. RISC-V Summit Europe (RSIC-V 2023), (2023)
(Scale4Edge)
(7) Image-Rejection Up-/Down-Converter LO Distribution Chain for 5G mm-Wave Phased-Array Systems
A. Franzese, N. Maletic, R. Negra, A. Malignaggi
Proc. IEEE Radio & Wireless Symposium (RWS 2023), 14 (2023)
DOI: 10.1109/RWS55624.2023.10046204, (Taranto)
(8) Bits, Flips and RISCs
N. Gerlin, E. Kaja, M. Ulbricht, F. Vargas, L. Lu, A. Breitenreiter, J.-C. Chen, M. Gomez, A. Tahiraga, S. Prebeck, E. Jentzsch, M. Krstic, W. Ecker
Proc. 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2023), 140 (2023)
DOI: 10.1109/LMWT.2023.3265861, (Scale4Edge)
(9) Multiple Bit Upset-Tolerant EDAC Approach for Robust Embedded Memory Systems Design
R. Goerl, P. Villa, L. Poehls, F. Vargas
Proc. 35. ITG/GMM/GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 61 (2023)
(10) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(Open 6G Hub)
(11) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(AgileHyBeams (HU-B))
(12) Joint Communication and Sensing (JCAS) for 6G Wireless Systems
E. Grass, L. Wimmer, E. Sedunova, V. Sark, Y. Zhao, P. Geranmayeh
Proc. 27. ITG Fachtagung Mobilkommunikation, 30 (2023)
(IHP - Humboldt-Universität Joint-Lab)
(13) Fully Parallel Fully Unrolled BP Decoding of LDPC and Polar Codes
A. Hasani, L. Lopacinski, M. Krstic, E. Grass
Proc. 21st IEEE Wireless Communications and Networking Conference (WCNC 2023), (2023)
DOI: 10.1109/WCNC55385.2023.10118633, (PSSS-FEC)
(14) Randomized Addressing Countermeasures are Inefficient against Address-Bit SCA
I. Kabin, Z. Dyka, P. Langendörfer
Proc. IEEE International Conference on Cyber Security and Resilience (CSR 2023), 580 (2023)
DOI: 10.1109/CSR57506.2023.10224968, (Total Resilience)
(15) Ultra-High Data-Rate Wireless Access & Sensing Demonstrators in D-Band
K. Krishnegowda, M. Scheide, C. Herold, M. Appel, L. Lopacinski, A. Malignaggi, C. Carta, E. Grass
Proc. European Conference on Networks and Communications & 6G Summit (EUCNC 2023), (2023)
(6G-RIC)
(16) Amplitude- and Phase-Modulated PSSS for Wide Bandwidth Mixed Analog-Digital Baseband Processors in THz Communication
L. Lopacinski, N. Maletic, R. Kraemer, A. Hasani, J. Gutiérrez Teran, M. Krstic, E. Grass
Proc. 97th IEEE Vehicular Technology Conference (VTC 2023), (2023)
DOI: 10.1109/VTC2023-Spring57618.2023.10199923, (PSSS-FEC)
(17) Amplitude- and Phase-Modulated PSSS for Wide Bandwidth Mixed Analog-Digital Baseband Processors in THz Communication
L. Lopacinski, N. Maletic, R. Kraemer, A. Hasani, J. Gutiérrez Teran, M. Krstic, E. Grass
Proc. 97th IEEE Vehicular Technology Conference (VTC 2023), (2023)
DOI: 10.1109/VTC2023-Spring57618.2023.10199923, (6G-RIC)
(18) NLP Powered Intent Based Network Management for Private 5G Networks
J. Mcnamara, D. Camps-Mur, M. Goodarzi, H. Frank, L. Chinchilla-Romero, F. Canellas, A. Fernández-Fernández, S. Yan
IEEE Access 11, 36642 (2023)
DOI: 10.1109/ACCESS.2023.3265894
Intent driven networking holds the promise of simplifying network operations by allowing operators to use declarative, instead of imperative, interfaces. Adoption of this technology for 5G and beyond networks is however still in its infancy, where the required architectures, platforms, interfaces and algorithms are still being discussed. In this work, we present the design and implementation of a novel intent based platform for private 5G networks powered by a Natural Language Processing (NLP) interface. We demonstrate how our platform simplifies network operations in three relevant private network use cases, including: i) an intent based slice provisioning use case, ii) an intent based positioning use case, and iii) an intent based service deployment use case. Finally, all use cases are benchmarked in terms of intent provisioning time.
(19) Techno-Economic Analysis Highlighting Aspects of 5G Network Deployments at Railway Environments
I. Mesogiti, E. Theodoropoulou, F. Setaki, G. Lyberopoulos, K. Stamatis, P.K. Chartsias, N. Makris, P. Flegkas, J. Gutiérrez Teran, C. Politi, C. Tranoris, M. Anastasopoulos, A. Tzanakaki
Proc. International Conference on Artificial Intelligence Applications and Innovations (AIAI 2022), in: Artificial Intelligence Applications and Innovations. AIAI 2023 IFIP WG 12.5 International Workshops, Springer, IFIPAICT 677, 139 (2023)
DOI: 10.1007/978-3-031-34171-7_11, (5G-VICTORI)
(20) GPS-Spoofing Attack Detection Mechanism for UAV Swarms
P. Mykytyn, M. Brzozowski, Z. Dyka, P. Langendörfer
Proc. 11th International Conference on Cyber-Physical Systems and Internet-of-Things (CPS&IoT 2023), 18 (2023)
DOI: 10.1109/MECO58584.2023.10154998, (iCampus)
(21) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (KI-PRO)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(22) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (MIMEC)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(23) Optical Fault Injection Attacks against Different Logic and Memory Cells
D. Petryk, Z. Dyka
Proc. 11th Prague Embedded Systems Workshop (PESW 2023), 24 (2023)
(Total Resilience)
(24) SNR Maximization in Beyond Diagonal RIS-assisted Single and Multiple Antenna Links
I. Santamaria, M. Soleymani, E. Jorswieck, J. Gutierrez Teran
IEEE Signal Processing Letters 30, 923 (2023)
DOI: 10.1109/LSP.2023.3296902, (6G-RIC)
Reconfigurable intelligent surface (RIS) architectures not limited to diagonal phase shift matrices have recently been considered to increase their flexibility in shaping the wireless channel. One of these beyond-diagonal RIS or BD-RIS architectures leads to a unitary and symmetric RIS matrix. In this letter, we consider the problem of maximizing the signal-to-noise ratio (SNR) in single and multiple antenna links assisted by a BD-RIS. The Max-SNR problem admits a closed-form solution based on the Takagi factorization of a certain complex and symmetric matrix. This allows us to solve the max-SNR problem for SISO, SIMO, and MISO channels.
(25) Interference Leakage Minimization in RIS-Assisted MIMO Interference Channels
I. Santamaria, M. Soleymani, E. Jorswieck, J. Gutierrez Teran
Proc. International Conference on Acoustics, Speech, & Signal Processing (ICASSP 2023), (2023)
DOI: 10.1109/ICASSP49357.2023.10094656, (6G-RIC)
(26) Intelligence and Motion Models of Continuum Robots: an Overview
O. Shamilyan, I. Kabin, Z. Dyka, O. Sudakov, A. Cherninsky, M. Brzozowski, P. Langendörfer
IEEE Access 11, 60988 (2023)
DOI: 10.1109/ACCESS.2023.3286300, (Total Resilience)
Many technical solutions are bio-inspired. Octopus-inspired robotic arms belong to continuum robots which are used in minimally invasive surgery or for technical system restoration in areas difficult-to-access. Continuum robot missions are bounded with their motions, whereby the motion of the robots is controlled by humans via wireless communication. In case of a lost connection, robot autonomy is required. Distributed control and distributed decision-making mechanisms based on artificial intelligence approaches can be a promising solution to achieve autonomy of technical systems and to increase their resilience. However these methods are not well investigated yet. Octopuses are the living example of natural distributed intelligence but their learning and decision-making mechanisms are also not fully investigated and understood yet. Mechanisms of Distributed Artificial Intelligence can be investigated using a physical continuum robot prototype that is able to perform some basic movements and combine them into sequences of motions by itself. For the experimental investigations a suitable physical prototype has to be selected, its motion control has to be implemented and automated. In this paper, we give an overview combining different fields of research, such as Distributed Artificial Intelligence and continuum robots based on 97 publications. We provide a detailed description of the basic motion control models of continuum robots based on the literature reviewed, discuss different aspects of autonomy and give an overview of physical prototypes of continuum robots.
(27) Successful Simple Side Channel Analysis: Vulnerability of an Atomic Pattern kP Algorithm Implemented with a Constant Time Crypto Library to Simple Electromagnetic Analysis Attacks
A.A. Sigourou, I. Kabin, P. Langendörfer, N. Sklavos, Z. Dyka
Proc. 12th Mediterranean Conference on Embedded Computing (MECO 2023), 167 (2023)
DOI: 10.1109/MECO58584.2023.10154940, (Total Resilience)
(28) Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation
T. Song, Z. Huang, D. Wang, M. Krstic
Journal of Electronic Testing 39, 189 (2023)
DOI: 10.1007/s10836-023-06057-8
As the ICs become more complex, the duration of high-cost specification tests is increasingly important, especially given the total IC expenditure. In our current work, we propose an adaptive test strategy for reducing the duration of delay testing. This method employs pattern permutation with an ML algorithm to improve the test efficiency, followed by an examination of the effect of test performance, temperature, and voltage on the recognition of path delay defects. SPICE simulations under different voltage and temperature conditions with 65-nm CMOS technology were used to validate it. According to the experimental outcomes, when compared to the random ordering method, the proposed method successfully achieves a nearly 7-fold improvement in test quality at identical testing duration or a 25% reduction in the duration at identical test quality. In addition, the method provides the tester with a thorough understanding of the test efficiency contributions.
(29) High-Speed Optical Transceiver Integrated Chipset and Module for On-Board VCSEL-based Satellite Optical Interconnects
L. Sourikopoulos, G. Winzer, A. Peczek, M. Inac, P. Ostrovskyy, K. Tittelbach-Helmrich, G. Panic, G. Fischer, L. Zimmermann, Y. Franz, S. Jones, P. Kushner, U. Marvet, A. Lujambio, N. Garcia, D. Poudereux, M. Bodega, J. Barbero, L. Stampoulidis
Proc. 14th International Conference on Space Optics (ICSO 2022), 127774K (2023)
DOI: 10.1117/12.2690846, (SIPhoDiAS)
(30) Towards Reconfigurable CNN Accelerator for FPGA Implementation
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
IEEE Transactions on Circuits and Systems II 70(3), 12496 (2023)
DOI: 10.1109/TCSII.2023.3241154, (Open 6G Hub)
Convolutional Neural Networks (CNNs) have revolutionized many applications in recent years, especially in image classification, video processing, and pattern recognition. This success of CNNs has been a motivating factor for solving even more complex problems involving multiple data modalities. Traditionally, a single CNN accelerator has been optimized for just one task or has been used to perform correlated tasks. We leverage the CNNs capability to learn patterns and use one accelerator to perform multiple uncorrelated tasks from different modalities and achieve an average accuracy above 90%, which would otherwise require three accelerators. Two types of CNN architectures (i.e., fused and branched) are evaluated for three distinct tasks based on accuracy, quantization, pruning, hardware resource utilization, power, and latency. Capitalizing on this, we have further proposed a runtime reconfigurable CNN accelerator supporting fault-tolerant (FT), high-performance (HP), and de-stress (DS) modes.
(31) Towards Reconfigurable CNN Accelerator for FPGA Implementation
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
Proc. 14th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023), 206 (2023)
(Open 6G Hub)
(32) A Survey on Fault-Tolerant Methodologies for Deep Neural Networks
R.T. Syed, M. Ulbricht, K. Piotrowski, M. Krstic
Measurement Automation Robotics (Pomiary Automatyka Robotyka) 27(2), 89 (2023)
DOI: 10.14313/PAR_248/89, (Space Region)
A significant rise in Artificial Intelligence (AI) has impacted many applications around us, so much so that AI has now been increasingly used in safety-critical applications. AI at the edge is the reality, which means performing the data computation closer to the source of the data, as opposed to performing it on the cloud. Safety-critical applications have strict reliability requirements; therefore, it is essential that AI models running on the edge (i.e., hardware) must fulfill the required safety standards. In the vast field of AI, Deep Neural Networks (DNNs) are the focal point of this survey as it has continued to produce extraordinary outcomes in various applications .i.e medical, automotive, aerospace, defense, etc. Traditional reliability techniques for DNNs implementation are not always practical, as they fail to exploit the unique characteristics of the DNNs. Furthermore, it is also essential to understand the targeted edge hardware because the impact of the faults can be different in ASICs and FPGAs. Therefore, in this survey, first, we have examined the impact of the fault in ASICs and FPGAs, and then we seek to provide a glimpse of the recent progress made towards the fault-tolerant DNNs. We have discussed several factors that can impact the reliability of the DNNs. Further, we have extended this discussion to shed light on many state-of-the-art fault mitigation techniques for DNNs.
(33) An Approach for Runtime Reconfigurability in Application-Specific CNN Accelerators
R.T. Syed, M. Andjelkovic, M. Ulbricht, M. Krstic
Proc. 35. ITG/GMM /GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 43 (2023)
(Open 6G Hub)
(34) The TETRISC SoC - A Resilient Quad-Core System based on Pulpissimo
M. Ulbricht, L. Lu, J.-C. Chen, M. Krstic
Proc. RISC-V Summit Europe (2023), (2023)
(Scale4Edge)
(35) The TETRISC SoC - A Resilient Quad-Core System based on the ResiliCell Approach
M. Ulbricht, L. Lu, J.-C. Chen, M. Krstic
Microelectronics Reliability 148, 115173 (2023)
DOI: 10.1016/j.microrel.2023.115173, (Scale4Edge)
Resilient systems require monitoring and prediction of environmental and intrinsic conditions and the ability to adapt to changing circumstances to optimize the trade-off between performance, power consumption, and fault tolerance. This paper presents an approach for enabling a design to achieve resilience. By using a range of reliability sensors and the novel ResiliCells, we have developed the TETRISC System-on-Chip (SoC), which is a multiprocessor system based on the PULPissimo platform. The TETRISC SoC can operate its four cores in different performance and fault tolerance modes based on real-time data, making it ideal for use cases with dynamically changing and reliability critical requirements, such as avionics or aerospace. Additional in-depth studies on possible optimizations demonstrate the flexibility of the ResiliCell approach.
(36) PULP Fiction No More - Dependable PULP Systems for Space
M. Ulbricht, Y. Tortorella, M. Rogenmoser, L. Lu, J.-C. Chen, F. Conti, M. Krstic, L. Benini
Proc. 28th IEEE European Test Symposium (ETS 2023), (2023)
DOI: 10.1109/ETS56758.2023.10174164, (Scale4Edge)
(37) Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis
M. Ulbricht, J.-C. Chen, L. Lu, M. Krstic, W. Müller
Proc. 35. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2023), 9 (2023)
(Scale4Edge)
(38) Artificial Neural Network Accelerator for Classification of In-Field Conducted Noise in Integrated Circuits' DC Power Lines
F. Vargas, D. Borba, J.D. Benfica, R.T. Syed
Proc. 29th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2023), 212 (2023)
DOI: 10.1109/IOLTS59296.2023.10224874
(39) COCHISA Approach: European Core-Chip for Space Applications
F. Vargas, C. Corrado, A. Malignaggi, M. Krstic, D. Verploegen, G. Mannocchi, M. Petri, P. Fontana, U. Lewark, R. Follmann, S. Rochette
Proc. 1st ESA/ESTEC Space Microwave Week (2023), (2023)
(COCHISA)
(40) Localization System Architecture for Enhanced Positioning in Industry 4.0 Applications
R. Vasist, V. Sark, M. Goodarzi, J. Gutierrez Teran, E. Grass
Proc. International Conference on Computing, Networking and Communications (ICNC 2023), 683 (2023)
DOI: 10.1109/ICNC57223.2023.10074001, (5G-CLARITY)
(41) Media Services in Dense, Static and Mobile Environments Leveraging Edge Deployments
M.-E. Xezonaki, N. Psaromanolakis, P. K. Chartsias, K. Stamatis, D. Kritharidis, V. Theodorou, C. Politi, P. Papaioannou, C. Tranoris, S. Denazis, I. Mesogiti, E. Theodoropoulou, F. Setaki, G. Lyberopoulos, N. Makris, P. Flegkas, J. Gutierrez Teran, M. Anastassopoulos, A. Tzanakaki
Proc. IFIP International Conference on Artificial Intelligence Applications and Innovations (AIAI 2022), in: Artificial Intelligence Applications and Innovations. AIAI 2023 IFIP WG 12.5 International Workshops, Springer, IFIPAICT 677, 66 (2023)
DOI: 10.1007/978-3-031-34171-7_5, (5G-VICTORI)
(42) Development of AI-Hardware Related Curriculum for Universities in Brandenburg and Bavaria: Visions and Experiences from BB-KI Chips
Z. Xiong, M. Werner, O. Korup, M. Krstic
Proc. International Conference on Geomatics Education (ICGE 2023), abstr. 47 (2023)
(BB-KI-Chips)
(43) Integrating AI Hardware in Academic Teaching: Experiences and Scope from Brandenburg and Bavaria
Z. Xiong, D. Stober, M. Krstic, O. Korup, M.I. Arango,H. Li, M. Werner
ISPRS Annals of the Photogrammetry, Remote Sensing and Spatial Information Sciences X-5/W1-2023, 75 (2023)
DOI: 10.5194/isprs-annals-X-5-W1-2023-75-2023, (BB-KI-Chips)
The field of artificial intelligence (AI) has gained increasing importance in recent years due to its potential to sustain growth and prosperity in a disruptive way. However, the role of special hardware for AI is still underdeveloped, and dedicated AI-capable hardware is crucial for effective and efficient processing. Moreover, hardware aspects are often neglected in university teaching, which emphasizes theoretical foundations and algorithmic implementations. As a result, there is a need for courses that focus on AI hardware development and its diverse applications. In response to this need, the BB-KI Chips consortium aims to develop a series of hardware-oriented courses with real-world AI applications. This consortium includes the Technical University of Munich (TUM) and the University of Potsdam (UP), which both offer a wide range of courses that focus on AI basics, AI algorithmic development, general computer architectures, chip design, and as well applications of AI. In the BB-KI-CHIPS project, these different capacities are planned to be tightly integrated into a unified curriculum covering knowledge from chip design over AI algorithms and techniques to applications.
(44) Low Complexity Radar Gesture Recognition Using Synthetic Training Data
Y. Zhao, V. Sark, M. Krstic, E. Grass
Sensors (MDPI) 23(1), 308 (2023)
DOI: 10.3390/s23010308, (Open 6G Hub)
Developments in radio detection and ranging (radar) technology have made hand gesture recognition feasible. In heat map-based gesture recognition, feature images have a large size and require complex neural networks to extract information. Machine learning methods typically require large amounts of data and collecting hand gestures with radar is time- and energy-consuming. Therefore, a low computational complexity algorithm for hand gesture recognition based on a frequency-modulated continuous-wave (FMCW) radar and a synthetic hand gesture feature generator are proposed. In the low computational complexity algorithm, two-dimensional Fast Fourier Transform is implemented on the radar raw data to generate a range-Doppler matrix. After that, background modelling is applied to separate the dynamic object and the static background. Then a bin with the highest magnitude in the range-Doppler matrix is selected to locate the target and obtain its range and velocity. The bins at this location along the dimension of the antenna can be utilised to calculate the angle of the target using Fourier beam steering. In the synthetic generator, the Blender software is used to generate different hand gestures and trajectories and then the range, velocity and angle of targets are extracted directly from the trajectory. The experimental results demonstrate that the average recognition accuracy of the model on the test set can reach 89.13% when the synthetic data are used as the training set and the real data are used as the test set. This indicates that the generation of synthetic data can make a meaningful contribution in the pre-training phase
(45) Low Complexity Radar Gesture Recognition Using Synthetic Training Data
Y. Zhao, V. Sark, M. Krstic, E. Grass
Sensors (MDPI) 23(1), 308 (2023)
DOI: 10.3390/s23010308, (iCampus)
Developments in radio detection and ranging (radar) technology have made hand gesture recognition feasible. In heat map-based gesture recognition, feature images have a large size and require complex neural networks to extract information. Machine learning methods typically require large amounts of data and collecting hand gestures with radar is time- and energy-consuming. Therefore, a low computational complexity algorithm for hand gesture recognition based on a frequency-modulated continuous-wave (FMCW) radar and a synthetic hand gesture feature generator are proposed. In the low computational complexity algorithm, two-dimensional Fast Fourier Transform is implemented on the radar raw data to generate a range-Doppler matrix. After that, background modelling is applied to separate the dynamic object and the static background. Then a bin with the highest magnitude in the range-Doppler matrix is selected to locate the target and obtain its range and velocity. The bins at this location along the dimension of the antenna can be utilised to calculate the angle of the target using Fourier beam steering. In the synthetic generator, the Blender software is used to generate different hand gestures and trajectories and then the range, velocity and angle of targets are extracted directly from the trajectory. The experimental results demonstrate that the average recognition accuracy of the model on the test set can reach 89.13% when the synthetic data are used as the training set and the real data are used as the test set. This indicates that the generation of synthetic data can make a meaningful contribution in the pre-training phase
(46) Instantaneous 3D Velocity Estimation using Coordinated OFDM Radar Nodes
Y. Zhao, L.Wimmer, V. Sark, M. Krstic, E. Grass
Proc. 24th International Radar Symposium (IRS 2023), (2023)
DOI: 10.23919/IRS57608.2023.10172411, (Open 6G Hub)
(47) Instantaneous 3D Velocity Estimation using Coordinated OFDM Radar Nodes
Y. Zhao, L.Wimmer, V. Sark, M. Krstic, E. Grass
Proc. 24th International Radar Symposium (IRS 2023), (2023)
DOI: 10.23919/IRS57608.2023.10172411, (iCampus)
