Publications 2026
Script list Publications
(1) Reliability Assessment of Deep Neural Networks and Accelerators Across Design Stages
M.H. Ahmadilivani, N. Cherezova, M. Glaß, J.D. Guerrero Balaguera, M. Jenihhin, A. Kritikakou, R. Limas Sierra, L.M. Bolzani Poehls, J. Raik, L. Roquet, F. Fernandes dos Santos, F. Augusto, M. Sonza Reorda, A. Veronesi, E.C. Villegas Castillo, J.E. Rodriguez Condia
Proc. 27th IEEE Latin-American Test Symposium (LATS 2026), (2026)
DOI: 10.1109/LATS70329.2026.11480274, (TAICHIP)
(2) An Overview of On-Chip Sensing and Analytics for Resilient Integrated Circuits
M. Andjelkovic, R.T. Syed, M. Ulbricht, F. Vargas, Z. Peric, M. Dincic, J. Nikolic, A. Jovanovic, D. Ciric, T. Nikolic, G. Nikolic, J. Nedeljkovic, S. Peric, N. Vucic, M. Krstić
Proc. 10th Small Systems Simulation Symposium (SSSS 2025), (2026)
(AIDA4Edge)
(3) Advanced Machine Learning-Based Eco-Integrated Model for Predicting Potato Late Blight in Multiple Cultivation Systems
P. Bagchi, B. Sawicka, Z. Stamenkovic, P. Barbas, P. Pszczolkowski, D. Markovic, D. Bhattacharjee
Facta Universitatis, Series: Electronics and Energetics 39(1), 219 (2026)
DOI: 10.2298/FUEE2601219B, (BB-KI-Chips)
This paper presents a machine learning–driven framework for analyzing and predicting potato late blight (caused by Phytophthora infestans) across two distinct cultivation systems—ecological and integrated—using six potato varieties. Traditional statistical methods, including a two-factor Analysis of Variance (ANOVA) and Tukey’s Honest Significant Difference (HSD) test, were applied to assess the effects of cultivation systems, potato varieties, and year. To enhance predictive accuracy and model interpretability, an advanced machine learning pipeline, termed the Eco-Integrated Model, was developed. This model integrates SMOTE (Synthetic Minority Oversampling Technique) for handling class imbalance, SHAP (SHapley Additive xPlanations) for interpretability and feature importance analysis, and the CatBoost classifier for robust, high-performance prediction. The dataset, collected over three years (2018–2020), includes multi-varietal and system-specific records of late blight incidence for both ecological integrated-based data, serving as input for model training and evaluation. The proposed Eco-Integrated Model demonstrated high predictive capability, revealing that integrated cultivation systems are generally more effective at suppressing disease progression. Moreover, substantial varietal differences were identified in late blight susceptibility, as highlighted by both statistical and machine learning analyses. These findings underline the value of incorporating explainable, data-driven approaches into plant disease forecasting. The Eco-Integrated Model offers a scalable, interpretable, and accurate predictive solution, contributing to precision agriculture practices and supporting evidence-based decision-making for sustainable potato production and disease management strategies.
(4) Modeling Endurance Degradation of VCM-based 1T1R ReRAM Cell for Circuit Simulations
S. Chakraborty, S.H. Hashemi Shadmehri, T.S. Copetti, T. Gemmeke, L.M. Bolzani Poehls
Proc. 27th International Symposium on Quality Electronic Design (ISQED 2026), (2026)
DOI: 10.1109/ISQED69900.2026.11534679
(5) Agile Methodologies for the Development of Radiation-Hardened Integrated Circuits
J.-C. Chen, L. Lu, A. Veronsi, M. Andjelkovic, M. Krstic
The European Physical Journal Special Topics 235, 1165 (2026)
DOI: 10.1140/epjs/s11734-025-01754-1, (Scale4Edge)
Radiation effects in integrated circuits (ICs) pose significant challenges for reliability-critical applications such as aviation, space exploration, and automotive systems. Traditional radiation hardening methods, while effective, are often resource-intensive and time consuming. Agile hardware development, as a new hardware design method, provides an efficient approach for ICs design. This paper explores the application of agile methodologies to enhance the design and evaluation of radiation-hardened systems. We first review existing agile hardware development methods and achievements in high-reliability hardware development. To address the time-consuming feature of reliability evaluation and the difficulty of selective hardening in high-reliability chip design, we propose fault injection and reliability analysis methods based on graph neural networks (GNNs), as well as fast cross-layer system reliability analysis techniques. These methods can quickly evaluate design reliability at the abstract or netlist levels, and predict simulation-based fault injection results. These methods accelerate fault detection and reliability evaluation, enabling faster iterations and more responsive design adjustments. By integrating these agile methods into the traditional high-reliability chip design process, we achieve improvements in both efficiency and reliability assessment of high-reliability IC design.
(6) Agile Methodologies for the Development of Radiation-Hardened Integrated Circuits
J.-C. Chen, L. Lu, A. Veronsi, M. Andjelkovic, M. Krstic
The European Physical Journal Special Topics 235, 1165 (2026)
DOI: 10.1140/epjs/s11734-025-01754-1, (Open 6G Hub)
Radiation effects in integrated circuits (ICs) pose significant challenges for reliability-critical applications such as aviation, space exploration, and automotive systems. Traditional radiation hardening methods, while effective, are often resource-intensive and time consuming. Agile hardware development, as a new hardware design method, provides an efficient approach for ICs design. This paper explores the application of agile methodologies to enhance the design and evaluation of radiation-hardened systems. We first review existing agile hardware development methods and achievements in high-reliability hardware development. To address the time-consuming feature of reliability evaluation and the difficulty of selective hardening in high-reliability chip design, we propose fault injection and reliability analysis methods based on graph neural networks (GNNs), as well as fast cross-layer system reliability analysis techniques. These methods can quickly evaluate design reliability at the abstract or netlist levels, and predict simulation-based fault injection results. These methods accelerate fault detection and reliability evaluation, enabling faster iterations and more responsive design adjustments. By integrating these agile methods into the traditional high-reliability chip design process, we achieve improvements in both efficiency and reliability assessment of high-reliability IC design.
(7) Optimizing Edge AI: Current Challenges and the Neuromorphic Outlook
M. Dincic, A. Bizzarri, D. Bertozzi, R.T. Syed, E. Jones
Proc. 29th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2026), (2026)
DOI: 10.1109/DDECS69233.2026.11521015, (AIDA4Edge)
(8) Towards Programmable Infrastructure for Organic and Flexible 6G Networks
F. Eichhorn, R. Bless, P. Seehofer, M. Gundall, D. Lindenschmitt, B. Bloessl, D. Volz, N. Keshtiarast, H. Borchert, M. Petri, E.-R. Modroiu, J. John, H. Mohammadalizadeh, T. Radig, L. Paeleke, H. Ackermann, D. Hauer, M.-I. Corici, M. Petrova, T. Magedanz, H.D. Schotten
IEEE Access 14, 1 (2026)
DOI: 10.1109/ACCESS.2026.3675437, (Open 6G Hub)
The next generation of wireless mobile networks will be driven by software and infrastructure virtualization. At the same time, the underlying hardware will become more diverse. Edge, intermediate and central network nodes will allow distributed deployments of never seen before scale. Non-terrestrial networks, nomadic networks and networks in networks promise more dynamicity, changing their topologies over time in predictable and unpredictable ways. To handle the complexity and dynamicity, a highly flexible and adaptable network is required. The key enablers of this complex digital communication system will be programmable infrastructures. From programmable access and flexible backhauls to zero-touch, adaptable and resilient control planes, we conducted research into advanced programmability at different layers of the network, within the Open6GHub project. In this article, we present innovative solutions for advanced programmable network infrastructure and show why they are essential for our vision of the programmable infrastructure of future wireless mobile networks.
(9) Sideband/Image-Rejection Up-/Down-Converter Transceiver RFIC for Scalable 5G mm-Wave Phased-Array Antenna Systems
A. Franzese, B. Sütbas, N. Maletic, A. Malignaggi, R. Negra, C. Carta
Proc. 37th Asia-Pacific Microwave Conference (APMC 2025), (2026)
DOI: 10.1109/APMC65046.2025.11379226
(10) UPSET: A Comprehensive Probabilistic Single Event Transient Analysis Flow for VLSI Circuits using Static Timing Analysis
C. Georgakidis, D. Valiantzas, N. Chatzivangelis, M. Andjelkovic, C. Sotiriou, M. Krstic
Electronics (MDPI) 15(4), 818 (2026)
DOI: 10.3390/electronics15040818, (TWIN-RELECT)
The downscaling of VLSI technologies has exacerbated the susceptibility of integrated circuits (ICs) to radiation-induced Single Event Transients (SETs). This work presents UPSET, a comprehensive and technology-independent EDA framework for probabilistic SET analysis using Static Timing Analysis (STA). Unlike traditional simulation-based methods that suffer from prohibitive runtimes, UPSET leverages graph-based propagation with advanced logical, electrical, and timing-window masking models to evaluate circuit sensitivity efficiently. Key contributions include a novel "Electrical Masking Window" (EMW) criterion that effectively filters non-full-rail pulses early in reconvergent logic, and a TimeStamp-based propagation mode that accurately handles complex signal reconvergence with Boolean evaluation. Experimental results over some featuring benchmarks demonstrate over 25,000× speedup compared to SPICE, while maintaining a tight 4.56% error bound in pulse width estimation. Moreover, experimental validation on 50 benchmarks across varying complexities showcases that EMW enhancement reduces the pessimism to circuit sensitivity by up to 25% on average, providing tighter upper bounds while maintaiing scalability to million-gate designs. By integrating seamlessly with standard industrial formats (LEF/DEF/LIB/SPEF), UPSET enables scalable, accurate soft SET sensitivity assessment for modern digital designs, establishing a robust foundation for automated radiation hardening flows.
(11) Optimizing Beamforming and Transmit Power for Improving mmWave Wireless Network Performance
P. Geranmayeh, E. Grass
Proc. IEEE International Conference on AI for Sustainable Innovation (AI-SI 2025), (2026)
DOI: 10.1109/AI-SI66213.2025.11340944, (IHP - Humboldt-Universität Joint-Lab)
(12) Optimizing Beamforming and Transmit Power for Improving mmWave Wireless Network Performance
P. Geranmayeh, E. Grass
Proc. IEEE International Conference on AI for Sustainable Innovation (AI-SI 2025), (2026)
DOI: 10.1109/AI-SI66213.2025.11340944, (5G-REMOTE)
(13) Energy-Efficient and Intelligent RAN Evolution for B5G and 6G
J. Gutiérrez Teran, M. Ghoraishi, M. Catalán-Cid, S. Pryor
BeGREEN Project Final White Paper (March 2026)
DOI: 10.5281/zenodo.19484593, (BeGREEN)
(14) On-Chip Slotted Patch Antenna at 226-244 GHz in SiGe Cu-Backend Technology
R. Hasan, D. Cvetkovski, F.A. Dürrwald, S. Dilek, U. Maß, A. Bhutani, M.H. Eissa, B. Sütbas, D. Kissinger, C. Carta
Proc. 37th Asia-Pacific Microwave Conference (APMC 2025), (2026)
DOI: 10.1109/APMC65046.2025.11378886, (iCampus II)
(15) Mobility-Induced Sensitivity of UAV-based Nodes to Jamming in Private 5G Airfield Networks - An Experimental Study
P. Mykytyn, R. Chitauro, O. Yener, P. Langendörfer
Proc. iCampus Cottbus Conference (iCCC 2026), 268 (2026)
DOI: 10.5162/iCCC2026/P37
(16) Unsourced Random Access: A Comprehensive Survey
M. Özates, M.J. Ahmadi, M. Kazemi, D. Gündüz, T.M. Duman
IEEE Communications Surveys & Tutorials 28, 955 (2026)
DOI: 10.1109/COMST.2025.3637685, (6G-RIC)
The sixth generation and beyond communication systems are expected to enable communications of a massive number of machine-type devices. The traffic generated by some of these devices will significantly deviate from those in conventional communication scenarios. For instance, for applications where a massive number of cheap sensors communicate with a base station (BS), the devices will only be sporadically active and there will be no coordination among them or with the BS. For such systems requiring massive random access solutions, a new paradigm called unsourced random access (URA) has been proposed. In URA, all the users employ the same codebook and there is no user identity during the data transmission phase. The destination is only interested in the list of messages being sent from the set of active users.
In this survey, we provide a comprehensive overview of existing URA solutions with an emphasis on the state-of-the-art, covering both algorithmic and information-theoretic aspects. Moreover, we provide future research directions and challenges, and describe some potential methods of addressing them.
(17) ICAS-Enabled Predictive Beam-Steering for Link Blockage Mitigation in Millimeter-Wave Systems
M. Petri, N. Maletic
Proc. 6th IEEE International Symposium on Joint Communications & Sensing (JC&S 2026), (2026)
DOI: 10.1109/JCS69321.2026.11366018, (Open 6G Hub)
(18) Demonstration of ICAS-enabled Environment Perception and Beam Adaptation for mmWave Link Blockage Mitigation
M. Petri, N. Maletic
Proc. 17th German Microwave Conference (GeMiC 2026), (2026)
DOI: 10.1109/GeMiC71240.2026.11516402, (Open 6G Hub)
(19) Riemannian Optimization on the Manifold of Unitary and Symmetric Matrices with Application to BD-RIS-Assisted Systems
I. Santamaria, M. Soleymani, E. Jorswieck, J. Gutierrez Teran, C. Beltran
Proc. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2026), 531 (2026)
DOI: 10.1109/ICASSP55912.2026.11460513
(20) Latch Based Design for Fast Voltage Droop Response
S. Srinivas, I.W. Jones, G. Panic, C. Lenzen
zu finden unter: https://arxiv.org/abs/2501.18843
(21) Efficient Reliability-Aware Hardware Trojan Design and Insertion for SET-Induced Soft Error Attacks
A. Takou, G. Paliaroutis, P. Tsoumanis, M. Andjelkovic, F. Vargas, N. Evmorfopoulos, G. Stamoulis
Electronics (MDPI) 15(2), 425 (2026)
DOI: 10.3390/electronics15020425, (TWIN-RELECT)
Soft errors and Hardware Trojans (HTs) constitute major reliability concerns, and in combination they can pose an even greater threat to circuit security. The main aim of this research is to develop and implement a reliability-based HT and to identify the optimal regions for its injection, enabling the creation of challenging benchmarks for evaluating detection techniques. In this context, a reliability-based HT is designed and evaluated using different components to achieve the required time overhead. Next, a method that combines the generation and propagation of Single-Event Transients (SETs), while accounting for both masking effects and the design’s timing constraints, is employed to efficiently identify the most vulnerable and critical gates. The sensitive gates selected for HT insertion exhibit 50–70% vulnerability to soft errors. At the same time, their insertion and the resulting path delay overhead must not violate the design’s timing constraints, and the additional area must remain below 10% of the total area. These three conditions ensure that the inserted HTs remain stealthy and, therefore, challenging to detect. The experimental results demonstrate that selecting this category of gates is highly effective, as it leads to a significant increase in the number of soft errors and, consequently, aggravates circuit vulnerability with minimal impact on the design. On average, the targeted gates exhibit a 130% increase in sensitivity, and the overall Soft Error Rate (SER) increases by 78%, confirming the importance of providing robust benchmarks to combat potential attacks of this kind.
(22) Auf dem Weg zur radarbasierten Rinderüberwachung: Erste Überlegungen, Aufbauten und Ergebnisse
M. Ulbricht, V. Sark, R.T. Syed, J. Gose, G. Hoffmann
Proc. iCampµs Cottbus Conference (iCCC 2026), 90 (2026)
DOI: 10.5162/iCCC2026/5.4, (iCampus II)
(23) On-Chip Sensor with Programmable Delay Logic to Monitor Memory Aging Evolution
F. Vargas, V. Galstyan, G. Harutyunyan, Y. Zorian
Proc. 29th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2026), (2026)
DOI: 10.1109/DDECS69233.2026.11520974
(24) Embedded Tutorial: Considerations on the Design of Resilient 2.5/3D Heterogeneous Integration, Multilayer Interposer Systems for Chip Lifecycle Management
F. Vargas, M. Andjelkovic, C. Sotirio
Proc. 29th IEEE International Symposium on Design and Diagnostics of Electronic Circuit and Systems (DDECS 2026), (2026)
DOI: 10.1109/DDECS69233.2026.11521006, (TWIN-RELECT)
(25) ReFFT: An Energy-Efficient RRAM-Based FFT Accelerator
J. Wen, A. Baroni, M. Uhlmann, E. Perez, Ch. Wenger, M. Krstic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 45(6), 2620 (2026)
DOI: 10.1109/TCAD.2025.3627146, (INSEKT)
The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector–matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.
(26) RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference
J. Wen, A. Baroni, Ch. Wenger, M. Krstic, L.M. Bolzani Poehls
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 34(3), 809 (2026)
DOI: 10.1109/TVLSI.2025.3644141, (6G-RIC)
The growing computational demands of convolutional neural networks (CNNs) have motivated the use of spectral-domain inference as an alternative to costly spatial-domain convolutions. In this work, we propose an resistive RAM (RRAM)-based spectral-domain convolutional layer that exploits in-memory computing (IMC) for low energy consumption and high parallelism. Both the two-dimensional Fourier transform and the pointwise multiplications are directly implemented on RRAM crossbar arrays, while Hermitian symmetry is leveraged to further enhance the energy efficiency of the transform and subsequent spectral processing. To ensure robustness, measured RRAM device data are incorporated into system-level simulations to evaluate the impact of device variability on inference accuracy. Furthermore, we introduce a layer-wise mapping framework that adaptively selects between spatial- and spectral-domain execution based on the trade-off between energy efficiency and accuracy. Simulation results show that the proposed design achieves up to a 2.18× improvement in energy efficiency across convolutional layer configurations. For VGG-8 on CIFAR-100, the proposed architecture with the layer-wise mapping scheme reduces the energy–delay product (EDP) by 45% while incurring negligible accuracy loss. This work presents the first complete RRAM-based spectral-domain convolutional layer that accounts for device variability, providing a promising solution for edge CNN inference.
(27) ReFFT: An Energy-Efficient RRAM-Based FFT Accelerator
J. Wen, A. Baroni, M. Uhlmann, E. Perez, Ch. Wenger, M. Krstic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 45(6), 2620 (2026)
DOI: 10.1109/TCAD.2025.3627146, (6G-RIC)
The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector–matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.
(28) RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference
J. Wen, A. Baroni, Ch. Wenger, M. Krstic, L.M. Bolzani Poehls
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 34(3), 809 (2026)
DOI: 10.1109/TVLSI.2025.3644141, (INSEKT)
The growing computational demands of convolutional neural networks (CNNs) have motivated the use of spectral-domain inference as an alternative to costly spatial-domain convolutions. In this work, we propose an resistive RAM (RRAM)-based spectral-domain convolutional layer that exploits in-memory computing (IMC) for low energy consumption and high parallelism. Both the two-dimensional Fourier transform and the pointwise multiplications are directly implemented on RRAM crossbar arrays, while Hermitian symmetry is leveraged to further enhance the energy efficiency of the transform and subsequent spectral processing. To ensure robustness, measured RRAM device data are incorporated into system-level simulations to evaluate the impact of device variability on inference accuracy. Furthermore, we introduce a layer-wise mapping framework that adaptively selects between spatial- and spectral-domain execution based on the trade-off between energy efficiency and accuracy. Simulation results show that the proposed design achieves up to a 2.18× improvement in energy efficiency across convolutional layer configurations. For VGG-8 on CIFAR-100, the proposed architecture with the layer-wise mapping scheme reduces the energy–delay product (EDP) by 45% while incurring negligible accuracy loss. This work presents the first complete RRAM-based spectral-domain convolutional layer that accounts for device variability, providing a promising solution for edge CNN inference.
M.H. Ahmadilivani, N. Cherezova, M. Glaß, J.D. Guerrero Balaguera, M. Jenihhin, A. Kritikakou, R. Limas Sierra, L.M. Bolzani Poehls, J. Raik, L. Roquet, F. Fernandes dos Santos, F. Augusto, M. Sonza Reorda, A. Veronesi, E.C. Villegas Castillo, J.E. Rodriguez Condia
Proc. 27th IEEE Latin-American Test Symposium (LATS 2026), (2026)
DOI: 10.1109/LATS70329.2026.11480274, (TAICHIP)
(2) An Overview of On-Chip Sensing and Analytics for Resilient Integrated Circuits
M. Andjelkovic, R.T. Syed, M. Ulbricht, F. Vargas, Z. Peric, M. Dincic, J. Nikolic, A. Jovanovic, D. Ciric, T. Nikolic, G. Nikolic, J. Nedeljkovic, S. Peric, N. Vucic, M. Krstić
Proc. 10th Small Systems Simulation Symposium (SSSS 2025), (2026)
(AIDA4Edge)
(3) Advanced Machine Learning-Based Eco-Integrated Model for Predicting Potato Late Blight in Multiple Cultivation Systems
P. Bagchi, B. Sawicka, Z. Stamenkovic, P. Barbas, P. Pszczolkowski, D. Markovic, D. Bhattacharjee
Facta Universitatis, Series: Electronics and Energetics 39(1), 219 (2026)
DOI: 10.2298/FUEE2601219B, (BB-KI-Chips)
This paper presents a machine learning–driven framework for analyzing and predicting potato late blight (caused by Phytophthora infestans) across two distinct cultivation systems—ecological and integrated—using six potato varieties. Traditional statistical methods, including a two-factor Analysis of Variance (ANOVA) and Tukey’s Honest Significant Difference (HSD) test, were applied to assess the effects of cultivation systems, potato varieties, and year. To enhance predictive accuracy and model interpretability, an advanced machine learning pipeline, termed the Eco-Integrated Model, was developed. This model integrates SMOTE (Synthetic Minority Oversampling Technique) for handling class imbalance, SHAP (SHapley Additive xPlanations) for interpretability and feature importance analysis, and the CatBoost classifier for robust, high-performance prediction. The dataset, collected over three years (2018–2020), includes multi-varietal and system-specific records of late blight incidence for both ecological integrated-based data, serving as input for model training and evaluation. The proposed Eco-Integrated Model demonstrated high predictive capability, revealing that integrated cultivation systems are generally more effective at suppressing disease progression. Moreover, substantial varietal differences were identified in late blight susceptibility, as highlighted by both statistical and machine learning analyses. These findings underline the value of incorporating explainable, data-driven approaches into plant disease forecasting. The Eco-Integrated Model offers a scalable, interpretable, and accurate predictive solution, contributing to precision agriculture practices and supporting evidence-based decision-making for sustainable potato production and disease management strategies.
(4) Modeling Endurance Degradation of VCM-based 1T1R ReRAM Cell for Circuit Simulations
S. Chakraborty, S.H. Hashemi Shadmehri, T.S. Copetti, T. Gemmeke, L.M. Bolzani Poehls
Proc. 27th International Symposium on Quality Electronic Design (ISQED 2026), (2026)
DOI: 10.1109/ISQED69900.2026.11534679
(5) Agile Methodologies for the Development of Radiation-Hardened Integrated Circuits
J.-C. Chen, L. Lu, A. Veronsi, M. Andjelkovic, M. Krstic
The European Physical Journal Special Topics 235, 1165 (2026)
DOI: 10.1140/epjs/s11734-025-01754-1, (Scale4Edge)
Radiation effects in integrated circuits (ICs) pose significant challenges for reliability-critical applications such as aviation, space exploration, and automotive systems. Traditional radiation hardening methods, while effective, are often resource-intensive and time consuming. Agile hardware development, as a new hardware design method, provides an efficient approach for ICs design. This paper explores the application of agile methodologies to enhance the design and evaluation of radiation-hardened systems. We first review existing agile hardware development methods and achievements in high-reliability hardware development. To address the time-consuming feature of reliability evaluation and the difficulty of selective hardening in high-reliability chip design, we propose fault injection and reliability analysis methods based on graph neural networks (GNNs), as well as fast cross-layer system reliability analysis techniques. These methods can quickly evaluate design reliability at the abstract or netlist levels, and predict simulation-based fault injection results. These methods accelerate fault detection and reliability evaluation, enabling faster iterations and more responsive design adjustments. By integrating these agile methods into the traditional high-reliability chip design process, we achieve improvements in both efficiency and reliability assessment of high-reliability IC design.
(6) Agile Methodologies for the Development of Radiation-Hardened Integrated Circuits
J.-C. Chen, L. Lu, A. Veronsi, M. Andjelkovic, M. Krstic
The European Physical Journal Special Topics 235, 1165 (2026)
DOI: 10.1140/epjs/s11734-025-01754-1, (Open 6G Hub)
Radiation effects in integrated circuits (ICs) pose significant challenges for reliability-critical applications such as aviation, space exploration, and automotive systems. Traditional radiation hardening methods, while effective, are often resource-intensive and time consuming. Agile hardware development, as a new hardware design method, provides an efficient approach for ICs design. This paper explores the application of agile methodologies to enhance the design and evaluation of radiation-hardened systems. We first review existing agile hardware development methods and achievements in high-reliability hardware development. To address the time-consuming feature of reliability evaluation and the difficulty of selective hardening in high-reliability chip design, we propose fault injection and reliability analysis methods based on graph neural networks (GNNs), as well as fast cross-layer system reliability analysis techniques. These methods can quickly evaluate design reliability at the abstract or netlist levels, and predict simulation-based fault injection results. These methods accelerate fault detection and reliability evaluation, enabling faster iterations and more responsive design adjustments. By integrating these agile methods into the traditional high-reliability chip design process, we achieve improvements in both efficiency and reliability assessment of high-reliability IC design.
(7) Optimizing Edge AI: Current Challenges and the Neuromorphic Outlook
M. Dincic, A. Bizzarri, D. Bertozzi, R.T. Syed, E. Jones
Proc. 29th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2026), (2026)
DOI: 10.1109/DDECS69233.2026.11521015, (AIDA4Edge)
(8) Towards Programmable Infrastructure for Organic and Flexible 6G Networks
F. Eichhorn, R. Bless, P. Seehofer, M. Gundall, D. Lindenschmitt, B. Bloessl, D. Volz, N. Keshtiarast, H. Borchert, M. Petri, E.-R. Modroiu, J. John, H. Mohammadalizadeh, T. Radig, L. Paeleke, H. Ackermann, D. Hauer, M.-I. Corici, M. Petrova, T. Magedanz, H.D. Schotten
IEEE Access 14, 1 (2026)
DOI: 10.1109/ACCESS.2026.3675437, (Open 6G Hub)
The next generation of wireless mobile networks will be driven by software and infrastructure virtualization. At the same time, the underlying hardware will become more diverse. Edge, intermediate and central network nodes will allow distributed deployments of never seen before scale. Non-terrestrial networks, nomadic networks and networks in networks promise more dynamicity, changing their topologies over time in predictable and unpredictable ways. To handle the complexity and dynamicity, a highly flexible and adaptable network is required. The key enablers of this complex digital communication system will be programmable infrastructures. From programmable access and flexible backhauls to zero-touch, adaptable and resilient control planes, we conducted research into advanced programmability at different layers of the network, within the Open6GHub project. In this article, we present innovative solutions for advanced programmable network infrastructure and show why they are essential for our vision of the programmable infrastructure of future wireless mobile networks.
(9) Sideband/Image-Rejection Up-/Down-Converter Transceiver RFIC for Scalable 5G mm-Wave Phased-Array Antenna Systems
A. Franzese, B. Sütbas, N. Maletic, A. Malignaggi, R. Negra, C. Carta
Proc. 37th Asia-Pacific Microwave Conference (APMC 2025), (2026)
DOI: 10.1109/APMC65046.2025.11379226
(10) UPSET: A Comprehensive Probabilistic Single Event Transient Analysis Flow for VLSI Circuits using Static Timing Analysis
C. Georgakidis, D. Valiantzas, N. Chatzivangelis, M. Andjelkovic, C. Sotiriou, M. Krstic
Electronics (MDPI) 15(4), 818 (2026)
DOI: 10.3390/electronics15040818, (TWIN-RELECT)
The downscaling of VLSI technologies has exacerbated the susceptibility of integrated circuits (ICs) to radiation-induced Single Event Transients (SETs). This work presents UPSET, a comprehensive and technology-independent EDA framework for probabilistic SET analysis using Static Timing Analysis (STA). Unlike traditional simulation-based methods that suffer from prohibitive runtimes, UPSET leverages graph-based propagation with advanced logical, electrical, and timing-window masking models to evaluate circuit sensitivity efficiently. Key contributions include a novel "Electrical Masking Window" (EMW) criterion that effectively filters non-full-rail pulses early in reconvergent logic, and a TimeStamp-based propagation mode that accurately handles complex signal reconvergence with Boolean evaluation. Experimental results over some featuring benchmarks demonstrate over 25,000× speedup compared to SPICE, while maintaining a tight 4.56% error bound in pulse width estimation. Moreover, experimental validation on 50 benchmarks across varying complexities showcases that EMW enhancement reduces the pessimism to circuit sensitivity by up to 25% on average, providing tighter upper bounds while maintaiing scalability to million-gate designs. By integrating seamlessly with standard industrial formats (LEF/DEF/LIB/SPEF), UPSET enables scalable, accurate soft SET sensitivity assessment for modern digital designs, establishing a robust foundation for automated radiation hardening flows.
(11) Optimizing Beamforming and Transmit Power for Improving mmWave Wireless Network Performance
P. Geranmayeh, E. Grass
Proc. IEEE International Conference on AI for Sustainable Innovation (AI-SI 2025), (2026)
DOI: 10.1109/AI-SI66213.2025.11340944, (IHP - Humboldt-Universität Joint-Lab)
(12) Optimizing Beamforming and Transmit Power for Improving mmWave Wireless Network Performance
P. Geranmayeh, E. Grass
Proc. IEEE International Conference on AI for Sustainable Innovation (AI-SI 2025), (2026)
DOI: 10.1109/AI-SI66213.2025.11340944, (5G-REMOTE)
(13) Energy-Efficient and Intelligent RAN Evolution for B5G and 6G
J. Gutiérrez Teran, M. Ghoraishi, M. Catalán-Cid, S. Pryor
BeGREEN Project Final White Paper (March 2026)
DOI: 10.5281/zenodo.19484593, (BeGREEN)
(14) On-Chip Slotted Patch Antenna at 226-244 GHz in SiGe Cu-Backend Technology
R. Hasan, D. Cvetkovski, F.A. Dürrwald, S. Dilek, U. Maß, A. Bhutani, M.H. Eissa, B. Sütbas, D. Kissinger, C. Carta
Proc. 37th Asia-Pacific Microwave Conference (APMC 2025), (2026)
DOI: 10.1109/APMC65046.2025.11378886, (iCampus II)
(15) Mobility-Induced Sensitivity of UAV-based Nodes to Jamming in Private 5G Airfield Networks - An Experimental Study
P. Mykytyn, R. Chitauro, O. Yener, P. Langendörfer
Proc. iCampus Cottbus Conference (iCCC 2026), 268 (2026)
DOI: 10.5162/iCCC2026/P37
(16) Unsourced Random Access: A Comprehensive Survey
M. Özates, M.J. Ahmadi, M. Kazemi, D. Gündüz, T.M. Duman
IEEE Communications Surveys & Tutorials 28, 955 (2026)
DOI: 10.1109/COMST.2025.3637685, (6G-RIC)
The sixth generation and beyond communication systems are expected to enable communications of a massive number of machine-type devices. The traffic generated by some of these devices will significantly deviate from those in conventional communication scenarios. For instance, for applications where a massive number of cheap sensors communicate with a base station (BS), the devices will only be sporadically active and there will be no coordination among them or with the BS. For such systems requiring massive random access solutions, a new paradigm called unsourced random access (URA) has been proposed. In URA, all the users employ the same codebook and there is no user identity during the data transmission phase. The destination is only interested in the list of messages being sent from the set of active users.
In this survey, we provide a comprehensive overview of existing URA solutions with an emphasis on the state-of-the-art, covering both algorithmic and information-theoretic aspects. Moreover, we provide future research directions and challenges, and describe some potential methods of addressing them.
(17) ICAS-Enabled Predictive Beam-Steering for Link Blockage Mitigation in Millimeter-Wave Systems
M. Petri, N. Maletic
Proc. 6th IEEE International Symposium on Joint Communications & Sensing (JC&S 2026), (2026)
DOI: 10.1109/JCS69321.2026.11366018, (Open 6G Hub)
(18) Demonstration of ICAS-enabled Environment Perception and Beam Adaptation for mmWave Link Blockage Mitigation
M. Petri, N. Maletic
Proc. 17th German Microwave Conference (GeMiC 2026), (2026)
DOI: 10.1109/GeMiC71240.2026.11516402, (Open 6G Hub)
(19) Riemannian Optimization on the Manifold of Unitary and Symmetric Matrices with Application to BD-RIS-Assisted Systems
I. Santamaria, M. Soleymani, E. Jorswieck, J. Gutierrez Teran, C. Beltran
Proc. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2026), 531 (2026)
DOI: 10.1109/ICASSP55912.2026.11460513
(20) Latch Based Design for Fast Voltage Droop Response
S. Srinivas, I.W. Jones, G. Panic, C. Lenzen
zu finden unter: https://arxiv.org/abs/2501.18843
(21) Efficient Reliability-Aware Hardware Trojan Design and Insertion for SET-Induced Soft Error Attacks
A. Takou, G. Paliaroutis, P. Tsoumanis, M. Andjelkovic, F. Vargas, N. Evmorfopoulos, G. Stamoulis
Electronics (MDPI) 15(2), 425 (2026)
DOI: 10.3390/electronics15020425, (TWIN-RELECT)
Soft errors and Hardware Trojans (HTs) constitute major reliability concerns, and in combination they can pose an even greater threat to circuit security. The main aim of this research is to develop and implement a reliability-based HT and to identify the optimal regions for its injection, enabling the creation of challenging benchmarks for evaluating detection techniques. In this context, a reliability-based HT is designed and evaluated using different components to achieve the required time overhead. Next, a method that combines the generation and propagation of Single-Event Transients (SETs), while accounting for both masking effects and the design’s timing constraints, is employed to efficiently identify the most vulnerable and critical gates. The sensitive gates selected for HT insertion exhibit 50–70% vulnerability to soft errors. At the same time, their insertion and the resulting path delay overhead must not violate the design’s timing constraints, and the additional area must remain below 10% of the total area. These three conditions ensure that the inserted HTs remain stealthy and, therefore, challenging to detect. The experimental results demonstrate that selecting this category of gates is highly effective, as it leads to a significant increase in the number of soft errors and, consequently, aggravates circuit vulnerability with minimal impact on the design. On average, the targeted gates exhibit a 130% increase in sensitivity, and the overall Soft Error Rate (SER) increases by 78%, confirming the importance of providing robust benchmarks to combat potential attacks of this kind.
(22) Auf dem Weg zur radarbasierten Rinderüberwachung: Erste Überlegungen, Aufbauten und Ergebnisse
M. Ulbricht, V. Sark, R.T. Syed, J. Gose, G. Hoffmann
Proc. iCampµs Cottbus Conference (iCCC 2026), 90 (2026)
DOI: 10.5162/iCCC2026/5.4, (iCampus II)
(23) On-Chip Sensor with Programmable Delay Logic to Monitor Memory Aging Evolution
F. Vargas, V. Galstyan, G. Harutyunyan, Y. Zorian
Proc. 29th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2026), (2026)
DOI: 10.1109/DDECS69233.2026.11520974
(24) Embedded Tutorial: Considerations on the Design of Resilient 2.5/3D Heterogeneous Integration, Multilayer Interposer Systems for Chip Lifecycle Management
F. Vargas, M. Andjelkovic, C. Sotirio
Proc. 29th IEEE International Symposium on Design and Diagnostics of Electronic Circuit and Systems (DDECS 2026), (2026)
DOI: 10.1109/DDECS69233.2026.11521006, (TWIN-RELECT)
(25) ReFFT: An Energy-Efficient RRAM-Based FFT Accelerator
J. Wen, A. Baroni, M. Uhlmann, E. Perez, Ch. Wenger, M. Krstic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 45(6), 2620 (2026)
DOI: 10.1109/TCAD.2025.3627146, (INSEKT)
The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector–matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.
(26) RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference
J. Wen, A. Baroni, Ch. Wenger, M. Krstic, L.M. Bolzani Poehls
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 34(3), 809 (2026)
DOI: 10.1109/TVLSI.2025.3644141, (6G-RIC)
The growing computational demands of convolutional neural networks (CNNs) have motivated the use of spectral-domain inference as an alternative to costly spatial-domain convolutions. In this work, we propose an resistive RAM (RRAM)-based spectral-domain convolutional layer that exploits in-memory computing (IMC) for low energy consumption and high parallelism. Both the two-dimensional Fourier transform and the pointwise multiplications are directly implemented on RRAM crossbar arrays, while Hermitian symmetry is leveraged to further enhance the energy efficiency of the transform and subsequent spectral processing. To ensure robustness, measured RRAM device data are incorporated into system-level simulations to evaluate the impact of device variability on inference accuracy. Furthermore, we introduce a layer-wise mapping framework that adaptively selects between spatial- and spectral-domain execution based on the trade-off between energy efficiency and accuracy. Simulation results show that the proposed design achieves up to a 2.18× improvement in energy efficiency across convolutional layer configurations. For VGG-8 on CIFAR-100, the proposed architecture with the layer-wise mapping scheme reduces the energy–delay product (EDP) by 45% while incurring negligible accuracy loss. This work presents the first complete RRAM-based spectral-domain convolutional layer that accounts for device variability, providing a promising solution for edge CNN inference.
(27) ReFFT: An Energy-Efficient RRAM-Based FFT Accelerator
J. Wen, A. Baroni, M. Uhlmann, E. Perez, Ch. Wenger, M. Krstic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 45(6), 2620 (2026)
DOI: 10.1109/TCAD.2025.3627146, (6G-RIC)
The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector–matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.
(28) RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference
J. Wen, A. Baroni, Ch. Wenger, M. Krstic, L.M. Bolzani Poehls
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 34(3), 809 (2026)
DOI: 10.1109/TVLSI.2025.3644141, (INSEKT)
The growing computational demands of convolutional neural networks (CNNs) have motivated the use of spectral-domain inference as an alternative to costly spatial-domain convolutions. In this work, we propose an resistive RAM (RRAM)-based spectral-domain convolutional layer that exploits in-memory computing (IMC) for low energy consumption and high parallelism. Both the two-dimensional Fourier transform and the pointwise multiplications are directly implemented on RRAM crossbar arrays, while Hermitian symmetry is leveraged to further enhance the energy efficiency of the transform and subsequent spectral processing. To ensure robustness, measured RRAM device data are incorporated into system-level simulations to evaluate the impact of device variability on inference accuracy. Furthermore, we introduce a layer-wise mapping framework that adaptively selects between spatial- and spectral-domain execution based on the trade-off between energy efficiency and accuracy. Simulation results show that the proposed design achieves up to a 2.18× improvement in energy efficiency across convolutional layer configurations. For VGG-8 on CIFAR-100, the proposed architecture with the layer-wise mapping scheme reduces the energy–delay product (EDP) by 45% while incurring negligible accuracy loss. This work presents the first complete RRAM-based spectral-domain convolutional layer that accounts for device variability, providing a promising solution for edge CNN inference.
