Publications 2026
Script list Publications
(1) Advanced Machine Learning-Based Eco-Integrated Model for Predicting Potato Late Blight in Multiple Cultivation Systems
P. Bagchi, B. Sawicka, Z. Stamenkovic, P. Barbas, P. Pszczolkowski, D. Markovic, D. Bhattacharjee
Facta Universitatis, Series: Electronics and Energetics 39(1), 219 (2026)
DOI: 10.2298/FUEE2601219B, (BB-KI-Chips)
This paper presents a machine learning–driven framework for analyzing and predicting potato late blight (caused by Phytophthora infestans) across two distinct cultivation systems—ecological and integrated—using six potato varieties. Traditional statistical methods, including a two-factor Analysis of Variance (ANOVA) and Tukey’s Honest Significant Difference (HSD) test, were applied to assess the effects of cultivation systems, potato varieties, and year. To enhance predictive accuracy and model interpretability, an advanced machine learning pipeline, termed the Eco-Integrated Model, was developed. This model integrates SMOTE (Synthetic Minority Oversampling Technique) for handling class imbalance, SHAP (SHapley Additive xPlanations) for interpretability and feature importance analysis, and the CatBoost classifier for robust, high-performance prediction. The dataset, collected over three years (2018–2020), includes multi-varietal and system-specific records of late blight incidence for both ecological integrated-based data, serving as input for model training and evaluation. The proposed Eco-Integrated Model demonstrated high predictive capability, revealing that integrated cultivation systems are generally more effective at suppressing disease progression. Moreover, substantial varietal differences were identified in late blight susceptibility, as highlighted by both statistical and machine learning analyses. These findings underline the value of incorporating explainable, data-driven approaches into plant disease forecasting. The Eco-Integrated Model offers a scalable, interpretable, and accurate predictive solution, contributing to precision agriculture practices and supporting evidence-based decision-making for sustainable potato production and disease management strategies.
(2) Towards Programmable Infrastructure for Organic and Flexible 6G Networks
F. Eichhorn, R. Bless, P. Seehofer, M. Gundall, D. Lindenschmitt, B. Bloessl, D. Volz, N. Keshtiarast, H. Borchert, M. Petri, E.-R. Modroiu, J. John, H. Mohammadalizadeh, T. Radig, L. Paeleke, H. Ackermann, D. Hauer, M.-I. Corici, M. Petrova, T. Magedanz, H.D. Schotten
IEEE Access 14, 1 (2026)
DOI: 10.1109/ACCESS.2026.3675437, (Open 6G Hub)
The next generation of wireless mobile networks will be driven by software and infrastructure virtualization. At the same time, the underlying hardware will become more diverse. Edge, intermediate and central network nodes will allow distributed deployments of never seen before scale. Non-terrestrial networks, nomadic networks and networks in networks promise more dynamicity, changing their topologies over time in predictable and unpredictable ways. To handle the complexity and dynamicity, a highly flexible and adaptable network is required. The key enablers of this complex digital communication system will be programmable infrastructures. From programmable access and flexible backhauls to zero-touch, adaptable and resilient control planes, we conducted research into advanced programmability at different layers of the network, within the Open6GHub project. In this article, we present innovative solutions for advanced programmable network infrastructure and show why they are essential for our vision of the programmable infrastructure of future wireless mobile networks.
(3) UPSET: A Comprehensive Probabilistic Single Event Transient Analysis Flow for VLSI Circuits using Static Timing Analysis
C. Georgakidis, D. Valiantzas, N. Chatzivangelis, M. Andjelkovic, C. Sotiriou, M. Krstic
Electronics (MDPI) 15(4), 818 (2026)
DOI: 10.3390/electronics15040818, (TWIN-RELECT)
The downscaling of VLSI technologies has exacerbated the susceptibility of integrated circuits (ICs) to radiation-induced Single Event Transients (SETs). This work presents UPSET, a comprehensive and technology-independent EDA framework for probabilistic SET analysis using Static Timing Analysis (STA). Unlike traditional simulation-based methods that suffer from prohibitive runtimes, UPSET leverages graph-based propagation with advanced logical, electrical, and timing-window masking models to evaluate circuit sensitivity efficiently. Key contributions include a novel "Electrical Masking Window" (EMW) criterion that effectively filters non-full-rail pulses early in reconvergent logic, and a TimeStamp-based propagation mode that accurately handles complex signal reconvergence with Boolean evaluation. Experimental results over some featuring benchmarks demonstrate over 25,000× speedup compared to SPICE, while maintaining a tight 4.56% error bound in pulse width estimation. Moreover, experimental validation on 50 benchmarks across varying complexities showcases that EMW enhancement reduces the pessimism to circuit sensitivity by up to 25% on average, providing tighter upper bounds while maintaiing scalability to million-gate designs. By integrating seamlessly with standard industrial formats (LEF/DEF/LIB/SPEF), UPSET enables scalable, accurate soft SET sensitivity assessment for modern digital designs, establishing a robust foundation for automated radiation hardening flows.
(4) Unsourced Random Access: A Comprehensive Survey
M. Özates, M.J. Ahmadi, M. Kazemi, D. Gündüz, T.M. Duman
IEEE Communications Surveys & Tutorials 28, 955 (2026)
DOI: 10.1109/COMST.2025.3637685, (6G-RIC)
The sixth generation and beyond communication systems are expected to enable communications of a massive number of machine-type devices. The traffic generated by some of these devices will significantly deviate from those in conventional communication scenarios. For instance, for applications where a massive number of cheap sensors communicate with a base station (BS), the devices will only be sporadically active and there will be no coordination among them or with the BS. For such systems requiring massive random access solutions, a new paradigm called unsourced random access (URA) has been proposed. In URA, all the users employ the same codebook and there is no user identity during the data transmission phase. The destination is only interested in the list of messages being sent from the set of active users.
In this survey, we provide a comprehensive overview of existing URA solutions with an emphasis on the state-of-the-art, covering both algorithmic and information-theoretic aspects. Moreover, we provide future research directions and challenges, and describe some potential methods of addressing them.
(5) Demonstration of ICAS-enabled Environment Perception and Beam Adaptation for mmWave Link Blockage Mitigation
M. Petri, N. Maletic
Proc. 17th German Microwave Conference (GeMiC 2026), (2026)
(Open 6G Hub)
(6) ICAS-Enabled Predictive Beam-Steering for Link Blockage Mitigation in Millimeter-Wave Systems
M. Petri, N. Maletic
Proc. 6th IEEE International Symposium on Joint Communications & Sensing (JC&S 2026), (2026)
DOI: 10.1109/JCS69321.2026.11366018, (Open 6G Hub)
(7) Latch Based Design for Fast Voltage Droop Response
S. Srinivas, I.W. Jones, G. Panic, C. Lenzen
zu finden unter: https://arxiv.org/abs/2501.18843
(8) Efficient Reliability-Aware Hardware Trojan Design and Insertion for SET-Induced Soft Error Attacks
A. Takou, G. Paliaroutis, P. Tsoumanis, M. Andjelkovic, F. Vargas, N. Evmorfopoulos, G. Stamoulis
Electronics (MDPI) 15(2), 425 (2026)
DOI: 10.3390/electronics15020425, (TWIN-RELECT)
Soft errors and Hardware Trojans (HTs) constitute major reliability concerns, and in combination they can pose an even greater threat to circuit security. The main aim of this research is to develop and implement a reliability-based HT and to identify the optimal regions for its injection, enabling the creation of challenging benchmarks for evaluating detection techniques. In this context, a reliability-based HT is designed and evaluated using different components to achieve the required time overhead. Next, a method that combines the generation and propagation of Single-Event Transients (SETs), while accounting for both masking effects and the design’s timing constraints, is employed to efficiently identify the most vulnerable and critical gates. The sensitive gates selected for HT insertion exhibit 50–70% vulnerability to soft errors. At the same time, their insertion and the resulting path delay overhead must not violate the design’s timing constraints, and the additional area must remain below 10% of the total area. These three conditions ensure that the inserted HTs remain stealthy and, therefore, challenging to detect. The experimental results demonstrate that selecting this category of gates is highly effective, as it leads to a significant increase in the number of soft errors and, consequently, aggravates circuit vulnerability with minimal impact on the design. On average, the targeted gates exhibit a 130% increase in sensitivity, and the overall Soft Error Rate (SER) increases by 78%, confirming the importance of providing robust benchmarks to combat potential attacks of this kind.
(9) RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference
J. Wen, A. Baroni, Ch. Wenger, M. Krstic, L.M. Bolzani Pöhls
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 34(3), 809 (2026)
DOI: 10.1109/TVLSI.2025.3644141, (INSEKT)
The growing computational demands of convolutional neural networks (CNNs) have motivated the use of spectral-domain inference as an alternative to costly spatial-domain convolutions. In this work, we propose an resistive RAM (RRAM)-based spectral-domain convolutional layer that exploits in-memory computing (IMC) for low energy consumption and high parallelism. Both the two-dimensional Fourier transform and the pointwise multiplications are directly implemented on RRAM crossbar arrays, while Hermitian symmetry is leveraged to further enhance the energy efficiency of the transform and subsequent spectral processing. To ensure robustness, measured RRAM device data are incorporated into system-level simulations to evaluate the impact of device variability on inference accuracy. Furthermore, we introduce a layer-wise mapping framework that adaptively selects between spatial- and spectral-domain execution based on the trade-off between energy efficiency and accuracy. Simulation results show that the proposed design achieves up to a 2.18× improvement in energy efficiency across convolutional layer configurations. For VGG-8 on CIFAR-100, the proposed architecture with the layer-wise mapping scheme reduces the energy–delay product (EDP) by 45% while incurring negligible accuracy loss. This work presents the first complete RRAM-based spectral-domain convolutional layer that accounts for device variability, providing a promising solution for edge CNN inference.
(10) RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference
J. Wen, A. Baroni, Ch. Wenger, M. Krstic, L.M. Bolzani Pöhls
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 34(3), 809 (2026)
DOI: 10.1109/TVLSI.2025.3644141, (6G-RIC)
The growing computational demands of convolutional neural networks (CNNs) have motivated the use of spectral-domain inference as an alternative to costly spatial-domain convolutions. In this work, we propose an resistive RAM (RRAM)-based spectral-domain convolutional layer that exploits in-memory computing (IMC) for low energy consumption and high parallelism. Both the two-dimensional Fourier transform and the pointwise multiplications are directly implemented on RRAM crossbar arrays, while Hermitian symmetry is leveraged to further enhance the energy efficiency of the transform and subsequent spectral processing. To ensure robustness, measured RRAM device data are incorporated into system-level simulations to evaluate the impact of device variability on inference accuracy. Furthermore, we introduce a layer-wise mapping framework that adaptively selects between spatial- and spectral-domain execution based on the trade-off between energy efficiency and accuracy. Simulation results show that the proposed design achieves up to a 2.18× improvement in energy efficiency across convolutional layer configurations. For VGG-8 on CIFAR-100, the proposed architecture with the layer-wise mapping scheme reduces the energy–delay product (EDP) by 45% while incurring negligible accuracy loss. This work presents the first complete RRAM-based spectral-domain convolutional layer that accounts for device variability, providing a promising solution for edge CNN inference.
P. Bagchi, B. Sawicka, Z. Stamenkovic, P. Barbas, P. Pszczolkowski, D. Markovic, D. Bhattacharjee
Facta Universitatis, Series: Electronics and Energetics 39(1), 219 (2026)
DOI: 10.2298/FUEE2601219B, (BB-KI-Chips)
This paper presents a machine learning–driven framework for analyzing and predicting potato late blight (caused by Phytophthora infestans) across two distinct cultivation systems—ecological and integrated—using six potato varieties. Traditional statistical methods, including a two-factor Analysis of Variance (ANOVA) and Tukey’s Honest Significant Difference (HSD) test, were applied to assess the effects of cultivation systems, potato varieties, and year. To enhance predictive accuracy and model interpretability, an advanced machine learning pipeline, termed the Eco-Integrated Model, was developed. This model integrates SMOTE (Synthetic Minority Oversampling Technique) for handling class imbalance, SHAP (SHapley Additive xPlanations) for interpretability and feature importance analysis, and the CatBoost classifier for robust, high-performance prediction. The dataset, collected over three years (2018–2020), includes multi-varietal and system-specific records of late blight incidence for both ecological integrated-based data, serving as input for model training and evaluation. The proposed Eco-Integrated Model demonstrated high predictive capability, revealing that integrated cultivation systems are generally more effective at suppressing disease progression. Moreover, substantial varietal differences were identified in late blight susceptibility, as highlighted by both statistical and machine learning analyses. These findings underline the value of incorporating explainable, data-driven approaches into plant disease forecasting. The Eco-Integrated Model offers a scalable, interpretable, and accurate predictive solution, contributing to precision agriculture practices and supporting evidence-based decision-making for sustainable potato production and disease management strategies.
(2) Towards Programmable Infrastructure for Organic and Flexible 6G Networks
F. Eichhorn, R. Bless, P. Seehofer, M. Gundall, D. Lindenschmitt, B. Bloessl, D. Volz, N. Keshtiarast, H. Borchert, M. Petri, E.-R. Modroiu, J. John, H. Mohammadalizadeh, T. Radig, L. Paeleke, H. Ackermann, D. Hauer, M.-I. Corici, M. Petrova, T. Magedanz, H.D. Schotten
IEEE Access 14, 1 (2026)
DOI: 10.1109/ACCESS.2026.3675437, (Open 6G Hub)
The next generation of wireless mobile networks will be driven by software and infrastructure virtualization. At the same time, the underlying hardware will become more diverse. Edge, intermediate and central network nodes will allow distributed deployments of never seen before scale. Non-terrestrial networks, nomadic networks and networks in networks promise more dynamicity, changing their topologies over time in predictable and unpredictable ways. To handle the complexity and dynamicity, a highly flexible and adaptable network is required. The key enablers of this complex digital communication system will be programmable infrastructures. From programmable access and flexible backhauls to zero-touch, adaptable and resilient control planes, we conducted research into advanced programmability at different layers of the network, within the Open6GHub project. In this article, we present innovative solutions for advanced programmable network infrastructure and show why they are essential for our vision of the programmable infrastructure of future wireless mobile networks.
(3) UPSET: A Comprehensive Probabilistic Single Event Transient Analysis Flow for VLSI Circuits using Static Timing Analysis
C. Georgakidis, D. Valiantzas, N. Chatzivangelis, M. Andjelkovic, C. Sotiriou, M. Krstic
Electronics (MDPI) 15(4), 818 (2026)
DOI: 10.3390/electronics15040818, (TWIN-RELECT)
The downscaling of VLSI technologies has exacerbated the susceptibility of integrated circuits (ICs) to radiation-induced Single Event Transients (SETs). This work presents UPSET, a comprehensive and technology-independent EDA framework for probabilistic SET analysis using Static Timing Analysis (STA). Unlike traditional simulation-based methods that suffer from prohibitive runtimes, UPSET leverages graph-based propagation with advanced logical, electrical, and timing-window masking models to evaluate circuit sensitivity efficiently. Key contributions include a novel "Electrical Masking Window" (EMW) criterion that effectively filters non-full-rail pulses early in reconvergent logic, and a TimeStamp-based propagation mode that accurately handles complex signal reconvergence with Boolean evaluation. Experimental results over some featuring benchmarks demonstrate over 25,000× speedup compared to SPICE, while maintaining a tight 4.56% error bound in pulse width estimation. Moreover, experimental validation on 50 benchmarks across varying complexities showcases that EMW enhancement reduces the pessimism to circuit sensitivity by up to 25% on average, providing tighter upper bounds while maintaiing scalability to million-gate designs. By integrating seamlessly with standard industrial formats (LEF/DEF/LIB/SPEF), UPSET enables scalable, accurate soft SET sensitivity assessment for modern digital designs, establishing a robust foundation for automated radiation hardening flows.
(4) Unsourced Random Access: A Comprehensive Survey
M. Özates, M.J. Ahmadi, M. Kazemi, D. Gündüz, T.M. Duman
IEEE Communications Surveys & Tutorials 28, 955 (2026)
DOI: 10.1109/COMST.2025.3637685, (6G-RIC)
The sixth generation and beyond communication systems are expected to enable communications of a massive number of machine-type devices. The traffic generated by some of these devices will significantly deviate from those in conventional communication scenarios. For instance, for applications where a massive number of cheap sensors communicate with a base station (BS), the devices will only be sporadically active and there will be no coordination among them or with the BS. For such systems requiring massive random access solutions, a new paradigm called unsourced random access (URA) has been proposed. In URA, all the users employ the same codebook and there is no user identity during the data transmission phase. The destination is only interested in the list of messages being sent from the set of active users.
In this survey, we provide a comprehensive overview of existing URA solutions with an emphasis on the state-of-the-art, covering both algorithmic and information-theoretic aspects. Moreover, we provide future research directions and challenges, and describe some potential methods of addressing them.
(5) Demonstration of ICAS-enabled Environment Perception and Beam Adaptation for mmWave Link Blockage Mitigation
M. Petri, N. Maletic
Proc. 17th German Microwave Conference (GeMiC 2026), (2026)
(Open 6G Hub)
(6) ICAS-Enabled Predictive Beam-Steering for Link Blockage Mitigation in Millimeter-Wave Systems
M. Petri, N. Maletic
Proc. 6th IEEE International Symposium on Joint Communications & Sensing (JC&S 2026), (2026)
DOI: 10.1109/JCS69321.2026.11366018, (Open 6G Hub)
(7) Latch Based Design for Fast Voltage Droop Response
S. Srinivas, I.W. Jones, G. Panic, C. Lenzen
zu finden unter: https://arxiv.org/abs/2501.18843
(8) Efficient Reliability-Aware Hardware Trojan Design and Insertion for SET-Induced Soft Error Attacks
A. Takou, G. Paliaroutis, P. Tsoumanis, M. Andjelkovic, F. Vargas, N. Evmorfopoulos, G. Stamoulis
Electronics (MDPI) 15(2), 425 (2026)
DOI: 10.3390/electronics15020425, (TWIN-RELECT)
Soft errors and Hardware Trojans (HTs) constitute major reliability concerns, and in combination they can pose an even greater threat to circuit security. The main aim of this research is to develop and implement a reliability-based HT and to identify the optimal regions for its injection, enabling the creation of challenging benchmarks for evaluating detection techniques. In this context, a reliability-based HT is designed and evaluated using different components to achieve the required time overhead. Next, a method that combines the generation and propagation of Single-Event Transients (SETs), while accounting for both masking effects and the design’s timing constraints, is employed to efficiently identify the most vulnerable and critical gates. The sensitive gates selected for HT insertion exhibit 50–70% vulnerability to soft errors. At the same time, their insertion and the resulting path delay overhead must not violate the design’s timing constraints, and the additional area must remain below 10% of the total area. These three conditions ensure that the inserted HTs remain stealthy and, therefore, challenging to detect. The experimental results demonstrate that selecting this category of gates is highly effective, as it leads to a significant increase in the number of soft errors and, consequently, aggravates circuit vulnerability with minimal impact on the design. On average, the targeted gates exhibit a 130% increase in sensitivity, and the overall Soft Error Rate (SER) increases by 78%, confirming the importance of providing robust benchmarks to combat potential attacks of this kind.
(9) RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference
J. Wen, A. Baroni, Ch. Wenger, M. Krstic, L.M. Bolzani Pöhls
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 34(3), 809 (2026)
DOI: 10.1109/TVLSI.2025.3644141, (INSEKT)
The growing computational demands of convolutional neural networks (CNNs) have motivated the use of spectral-domain inference as an alternative to costly spatial-domain convolutions. In this work, we propose an resistive RAM (RRAM)-based spectral-domain convolutional layer that exploits in-memory computing (IMC) for low energy consumption and high parallelism. Both the two-dimensional Fourier transform and the pointwise multiplications are directly implemented on RRAM crossbar arrays, while Hermitian symmetry is leveraged to further enhance the energy efficiency of the transform and subsequent spectral processing. To ensure robustness, measured RRAM device data are incorporated into system-level simulations to evaluate the impact of device variability on inference accuracy. Furthermore, we introduce a layer-wise mapping framework that adaptively selects between spatial- and spectral-domain execution based on the trade-off between energy efficiency and accuracy. Simulation results show that the proposed design achieves up to a 2.18× improvement in energy efficiency across convolutional layer configurations. For VGG-8 on CIFAR-100, the proposed architecture with the layer-wise mapping scheme reduces the energy–delay product (EDP) by 45% while incurring negligible accuracy loss. This work presents the first complete RRAM-based spectral-domain convolutional layer that accounts for device variability, providing a promising solution for edge CNN inference.
(10) RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference
J. Wen, A. Baroni, Ch. Wenger, M. Krstic, L.M. Bolzani Pöhls
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 34(3), 809 (2026)
DOI: 10.1109/TVLSI.2025.3644141, (6G-RIC)
The growing computational demands of convolutional neural networks (CNNs) have motivated the use of spectral-domain inference as an alternative to costly spatial-domain convolutions. In this work, we propose an resistive RAM (RRAM)-based spectral-domain convolutional layer that exploits in-memory computing (IMC) for low energy consumption and high parallelism. Both the two-dimensional Fourier transform and the pointwise multiplications are directly implemented on RRAM crossbar arrays, while Hermitian symmetry is leveraged to further enhance the energy efficiency of the transform and subsequent spectral processing. To ensure robustness, measured RRAM device data are incorporated into system-level simulations to evaluate the impact of device variability on inference accuracy. Furthermore, we introduce a layer-wise mapping framework that adaptively selects between spatial- and spectral-domain execution based on the trade-off between energy efficiency and accuracy. Simulation results show that the proposed design achieves up to a 2.18× improvement in energy efficiency across convolutional layer configurations. For VGG-8 on CIFAR-100, the proposed architecture with the layer-wise mapping scheme reduces the energy–delay product (EDP) by 45% while incurring negligible accuracy loss. This work presents the first complete RRAM-based spectral-domain convolutional layer that accounts for device variability, providing a promising solution for edge CNN inference.
