IHP : Schedule & Price List

MPW Schedule 2026 & 2027 and Price Information 2026

General Technology Description

IHP offers standard 0.13 and 0.25 μm CMOS processes which provide NMOS, PMOS, isolated NMOS and passive components such as poly resistors and MIM capacitors. In addition to the standard CMOS processes different front-end-of-line options are offered. In 0.25 μm CMOS the standard aluminum BEOL backend offers 3 thin metal layers and two TopMetal layers (TopMetal1 - fourth 2 μm thick metal layer, TopMetal2 – fifth 3 μm thick metal layer). The Al-BEOL backend for 0.13 μm process offers 5 thin and 2 thick metal layers (TM1: 2 μm TM2: 3 μm). Together with a high dielectric stack this enables increased performance of the passive RF components.

Technologies with an enhanced copper BEOL option are offered.

Technologies for MPW & Prototyping

SG13S	A high-performance 0.13 µm BiCMOS with npn-HBTs up to f_T / f_max= 250/340 GHz, with 3.3 V I/O CMOS and 1.2 V logic CMOS.
SG13G2	A 0.13 µm BiCMOS technology with much higher bipolar performance of f_T/f_max = 350/450 GHz.
SG13CMOS‍	A RF CMOS technology which includes all features of SG13G2, but no bipolar HBTs
SG13CMOS5L	A CMOS technology offered for open-source education designs and which includes front-end of SG13CMOS, but noisolated NMOS, further only 4 thin metal layer and one 2μm thick TopMetal and no MIM capacitor
SG13SCu	FEOL process SG13S together with 8 layer Cu BEOL option from X-FAB containing 4 thin Cu layers, 2 thick 3 µm Cu layers, a thin Al layer with 2 fF/µm MIM capacitor and a 2.8 µm Al top layer.
SG13G2Cu	FEOL process SG13G2 together with 8 layer Cu BEOL option from X-FAB containing 4 thin Cu layers, 2 thick 3 µm Cu layers, a thin Al layer with 2 fF/µm MIM capacitor and a 2.8 µm Al top layer.
SG13G3Cu	IHP´s highest performance HBT’s with ft/fmax = 470/650 GHz. The process offers a 8-layer Cu-BEOL from X-FAB containing 4 thin Cu layers, 2 thick 3μm Cu layers, a thin Al layer with 2 fF/μm MIM capacitor and a 2.8 μm Aluminum top layer. This technology offers CMOS devices with 130 nm gate length and 1.2 V core voltage and high voltage CMOS devices with 3.3 V core voltage.
SG25H7_EPIC	A monolithic photonic BiCMOS technology combining 0.25 µm CMOS, high-performance npn HBTs (f_T / f_max = >350/>500 GHz), and full photonic device set for C/O-band.
SGB25RH	Is a special variant of SGB25V which includes radiation hard IP for space applications.
INTM4TM2 ‍	Interposer technology which offers 2 thin and 2 thick Al-BEOL layer on a high resistivity substrate. Further is contains a MIM capacitor and a Thin film resistor.

A cadence-based mixed signal design kit is available. For high frequency designs an analogue Design Kit in ADS can be used. IHP's reusable blocks and IPs for wireless and broadband are offered to support your designs.

The following Modules are available

LBE	The Localized Backside Etching module is offered to remove silicon locally to improve passive properties (available in all Al-BEOL technologies).
H7PIC	Includes additional photonic design layers along with BiCMOS BEOL layers on SOI wafers.
TSV	An additional option in SG13S and SG13G2 technology that provides RF grounding by vias through silicon to improve RF performance.
MEMRES (RRAM)	An RRAM based fully CMOS integrated memristive module based on resistive TiN / HfO2-x / TiN switching devices in SG13G2 technology, along with a Process Design Kit including layout and VerilogA simulation model.

2.1 MPW Price Information 2026

Non-Commercial Access

For European non-profit and educational institutions, special discounts are offered for research projects via EUROPRACTICE.

2.1.1 Prices for Technologies

Process	Area Price / mm²
SGB25RH	€ 3050
SG25H7_EPIC	€ 9000
SG13S	€ 6300
SG13C	€ 4500
SG13G2	€ 7300
SG13G3	€ 9000
SG13SCu	€ 6300
SG13G2Cu	€ 7300
SG13G3Cu	€ 9000

2.1.2 Prices for Modules

Module (Process)	Price
LBE (all Al BEOL)	€ 5000 per order and technology
BEOL (only) 0.13 µm (SG13)	€ 1300 (per mm²)
SG25_H7PIC	€ 3800 (per mm²)
TSV (S, G2)	€ 12500 per order
MEMRES (G2)	€ 2500 per Run + € 600 per mm²
INTM4TM2	€ 900 (per mm²)

2.2 MPW Schedule

There is a minimum area requirement of only 0.8 mm² for all runs with bold shipment times. For all technologies or modules marked in brackets, minimum area order is required. For details see chapter 2.4. TAPE IN time is given in a column “TAPE IN”, shipment time in corresponding table cells.

Schedule for complete technologies

2026

TAPE IN	SG25	SG13
	EPIC H7	CMOS & CMOS5L**	S	MEMRES	SCu	G2Cu	G2	G3	G3Cu
Nov 3, 25	Jul 13
Nov 24, 25		May 18*
Dec 8, 25			Sep 21*	Oct 08*	Aug 13*	Jun 29	Jun 10	Jul 26	Jul 09
Mar 16, 26						Sep 07			Sep 17
Mar 30, 26		Oct 02*
Jun 1, 26			Mar 15*	Feb 04*			Dec 16
Jul 13, 26		Dec 16*
Aug 31, 26			May 18*		May 10*	Mar 05	Apr 12	Apr 19	Mar 04
Oct 6, 26							Jun 30**
Nov 2, 26	Jul 05
Nov 16, 26		May 10*
Dec 7, 26			Sep 20*	Jul 02*	Aug 12*	Jun 28	Jun 16	Jun 22	Jul 08

* Runs with lower priority
** Open-Source MPW Runs with special conditions, which you can find here.

2027

Changes for 2027 schedule are possible till December 1st 2026.

TAPE IN	SG25	SG13
	EPIC H7	CMOS5L**	S	MEMRES	SCu	G2Cu	G2	G3	G3Cu
Nov 2, 26	Jul 05
Nov 16, 26		May 10*
Dec 7, 26			Sep 20*	Jul 02*	Aug 12*	Jun 28	Jun 16	Jun 22	Jul 08
Mar 15, 27						Sep 06
Mar 30, 27		Sep 16*
May 31, 27			Mar 13*	Feb 03*			Dec 15
Aug 30, 27			May 15*		May 04*	Feb 21	Apr 10	Apr 18	Mar 02
Oct 4, 27							Jun 25**
Nov 1, 27	Jul 03
Nov 15, 27		May 08*
Dec 6, 27			Sep 18*	Jun 30*	Aug 10*	Jun 26	Jun 14	Jun 20	Jul 06

* Runs with lower priority
** Open-Source MPW Runs with special conditions, which you can find here.

Local Backside Etching (LBE) is not offered for runs with Cu-BEOL from X-FAB. For all the other runs LBE is available and shipment will be 21 days later than the standard shipment. TSV and RDL modules is available for SG13S and SG13G2 technologies and for runs with low priority, it leads to a 35 days longer cycle time for TSV module.

2.2.1 BEOL (only)/Interposer/PIC runs

TAPE IN	SG13 BEOL	SG25_PIC_H7	IntM4TM2	TSV
Feb 9, 26		Aug 20
Apr 13, 26			Jul 01
Jun 15, 26	Oct 26			Dec 02*
Aug 24, 26			Nov 11

There might be internal runs, without confirmed schedule. Feel free to ask our customer support for more details if you are interested in joining such runs.

2.3 Information on Minimum Area per MPW Run

There is a minimum area requirement of only 0.8 mm² for selected technologies or module in schedule tables in chapter 2.2 and 2.3. This is valid for all technologies or modules marked with bold shipment times. For all technologies or modules marked with grey italic shipment times in brackets, minimum area order as given in the following table is required. A registration 4 weeks before TAPE out, followed by the confirmation from the foundry, is necessary in this case. By default these additional runs are without priority. A combination of 0.25 μm based runs and 0.13 μm based runs is not possible.

Process	Min Area [mm²]	Min Area¹ for Discount
SG25H7_EPIC	10	-
SGB25RH	25	-
SG13S	10	10
SG13CMOS	-	-
SG13G2	10	10
SG13G3	10	-
SG13SCu	10	10
SG13G2Cu	10	10
SG13G3Cu	10	10
SG25_H7PIC	12	12

¹ Ask for special price if you need more than this area for one MPW run.

Delivery

As default 40 diced samples will be delivered. Exceptions are designs using TSV module and SG25_H7PIC. Here 25 samples will be delivered by default. The delivery includes E-test data and RF measurements.

Back lapping options:

200 µm (no additional fee)
300 µm (no additional fee)
250 µm (additional fee)
150 µm (additional fee)
100 µm (additional fee)
75 µm (for TSV module only)

Research Engineering Runs

IHP is offering complete mask sets only for research purpose and prototyping. If customer specific modules are added to a qualified technology, this technology is considered as non-qualified with status “early access”. Prices for Research Engineering Runs can be given upon request.

IHP's General Terms and Conditions »