MPW Schedule 2024 & 2025 and Price Information 2024
General Technology Description
IHP offers standard 0.13 and 0.25 μm CMOS processes which provide NMOS, PMOS, isolated NMOS and passive components such as poly resistors and MIM capacitors. In addition to the standard CMOS processes different front-end-of-line options are offered. In 0.25 μm CMOS the standard backend offers 3 thin metal layers and two TopMetal layers (TopMetal1 - fourth 2 μm thick metal layer, TopMetal2 – fifth 3 μm thick metal layer). The backend for 0.13 μm process offers 5 thin and 2 thick metal layers (TM1: 2 μm TM2: 3 μm). Together with a high dielectric stack this enables increased performance of the passive RF components.
Technologies with an enhanced BEOL option with copper are offered.
Technologies for MPW & Prototyping
| SG13S | A high-performance 0.13 µm BiCMOS with npn-HBTs up to fT / fmax= 250/340 GHz, with 3.3 V I/O CMOS and 1.2 V logic CMOS. |
|---|---|
| SG13G2 | A 0.13 µm BiCMOS technology with much higher bipolar performance of fT/fmax = 350/450 GHz. |
| SG13SCu | FEOL process SG13S together with 8 layer Cu BEOL option from X-FAB containing 4 thin Cu layers, 2 thick 3 µm Cu layers, a thin Al layer with 2 fF/µm MIM capacitor and a 2.8 µm Al top layer. |
| SG13G2Cu | FEOL process SG13G2 together with 8 layer Cu BEOL option from X-FAB containing 4 thin Cu layers, 2 thick 3 µm Cu layers, a thin Al layer with 2 fF/µm MIM capacitor and a 2.8 µm Al top layer. |
| SG13G3Cu | IHP´s highest performance HBT’s with ft/fmax = 470/650 GHz. The process offers a 8-layer Cu-BEOL from X-FAB containing 4 thin Cu layers, 2 thick 3μm Cu layers, a thin Al layer with 2 fF/μm MIM capacitor and a 2.8 μm Aluminum top layer. This technology offers CMOS devices with 130 nm gate length and 1.2 V core voltage and high voltage CMOS devices with 3.3 V core voltage. |
| SG25H5_EPIC | A monolithic photonic BiCMOS technology combining 0.25 µm CMOS, high-performance npn HBTs (fT / fmax = 220/290 GHz), and full photonic device set for C/O-band. |
| SGB25RH | Is a special variant of SGB25V which includes radiation hard IP for space applications. It is not allowed to use Process Design Kit IP together with SGB25V technology. |
The backend offers 3 (SG13: 5) thin and 2 thick metal layers (TM1: 2 μm, TM2: 3 μm).
A cadence-based mixed signal design kit is available. For high frequency designs an analogue Design Kit in ADS can be used. IHP's reusable blocks and IPs for wireless and broadband are offered to support your designs.
The following Modules are available
| LBE | The Localized Backside Etching module is offered to remove silicon locally to improve passive properties (available in all technologies). |
|---|---|
| PIC | Includes additional photonic design layers along with BiCMOS BEOL layers on SOI wafers. |
| TSV | An additional option in SG13S and SG13G2 technology that provides RF grounding by vias through silicon to improve RF performance. |
| MEMRES | A fully CMOS integrated memristive module based on resistive TiN / HfO2-x / TiN switching devices in SG13S technology, along with a Process Design Kit including layout and VerilogA simulation model. |
2.1 MPW Price Information 2024
Non-Commercial Access
For European non-profit and educational institutions, special discounts are offered for research projects via EUROPRACTICE.
2.1.1 Prices for Technologies
| Process | Area Price / mm2 |
|---|---|
| SGB25RH | € 3050 |
| SG25H5_EPIC | € 8000 |
| SG13S | € 6300 |
| SG13C | € 4500 |
| SG13G2 | € 7300 |
| SG13G3 | € 9000 |
| SG13SCu | € 6300 |
| SG13G2Cu | € 7300 |
| SG13G3Cu | € 9000 |
2.1.2 Prices for Modules
| Module (Process) | Price |
|---|---|
| LBE (all Al BEOL) | € 5000 per order and technology |
| BEOL (only) 0.13 µm (SG13) | € 1000 (per mm2) |
| SG25_PIC | € 3800 (per mm2) |
| TSV (S, G2) | € 12500 per order |
| MEMRES (S) | € 2500 per Run + € 600 per mm2 |
| TSV_RDL (S, G2) | € 27000 per Run |
2.2 MPW Schedule 2025
There is a minimum area requirement of only 0.8 mm2 for all runs with bold shipment times. For all technologies or modules marked in brackets, minimum area order is required. For details see chapter 2.4. TAPE IN time is given in a column “TAPE IN”, shipment time in corresponding table cells.
Schedule for complete technologies
| TAPE IN | SG25 | SG13 | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| CMOS | EPIC | S (C) | MEMRES | SCu | G2Cu | G2 | G3 | G3Cu | ||
| Nov 4, 24 | Oct 13 | |||||||||
| Dec 9, 24 | Jun 21* | Jun 30 | Jun 23* | Jun 12 | Jun 30** | Jul 16 | Jul 16 | |||
| Mar 17, 25 | Sep 10* | Aug 15 | Oct 5 | |||||||
| Apr 21, 25 | Nov 28*** | |||||||||
| May 26, 25 | Nov 18* | Nov 8 | Nov 7 | |||||||
| Sep 8, 25 | Feb 19 | Mar 10 | Apr 1* | Mar 29 | Mar 29 | |||||
| Sep 14, 25 | Feb 4*** | |||||||||
| Nov 3, 25 | Oct 7 | |||||||||
| Dec 8, 25 | Jun 20* | Jul 8 | Jul 6* | Jun 27 | Jun 6 | Jul 15 | Jul 15 | |||
* Runs with lower priority
** TAPE IN for digital blocks using IHP´s radhard library is 1 month before standard TAPE IN
*** Open Source Designs only
Local Backside Etching (LBE) is not offered for runs with Cu-BEOL from X-FAB. For all the other runs LBE is available and shipment will be 21 days later than the standard shipment. TSV and RDL modules is available for SG13S and SG13G2 technologies and for runs with low priority, it leads to a 35 days longer cycle time for TSV module: TSV_RDL is available only fpr TAPE IN in May and December with 42 days longer cycle time.
2.2.1 BEOL (only)/Interposer runs
| TAPE IN | SG13 | SG13_interposer | TSV |
|---|---|---|---|
| Feb 25, 25 | May 15 | Jul 9 | |
| Aug 11, 25 | Nov 28 |
There might be internal BEOL or SG25_PIC runs, without confirmed schedule. Feel free to ask our customer support for more details if you are interested in joining such runs.
2.3 Information on Minimum Area per MPW Run
There is a minimum area requirement of only 0.8 mm² for selected technologies or module in schedule tables in chapter 2.2 and 2.3. This is valid for all technologies or modules marked with bold shipment times. For all technologies or modules marked with grey italic shipment times in brackets, minimum area order as given in the following table is required. A registration 4 weeks before TAPE out, followed by the confirmation from the foundry, is necessary in this case. By default these additional runs are without priority. A combination of 0.25 μm based runs and 0.13 μm based runs is not possible.
| Process | Min Area [mm²] | Min Area1 for Discount |
|---|---|---|
| SG25H5_EPIC | 10 | - |
| SGB25RH | 25 | - |
| SG13S | 10 | 10 |
| SG13C | - | - |
| SG13G2 | 10 | 10 |
| SG13G3 | 10 | - |
| SG13SCu | 10 | 10 |
| SG13G2Cu | 10 | 10 |
| SG13G3Cu | 10 | 10 |
| SG25_PIC | 12 | 12 |
1 Ask for special price if you need more than this area for one MPW run.
Delivery
As default 40 diced samples will be delivered. Exceptions are designs using TSV module and SG25_PIC. Here 25 samples will be delivered by default. The delivery includes E-test data and RF measurements.
Back lapping options:
- 200 µm (no additional fee)
- 300 µm (no additional fee)
- 250 µm (additional fee)
- 150 µm (additional fee)
- 100 µm (additional fee)
- 75 µm (for TSV module only)
Hot lots and additional dies are available upon request.
Research Engineering Runs
IHP is offering complete mask sets only for research purpose and prototyping. If customer specific modules are added to a qualified technology, this technology is considered as non-qualified with status “early access”. Prices for Research Engineering Runs can be given upon request.
IHP's General Terms and Conditions »
For further information please contact:
Dr. René Scholz
IHP GmbH
Im Technologiepark 25
15236 Frankfurt (Oder)
Germany
Phone: +49 335 5625 647
Fax: +49 335 5625 327
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