Publikationen 2024

Script list Publications

(1) A 220—320 GHz High Image Rejection Sideband Separating Receiver for Space-Borne Observatories
E.M. Al Seragi, Y.L. Rajendra, W. Ahmad, M. Kaynak, P.F. Goldsmith, S. Zeinoladedinzadeh
IEEE Transactions on Terahertz Science and Technology 14(2), 162 (2024)
DOI: 10.1109/TTHZ.2024.3349483
This work presents a novel terahertz THz sideband separating receiver (SSR) implemented in silicon germanium (SiGe) 0.13 μm BiCMOS technology that covers a broad frequency range of 220-320 GHz. The proposed architecture provides simultaneous observation of spectral lines with high image rejection ratio (IRR) across the entire operating frequency range. The double down conversion architecture with a first mixer operating as a sub-harmonic mixer was configurated as a sideband separating receiver leveraging the Weaver topology to provide two differential channels, one for the upper sideband (USB) and one for the lower sideband (LSB). The presented design demonstrates an IRR exceeding 20 dB across the entire frequency range of 220-320 GHz, without the need for calibration. To the best of the author's knowledge, this is the first reported H-band simultaneous sideband separation receiver in silicon technology. The fabricated receiver measures 1.2×1 mm2 and consumes 19 mW (not including LO power consumption), showcasing its potential for application in multiple-pixel arrays for space-borne observations.

(2) A Highly Efficient 240-GHz Power Amplifier in 0.13-μm SiGe
K. Balaban, M. Kaynak, A.C. Ulusoy
IEEE Microwave and Wireless Technology Letters (MWTL) 34(1), 88 (2024)
DOI: 10.1109/LMWT.2023.3328934
This letter presents the design and experimental characterization of a highly efficient WR3.4-band power amplifier (PA) using 0.13-μm SiGe technology. The realized differential cascode PA demonstrates a high efficiency, owing to the gm-boosting technique which enables a relatively higher small-signal gain per stage. The proposed PA exhibits a saturated output power of 10.48 dBm with a maximum power-added-efficiency (PAE) of 5.46% at 240 GHz , which is a leading-edge performance among the reported silicon (Si)-based WR3.4-band PAs. The small-signal gain peaks at 24.1 dB and the PA has a 3-dB bandwidth of 21 GHz.

(3) Design of 240 GHz Dielectric Resonator Antenna in 130 nm SiGe BiCMOS Process
M.F. Bashir, M. Wietstruck
15th German Microwave Conference (GeMIC 2024), 73 (2024)
DOI: 10.23919/GeMiC59120.2024.10485246

(4) The Chip-Level in-Plane Stress Distribution over BiCMOS Wafers
Z. Cao, T. Voss, M. Wietstruck, C. Carta, M. Kaynak
Proc. 24th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2024), 45 (2024)
DOI: 10.1109/SiRF59913.2024.10438504, (FLEXCOM)

(5) A 300 GHz x9 Multiplier Chain with 9.6 dBm Output Power in 0.13-μm SiGe Technology
A. Chandra-Prabhu, J. Grzyb, P. Hillger, T. Bücher, H. Rücker, U. Pfeiffer
Proc. 24th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2024), 37 (2024)
DOI: 10.1109/SiRF59913.2024.10438581, (DFG-Dotseven2IC)

(6) A 240-GHz VMPS with 1.2° and 0.35 dB RMS Errors in 130 nm BiCMOS:C Technology
M.H. Eissa, Ch. Wipf, A. Malignaggi, G. Kahmen
IEEE Microwave and Wireless Technology Letters (MWTL) 34(3), 295 (2024)
DOI: 10.1109/LMWT.2024.3357203
This work presents a low phase error (PE) and amplitude error (AE) vector modulator phase shifter (VMPS) in the J -band. The influence of the IQ crosstalk RF impairment on the performance is analyzed for different vector summation implementations, guiding to the VMPS architecture choice and design optimization. The chosen architecture consists of an IQ analog-controlled voltage-gain amplifier (IQ-VGA), Branchline coupler, and a Wilkinson combiner. Test structures for the variable-gain amplifier (VGA) and the VMPS are manufactured and measured in a 130-nm BiCMOS technology ( f T / f max = 300/500 GHz). For the phase resolution of 11.25°, the VMPS achieves an average rms PE and AE of 1.2° and 0.35 dB, respectively, with equivalent to 5.5 -bits control voltage across the frequency band 220–260 GHz. The VMPS consumes 60 mW from 2.5-V supply and occupies 0.2 mm 2 of silicon area. This work presents the least PE and AE across a wide bandwidth for VMPS in silicon technologies above 200 GHz, which is crucial for large-scale beam-steering arrays.

(7) Epitaxial Growth of Nd2O3 Layers on Virtual SiGe Substrates on Si(111)
H. Genath, M.A. Schubert, H. Yamtomo, J. Krügener, H.J. Osten
Journal of Applied Physics 135(11), 115302 (2024)
DOI: 10.1063/5.0191350
This study explores the growth and structural characteristics of Nd2O3 layers on virtual germanium-rich SiGe substrates on Si(111). We focus on the emergence of the hexagonal phase depending on the stoichiometry of the virtual substrate. X-ray diffraction measurements reveal a hexagonal phase when Nd2O3 is grown directly on Si(111), while growth on Ge leads to a cubic oxide structure. On SiGe layers, the growth of the oxide results in a mixed phase containing hexagonal and cubic regions, regardless of the Ge content. The cubic structure grown on virtual Ge substrates exhibits strong tensile strain, while layers grown on SiGe layers show no strain. In situ growth control via electron diffraction shows a dependence of the oxide structure of the surface reconstruction of the virtual substrate. Growth on a 7×7 reconstruction leads to hexagonal parts on Si-based substrates, while growth on c(2×8) results in cubic oxide growth on Ge. Furthermore, oxide layers grown on virtual SiGe substrates form an interfacial silicate layer. The thickness of the interfacial layer is influenced by the Si content and the structure of the oxide layer enabling oxygen diffusion pathways.

(8) Strain and Optical Characteristics Analyses of 3-Dimentional Self-Ordered Multilayered SiGe Nanodots by Photoluminescence and Raman Spectroscopy
Y. Ito, R. Yokogawa, W.-C. Wen, Y. Yamamoto, T. Minowa, A. Ogura
Japanese Journal of Applied Physics 63(3), 035SP61 (2024)
DOI: 10.35848/1347-4065/ad231e
The strain state, optical properties, and band structure of the self-ordered multilayered silicon-germanium (SiGe) nanodots, which are staggered and dot-on-dot alignment and embedded by Si spacer, were evaluated by Raman spectroscopy and low-temperature Photoluminescence (PL). These results suggest that the compressive strain applied to the staggered nanodots is smaller than that of the dot-on-dot nanodots, which contributes to the shrinking of the bandgap of the staggered nanodots. Strong PL intensity was observed from the nanodots compared to the single crystalline bulk SiGe due to the carrier confinement and high crystal quality of the nanodots. The stack-controlled nanodots showed a redshift of the PL peaks compared to the bulk SiGe and the effect of strain induced in SiGe nanodots might not be enough to explain this phenomenon. The cause of the redshift was clarified by considering the hetero band structure of the nanodots and the tensile strained spacer.

(9) A 4-λ × 28-Gb/s/λ Silicon Ring-Resonator-based WDM Receiver with a Reconfigurable Temperature Controller
H.-K. Kim, J.-H. Lee, M. Kim, Y. Jo, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
IEEE Journal of Lightwave Technology 42(7), 2296 (2024)
DOI: 10.1109/JLT.2023.3337820
We present a 4-λ × 28-Gb/s/λ silicon ring-resonator-based hybrid-integrated WDM receiver along with the reconfigurable temperature controller. Each of four ring resonators is thermally controlled so that only the target wavelength can be delivered to an integrated photodetector and processed with a hybrid-integrated CMOS TIA. The controller automatically determines the heater voltage required for each ring resonator to receive any target wavelength and maintains this condition against any external temperature fluctuations. It is experimentally verified that the controller performs its task during the initial calibration process and against the thermal stress. In addition, using the controller, WDM channel reconfiguration is successfully demonstrated.

(10) Electron Emission from Alignment-Controlled Multiple Stacks of SiGe Nanodots Embedded in Si Structures
K. Makihara, Y. Yamamoto, H. Yagi, L. Li, N. Taoka, B. Tillack, S. Miyazaki
Materials Science in Semiconductor Processing 174, 108227 (2024)
DOI: 10.1016/j.mssp.2024.108227
We fabricated a vertically aligned and staggered structure comprising 20–stacking layers of SiGe–nanodots (NDs) embedded in Si via reduced–pressure chemical vapor deposition and investigated their electron emission properties. The SiGe–NDs with a 35% Ge content were deposited using SiH4–GeH4, while Si spacers were deposited using SiH4 or SiH2Cl2 to control a 3D–alignment of staggered or dot–on–dot structure, respectively. Top Au electrodes with 5–nm–thick SiO2 and bottom Al contact were fabricated for electron emission measurements. After applying a bias of −3.8 V to the bottom Al–electrode with respect to the grounded top Au–electrode, electron emission was observed from the staggered SiGe–ND stack, which was slightly lower than that of the vertically–aligned NDs. In addition, we also observed a reduction in sample current with the formation of the staggered SiGe–ND stack. These results indicate that aligning SiGe–NDs in a staggered configuration suppresses leakage current and improves electron emission efficiency.

(11) Radiation Tolerance of SiGe BiCMOS Monolithic Silicon Pixel Detectors without Internal Gain Layer
M. Milanesio, L. Paolozzi, T. Moretti, R. Cardella, T. Kugathasan, F. Martinelli, A. Picardi, I. Semendyaev, S. Zambito, K. Nakamura, Y. Tabuko, M. Togawa, M. Elviretti, H. Rücker, F. Cadoux, R. Cardarelli, S. Débieux, Y. Favre, C.A. Fenoglio, D. Ferrere, S. Gonzalez-Sevilla, L. Iodice, R. Kotitsa, C. Magliocca, M. Nessi, A. Pizarro-Medina, J. Sabater Iglesias, J. Saidi, M. Vicente Barreto Pinto, G. Iacobucci
Journal of Instrumentation 19, P01014 (2024)
DOI: 10.1088/1748-0221/19/01/P01014
A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 × 1016 1 MeV neq/cm2. The ASIC contains a matrix of hexagonal pixels with 100 𝜇m pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 𝜇m thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. Laboratory tests conducted with a 90Sr source show that the detector works satisfactorily after irradiation. The signal-to-noise ratio is not seen to change up to fluence of 6×1014 neq/cm2. The signal time jitter was estimated as the ratio between the voltage noise and the signal slope at threshold. At -35◦C, sensor bias voltage of 200 V and frontend power consumption of 0.9 W/cm2, the time jitter of the most-probable signal amplitude was estimated to be 𝜎𝑡90Sr = 21 ps for proton fluence up to 6 × 1014 neq/cm2 and 57 ps at 1 × 1016 neq/cm2 . Increasing the sensor bias to 250 V and the analog voltage of the preamplifier from 1.8 to 2.0 V provides a time jitter of 40 ps at 1 × 1016 neq/cm2 .

(12) Blooming and Pruning: Learning from Mistakes with Memristive Synapses
K. Nikiruy, E. Perez, A. Baroni, K.D.S. Reddy, S. Pechmann, Ch. Wenger, M. Ziegler
Scientific Reports 14, 7802 (2024)
DOI: 10.1038/s41598-024-57660-4, (KI-IoT)
Blooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.

(13) Strong Optical Coupling of Lattice Resonances in a Top-Down Fabricated Hybrid Metal−Dielectric Al/Si/Ge Metasurface
P. Oleynik, F. Berkmann, S. Reiter, J. Schlipf, M. Ratzke, Y. Yamamoto, I.A.Fischer
Nano Letters 24(10), 3142 (2024)
DOI: 10.1021/acs.nanolett.3c05050
Optical metasurfaces enable the manipulation of the light–matter interaction in ultrathin layers. Compared with their metal or dielectric counterparts, hybrid metasurfaces resulting from the combination of dielectric and metallic nanostructures can offer increased possibilities for interactions between modes present in the system. Here, we investigate the interaction between lattice resonances in a hybrid metal–dielectric metasurface obtained from a single-step nanofabrication process. Finite-difference time domain simulations show the avoided crossing of the modes appearing in the wavelength-dependent absorptance inside the Ge upon variations in a selected geometry parameter as evidence for strong optical coupling. We find good agreement between the measured and simulated absorptance and reflectance spectra. Our metasurface design can be easily incorporated into a top-down optoelectronic device fabrication process with possible applications ranging from on-chip spectroscopy to sensing.

(14) Employing Optical Beam-Induced Current Measurement in Side-Channel Analysis
D. Petryk, I. Kabin, J. Bělohoubek, P. Fišer, J. Schmidt, M. Krstic, Z. Dyka
Proc. 36. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2024), 15 (2024)
(Total Resilience)

(15) Design and Phase Noise Measurements of an Ultrafast Dual-Modulus Prescaler in 130 nm SiGe:C BiCMOS
L. Polzin, M. van Delden, N. Pohl, H. Rücker, T. Musch
IEEE Transactions on Microwave Theory and Techniques 72(1), 525 (2024)
DOI: 10.1109/TMTT.2023.3329699
The design complexity of high-speed and power-efficient circuits increases to higher operation frequencies. Therefore, this manuscript gives an overview of how to design and optimize fully differential emitter-coupled logic (ECL) gates using two dual-modulus prescalers with switchable division ratios of 4 and 5. The first prescaler is optimized to the highest operation frequencies, up to 142 GHz and even 166 GHz for the division ratios of 5 and 4, respectively. Furthermore, another prescaler has been optimized for the widely used 80 GHz band, which has been heavily promoted by the automotive industry and has a high number of components in that domain. Both prescalers can be utilized in a fully programmable frequency divider with a wide division ratio range. As the measurement of the additive phase noise for frequency-converting devices with excellent noise performance is quite challenging, this is discussed theoretically and carried out practically. The measured jitter is between 500 as and 1.9 fs within integration limits of 100 Hz up to 1 MHz offset frequency.

(16) Selective Epitaxy of Germanium on Silicon for the Fabrication of CMOS Compatible Short-Wavelength Infrared Photodetectors
D. Ryzhak, A.A. Corley-Wiciak, P. Steglich, Y. Yamamoto, J. Frigerio, R. Giani, A. De Iacovo, D. Spirito, G. Capellini
Materials Science in Semiconductor Processing 176, 108308 (2024)
DOI: 10.1016/j.mssp.2024.108308, (VISIR2)
Here we present the selective epitaxial growth of Ge on Si using reduced pressure chemical vapor deposition on SiO2/Si solid masks realized on 200 mm Si wafers, aiming at manufacturing integrated visible/short-wavelength infrared photodetectors. By a suitable choice of the reactants and of the process conditions, we demonstrated highly selective and pattern-independent growth of Ge microstructure featuring high crystalline quality. The Ge “patches” show a distinct faceting, with a flat top (001) facet and low energy facets such as e.g. {113} and {103} at their sidewalls, independently on their size. Interdiffusion of Si in to the Ge microcrystals is limited to an extension of ∼20 nm from the heterointerface. The Ge patches resulted to be plastically relaxed with threading dislocation density values better or on par than those observed in continuous two-dimensional Ge/Si epilayer in the low 107 cm−2 range. A residual tensile strain was observed for patches with size >10 μm, due to elastic thermal strain accumulation, as confirmed by μ-Raman spectroscopy and μ-photoluminescence characterization. Polarization-dependent Raman mapping highlights the strain distribution associated to the tridimensional shape. On this material, Ge photodiodes were fabricated and characterized, showing promising optoelectronic performances.

(17) Design, Fabrication, and Characterization of Integrated Optical Through-Silicon Waveguides for 3D Photonic Interconnections
F. Villasmunta, P. Steglich, C. Villringer, S. Schrader, H. Schenk, A. Mai, M. Regehly
Proc. 24th SPIE Optical Interconnects (OPTO 2024), 12892, 128920I (2024)
DOI: 10.1117/12.3003146

(18) Characterization, Analysis, and Modeling of Long-Term RF Reliability and Degradation of SiGe HBTs for High Power Density Applications
C. Weimer, G.G. Fischer, M. Schröter
IEEE Transactions on Device and Materials Reliability 24(1), 20 (2024)
DOI: 10.1109/TDMR.2023.3343503, (SIGEREL)
This paper aims at determining RF operating limits of SiGe HBTs. Long-term stress tests consisting of RF large-signal stress and periodic measurements of small-signal parameters are performed. Reliable dynamic large-signal transistor operation is demonstrated beyond conventional static safe operating limits. In addition, RF operating limits are identified and degradation of SiGe HBTs accelerated by extreme RF stress is systematically characterized, analyzed and modeled. RF-stress-caused degradation is shown to significantly affect the collector current and demonstrated to be different from electrothermal breakdown caused by DC stress. A modeling approach for estimating SiGe HBT degradation under RF large-signal operating conditions is proposed and shown to agree very well with experimental data.

(19) Thin and Locally Dislocation-Free SiGe Virtual Substrate Fabrication by Lateral Selective Growth
Y. Yamamoto, W.-C. Wen, M.A. Schubert, A.A. Corley-Wiciak, S. Sugawa, Y. Ito, R. Yokogawa, H. Han, R. Loo, A. Ogura, B. Tillack
Japanese Journal of Applied Physics 63(2), 02SP53 (2024)
DOI: 10.35848/1347-4065/ad189d
Locally dislocation-free SiGe-on-insulator (SGOI) is fabricated by chemical vapor deposition. Lateral selective SiGe growth of ~30%, ~45% and ~55% is performed around ~1 µm square Si(001) pillar located under the center of a 6.3 µm square SiO2 on Si-on-insulator substrate which is formed by H2-HCl vapor phase etching. The selective SiGe is deposited by H2-SiH2Cl2-GeH4-HCl. In the deposited SiGe layer, tensile strain is observed by top-view. The degree of strain is slightly increased at the corner of the SiGe. The tensile strain is caused by the partial compressive strain of SiGe in lateral direction and thermal expansion difference between Si and SiGe. Slightly higher Ge incorporation is observed in higher tensile strain region. At the peaks formed between the facets of growth front, Ge incorporation is reduced. These phenomena are pronounced for SiGe with higher Ge contents. Dislocation-free SGOI is formed along <010> from the Si pillar by lateral aspect-ratio-trapping.

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