Tutorial on IHP's 130 nm BiCMOS PDK including Cu backend and next generation technology using Cadence and ADS

Date:
June 23-25 2026
Starts on the 23rd at 13:00
Ends on the 25th at 12:00

Location:
IHP - Leibniz Institute for High Performance Microelectronics
Im Technologiepark 25
15236 Frankfurt (Oder) 

Tutorial Fee:
300 € for academic participants / 500 € for participants from industry

Please note: A duly signed NDA agreement with IHP and XFAB is required in order to take part in the PDK training. After registration, you will be contacted for further steps regarding the NDAs.

• Introduction
• Installation of our SG13G3Cu BiCMOS IHP PDK for Cadence
• The Guide to our Design Kit Elements and Features: A Step-by-Step Tutorial on How to Use Basic Features of our PDK
• Towards next generation IHP SG13G3Cu Technology: Post-layout EM/Circuit co-simulation on a 245 GHz Linear Amplifier
• Digital Design Kit Demonstration Tutorial: Serial Peripheral Interface (SPI) Test Chip Implementation
• Setup of ADS PDK and RFIC Virtuoso Interoperability
• Simulation using Analog-Mixed-Signal Simulator
• Post-layout EM/Circuit co-simulation on a 50 GHz BW Differential PA using RFPro in Virtuoso environment
• MPW Organization and Tape-Out Procedure
• Design Kit Documentation and IHP DK-Support