Script list Publications
(1) Solar Irradiation Prediction for Energy-Efficient Urban Planning using Machine Learning
S. Aleksic, P. Obla, S.P. Raja, Z. Stamenkovic
Proc. 10th International Conference on Radiation Applications (RAP 2025), abstr. book 158 (2025)
(2) Large Fractional Bandwidth D-Band Power Amplifier for 6G Communications in 130-nm SiGe BiCMOS Technology
M.K. Ali, T. Herbel, G. Panic, D. Kissinger
Proc. 16th German Microwave Conference (GeMiC 2025), 615 (2025)
DOI: 10.23919/GeMiC64734.2025.10979019, (6GKom)
(3) Optical Transport Network Optimization Supporting Integrated Sensing and Communication Services
M. Anastasopoulos, J. Gutiérrez Teran, A. Tzanakaki
Proc. 50th Optical Fiber Communications Conference and Exposition (OFC 2025), W2A.48 (2025)
(6G-SENSES)
(4) Demonstration of a Multi-Technology 6G Transport Network Integrating THz and Optical Network Technologies Empowered by Federated Learning
M. Anastasopoulos, A. Tzanakaki, Y. Jian, L. Lopacinski, J. Gutiérrez Teran, I. Mesogiti, E. Theodoropoulou, G. Lyberopoulos
Journal of Optical Communications and Networking 17(8),C156 (2025)
DOI: 10.1364/JOCN.551626, (6G-SENSES)
This paper proposes a 6G architecture that adopts a multi-technology transport network integrating THz links and optical network technologies to interconnect the 6G radio access network and core domains. The proposed solution operates in a self-organized manner, taking advantage of the software defined networking (SDN) control of the optical network, while suitable SDN control is purposely developed for the THz solution. An end-to-end (E2E) Service Management and Orchestration (SMO) layer is adopted, offering intelligence capabilities in service provisioning and resource allocation across the 6G infrastructure through the adoption of a federated learning (FL) scheme. The proposed architecture and the developed control scheme are validated through an experimental demonstration. To the best of the authors’ knowledge, this is the first experimental demonstration of an autonomously controlled 6G network implementation integrating optical network technologies and THz links in a common transport network. The developed intelligent management framework empowered by FL to jointly optimize THz and multi-vendor optical network equipment supporting 6G services is also experimentally showcased.
(5) Comparison of Gate-Level Techniques for Mitigation of Single Event Transients in Combinational Logic
M. Andjelkovic, M. Krstic
Proc. 16th IEEE CASS Latin American Symposium on Circuts and Systems (LASCAS 2025), (2025)
(Open 6G Hub)
(6) Comparison of Gate-Level Techniques for Mitigation of Single Event Transients in Combinational Logic
M. Andjelkovic, M. Krstic
Proc. 16th IEEE CASS Latin American Symposium on Circuts and Systems (LASCAS 2025), (2025)
(6G-TakeOff)
(7) Analysis and Modeling of Single Event Transient Generation in Standard Combinational Cells
M. Andjelkovic, M. Krstic
Journal of Electronic Testing 41, 287 (2025)
DOI: 10.1007/s10836-025-06175-5, (6G-TakeOff)
Singe Event Transients (SETs) are one of the most common causes of data corruption and malfunction in digitial integrated circuits (ICs) employed in applications involving exposure to high-energy particles, such as space missions. Therefore, the ICs intended to operate in ionizing radiation environments should be designed with special measures to ensure sufficient tolerance to SETs. To achieve this, the SET generation and propagation effects should be well understood and properly assessed for a given design. In this paper, we investigate the SET generation in standard digital combinational cells. Using SPICE simulations, we have analyzed the dependence of generated SET pulse width on various design and operating parameters. The characterization was done for standard cells designed in IHP’s 130 nm process, using a bias-dependent current source to inject SETs. Employing analytical fitting to the simulation results, a model for the width of generated SET pulse in terms of particle’s Linear Energy Transfer (LET), drive strength of target gate, drive strength of load gate, supply voltage and temperature was formulated. The proposed model is defined as the sum of multiple components, enabling to identify the contribution of individual parameters. It was shown that the average relative error of the proposed model with respect to the results from SPICE simulations is below 10 % for LET greater than 2 MeVcm2mg-1, confirming the model's very good accuracy. The model could be used as a basis of an automated tool-flow for the analysis of SET effects in complex digital designs.
(8) Prediction of Single Event Transient Propagation Using Machine Learning Models
M. Andjelkovic, J.-C. Chen, J. Aleksic, V. Padmakumar, M. Marjanovic, N, Zazatis, T.R. Lenka, D. Dankovic, C. Sotiriou, F. Vargas
Proc. 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD 2025), (2025)
DOI: 10.1109/SMACD65553.2025.11092057, (TWIN-RELECT)
(9) Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT)
M. Andjelkovic, F. Vargas, M. Krstic, L. Dilillo, A. Michez, F. Wrobel, D. Bertozzi, M. Lujan, C. Georgakidis, N. Chatzivangelis, K. Tsilingiri, N. Zatatis, G.-I. Pagliaroutis, P. Tsoumanis, C. Sotiriou
Proc. 28th Design, Automation and Test in Europe Conference (DATE 2025), (2025)
DOI: 10.23919/DATE64628.2025.10992721, (TWIN-RELECT)
(10) Heterogeneous Integration of Advanced CMOS and Emerging Devices: Challenges and Solutions
L.M. Bolzani Poehls, A.L. Chinazzo, M. Benkhelifa, A. Kar, H. Amrouch, M. Krstic
Proc. 30th IEEE European Test Symposium (ETS 2025), (2025)
DOI: 10.1109/ETS63895.2025.11049636, (INSEKT)
(11) Heterogeneous Integration of Advanced CMOS and Emerging Devices: Challenges and Solutions
L.M. Bolzani Poehls, A.L. Chinazzo, M. Benkhelifa, A. Kar, H. Amrouch, M. Krstic
Proc. 30th IEEE European Test Symposium (ETS 2025), (2025)
DOI: 10.1109/ETS63895.2025.11049636, (TAICHIP)
(12) Towards Adaptive RISC-V based Systems for Non-Terrestrial Sub-THz Communication
H. Borchert, M. Ulbricht, M. Andjelkovic, D. Göhringer, M. Krstic
Proc. International Conference on Mobile and Miniaturized Terahertz Systems (ICMMTS 2025), (2025)
DOI: 10.1109/ICMMTS62835.2025.10926015, (Scale4Edge)
(13) Towards Adaptive RISC-V based Systems for Non-Terrestrial Sub-THz Communication
H. Borchert, M. Ulbricht, M. Andjelkovic, D. Göhringer, M. Krstic
Proc. International Conference on Mobile and Miniaturized Terahertz Systems (ICMMTS 2025), (2025)
DOI: 10.1109/ICMMTS62835.2025.10926015, (6G-TakeOff)
(14) Towards Adaptive RISC-V based Systems for Non-Terrestrial Sub-THz Communication
H. Borchert, M. Ulbricht, M. Andjelkovic, D. Göhringer, M. Krstic
Proc. International Conference on Mobile and Miniaturized Terahertz Systems (ICMMTS 2025), (2025)
DOI: 10.1109/ICMMTS62835.2025.10926015, (COREnext)
(15) Ultra-Low-Latency Data Link Layer TX Buffer Architecture for Wireless Communications
H. Borchert, K. KrishneGowda, M. Krstic
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2025), (2025)
DOI: 10.1109/ISVLSI65124.2025.11130195, (6G-RIC)
(16) Ultra-Low-Latency Data Link Layer TX Buffer Architecture for Wireless Communications
H. Borchert, K. KrishneGowda, M. Krstic
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2025), (2025)
DOI: 10.1109/ISVLSI65124.2025.11130195, (Open 6G Hub)
(17) D-Band Demonstration of Quasi-Optical and Analog Beam Reconfiguration using Phased Array and Lens for 6G Applications
M.A. Campo, S. Bruni, A. Lauer, M. Wleklinski, U. Gollor, W. Wischmann, A. Friedrich, C. Oikonomopoulos, O. Litschke, C. Herold, A. Malignaggi, N. Moroni, K.Krishnegowda, C. Carta, W. Keusgen
IEEE Transactions on Antennas and Propagation 73(8), 5064 (2025)
DOI: 10.1109/TAP.2025.3557716
In this paper, a hybrid quasi-optic and analogue beamforming approach is presented, involving an elliptical lens with an active focal plane array at D-band (110-170 GHz). Beamwidth reconfigurability and steering in two planes with enhanced performance are demonstrated. The quasi-optic technique minimizes the beam squint over frequency. Analogue phase shift in the focal plane array is used to increase the lens steering range. A prototype including two 4-channel D-band transceivers with on-chip antennas has been built as demonstrator. The resulting active focal plane array consists of 2x4 antenna elements, which are tuned in amplitude and phase to reconfigure the beam. The advantages of using a resonant leaky-wave cavity combined with a coherent array of feeds are discussed and quantified. Radiation pattern measurements performed with the calibrated active antenna validate the beam reconfiguration concept in two planes at 140 GHz. A steering loss reduction ranging from 2 to 4.5 dB is achieved in the whole D-band at 22° scan angle by applying beam steering in the feed radiation.
(18) Next-Gen TETRISC SoC - A Quad-Heterogeneous Design for Adaptive Fault Tolerance
J.-C. Chen, L. Lu, M. Ulbricht, M. Krstic
Proc. RISC-V Summit Europe (RISC-V 2024)
(Scale4Edge)
(19) Next-Gen TETRISC SoC - A Quad-Heterogeneous Design for Adaptive Fault Tolerance
J.-C. Chen, L. Lu, M. Ulbricht, M. Krstic
Proc. RISC-V Summit Europe (RISC-V 2024)
(Open 6G Hub)
(20) Dynamic Fault Mitigation for Space Radiation using Fault Injection and Machine Learning
J.-C. Chen, L. Lu, M. Andjelkovic, F. Vargas, M. Krstic
Journal of Electronic Testing 41, 273 (2025)
DOI: 10.1007/s10836-025-06183-5, (Open 6G Hub)
In aerospace applications, the demand for highly reliable systems necessitates advanced dynamic fault mitigation strategies to achieve the trade-off between system reliability, performance, and power efficiency in dynamic space radiation environments. However, traditional fault mitigation methods fall short in simulating space radiation dynamics, particularly during solar events, thus hindering the effective optimization of dynamic systems. This paper presents a novel methodology that integrates space radiation-driven fault injection with machine learning-enhanced dynamic Parity per Byte with Duplication (PBD) fault mitigation strategies. The methodology utilizes historical space radiation data, creating time-series fault datasets for precise simulation of dynamic space environments. These datasets are integrated into fault injection platforms and a fault prediction model training framework to assess the effectiveness of dynamic error correction strategies. The proposed approach was validated using several historical solar events on dynamic PBD-based RAM scrubbing. The results demonstrate the dynamic PBD method’s effectiveness in mitigating fault accumulation during SPEs, significantly enhancing RAM scrubbing performance by up to 13 times compared to five traditional static methods.
(21) N-Modular Redundancy Controller Generator for Adaptive Fault Tolerance Systems
J.-C. Chen, M. Ulbricht, M. Krstic
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Open 6G Hub)
(22) N-Modular Redundancy Controller Generator for Adaptive Fault Tolerance Systems
J.-C. Chen, M. Ulbricht, M. Krstic
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Scale4Edge)
(23) Dynamic Fault Mitigation for Space Radiation using Fault Injection and Machine Learning
J.-C. Chen, L. Lu, M. Andjelkovic, F. Vargas, M. Krstic
Journal of Electronic Testing 41, 273 (2025)
DOI: 10.1007/s10836-025-06183-5, (Scale4Edge)
In aerospace applications, the demand for highly reliable systems necessitates advanced dynamic fault mitigation strategies to achieve the trade-off between system reliability, performance, and power efficiency in dynamic space radiation environments. However, traditional fault mitigation methods fall short in simulating space radiation dynamics, particularly during solar events, thus hindering the effective optimization of dynamic systems. This paper presents a novel methodology that integrates space radiation-driven fault injection with machine learning-enhanced dynamic Parity per Byte with Duplication (PBD) fault mitigation strategies. The methodology utilizes historical space radiation data, creating time-series fault datasets for precise simulation of dynamic space environments. These datasets are integrated into fault injection platforms and a fault prediction model training framework to assess the effectiveness of dynamic error correction strategies. The proposed approach was validated using several historical solar events on dynamic PBD-based RAM scrubbing. The results demonstrate the dynamic PBD method’s effectiveness in mitigating fault accumulation during SPEs, significantly enhancing RAM scrubbing performance by up to 13 times compared to five traditional static methods.
(24) A Combined Strategy for Testing RRAMs after Manufacturing and during Lifetime
T. Copetti, S. Chakraborty, L.M. Bolzani Poehls
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963957
(25) RRAMs: A Lifecycle Management Strategy for Manufacturing and On-Line Testing
T.S. Copetti, L. Bolzani Poehls
Proc. 37. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(26) D-Band Line-of-Sight MIMO Link Demonstration
D. Cvetkovski, C. Herold, E. Grass
Proc. 24th IFIP International Conference on Networking (NETWORKING 2025)
(6G-RIC)
In this work, preliminary results from the prototyping phase of a 2x2 D-Band Line-of-Sight MIMO link are presented. Aiming to demonstrate ultra-high throughput for point-to-point fixed wireless links, line-of-sight MIMO is implemented and evaluated with the large modulation bandwidth that is available in the D-Band (110 - 170 GHz) of the millimeter-wave frequency range. The link demonstration is performed in a hardware-in-the-loop setup, at a 2 m range in an indoor conference hall environment. It is based on IHP’s D-Band 130-nm SiGe BiCMOS analog front-ends operating at a carrier frequency of 135 GHz, in combination with dielectric lenses. In order to obtain a near-orthogonal MIMO channel in line-of-sight conditions, the setup is relying on optimal arrangement between the transmit and receive antennas, according to the Rayleigh criterion. By performing spatial multiplexing of 2 QPSK-modulated data streams with 4 GHz modulation bandwidth, an aggregated throughput of 16 Gb/s is achieved during a live link demonstration. As the system is in its early development phase, it is subject to ongoing work to further enhance the link range and throughput.
(27) Case Study: NASCERR: In-Mission Self-Tuning Error Correction Approach for Space Applications
L. De Albuquerque, C. Luz Salles Cavalcante, D. Alencar, E. Mallet de Chauny Druesne, J.M. Matos Sobreira, M.A. Almeida Bezerra, A.A. da Silva, J.E. Silva Filho, J. Silveira, F.L. Vargas
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/GAST60528.2024.10520763
(28) Low-Loss GSG Bondwire Chip-to-Chip Interconnects from DC to 330 GHz
F.A. Dürrwald, F. Protze, D. Cvetkovski, T. Meister, R. Kraemer, F. Ellinger
Proc. 14th International Conference on Modern Circuits and Systems Technologies (MOCAST 2025), (2025)
DOI: 10.1109/MOCAST65744.2025.11083949, (DFG BAUDOT)
(29) A Fully Integrated Modular 2x4 220-260 GHz Beam-Forming Transmitter and Receiver with 50 Gbps Wireless Transmission in SiGe:C BiCMOS
M.H. Eissa, N. Maletic, M. Wietstruck, V. Sark, A. Malignaggi, W. Abdullah, C. Carta, G. Kahmen
IEEE Transactions on Terahertz Science and Technology 15(5), 805 (2025)
DOI: 10.1109/TTHZ.2025.3573157, (Open 6G Hub)
This article presents a 220-260 GHz fully integrated phased-array wireless system featuring direct conversion RF beam-forming. The system is constructed using fully integrated transmitter (Tx) and receiver (Rx) chips with on-chip antenna array. A 4-channel Tx and Rx are designed and fabricated in a 130nm SiGe BiCMOS process with fT / fmax = 300 / 500 GHz. A modular design approach enables the chips as building units for 2xN phased arrays and multiple-input multiple-output (MIMO) systems. A comprehensive design approach for the Tx and Rx chips focusing on key design decisions is presented in this work. The transmitter is equipped with a local oscillator (LO) multiplication chain, IQ up−conversion mixer, active RF splitting network, vector modulator phase shifter (VMPS), temperature sensors, and high output power amplifiers (PA). The PA with power−combining boost the effective isotropic radiated power (EIRP) and reduces the need for external lenses. The receiver is equipped with an LO chain, IQ down−conversion mixer, active RF combining network, VMPS, and low noise amplifiers (LNA). In both Tx and Rx the antenna array is composed of four differential double-folded dipole antennas with local backside etching (LBE). The Tx and Rx chips consume 4.4W and 1.84W of power respectively from a 3.5V supply while each occupying 25mm2 of silicon area. With a measured Tx array effective isotropic radiated power (EIRP) of 24 dBm, a beamforming wireless link is demonstrated supporting up to 50 Gbps of data rates across 85 cm of link distance with no need for focusing lenses and ±30º of scanning capability. With these capabilities, the presented modular chips enable future scaling for 2xN antenna arrays for sensing and communication applications.
(30) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (6G-RIC)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(31) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (iCampus II)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(32) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (HYB-RISC)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(33) Optimization of Beamforming and Transmit Power using DQN and Comparison with Traditional Techniques
P. Geranmayeh, E. Grass
IEEE Access 13, 94275 (2025)
DOI: 10.1109/ACCESS.2025.3573096, (IHP - Humboldt-Universität Joint-Lab)
As Artificial Intelligence (AI) and Machine Learning (ML) technologies continue to evolve, their integration into 5G and 6G networks has become critical for improving performance and efficiency. These technologies enhance wireless communication by leveraging deep neural networks and data-driven methods to optimize resource allocation, signal detection, and channel coding. They also address the growing need to reduce energy consumption in next-generation networks. Deep Q-Networks (DQN) play a key role in this transformation by enabling dynamic resource management, adaptive beamforming, and efficient network slicing. The use of DQN can improve spectrum utilization, power consumption, and beamforming in massive MIMO systems, supporting demands like eMBB and URLLC. In 6G, it is considered for optimizing resource allocation, dynamic beamforming, RIS control for Terahertz communication, and complex network slicing. This article focuses on maximizing channel capacity by deploying DQN to identify optimal beamforming angles and transmit power values for multiple transmitters and receivers. The model determines the best steering vectors and power levels to achieve maximum channel capacity while minimizing energy consumption and mutual interference. Its performance is compared to conventional optimization methods, demonstrating its effectiveness in enhancing the efficiency and reliability of 5G and 6G networks.
(34) Optimization of Beamforming and Transmit Power using DQN and Comparison with Traditional Techniques
P. Geranmayeh, E. Grass
IEEE Access 13, 94275 (2025)
DOI: 10.1109/ACCESS.2025.3573096, (5G-REMOTE)
As Artificial Intelligence (AI) and Machine Learning (ML) technologies continue to evolve, their integration into 5G and 6G networks has become critical for improving performance and efficiency. These technologies enhance wireless communication by leveraging deep neural networks and data-driven methods to optimize resource allocation, signal detection, and channel coding. They also address the growing need to reduce energy consumption in next-generation networks. Deep Q-Networks (DQN) play a key role in this transformation by enabling dynamic resource management, adaptive beamforming, and efficient network slicing. The use of DQN can improve spectrum utilization, power consumption, and beamforming in massive MIMO systems, supporting demands like eMBB and URLLC. In 6G, it is considered for optimizing resource allocation, dynamic beamforming, RIS control for Terahertz communication, and complex network slicing. This article focuses on maximizing channel capacity by deploying DQN to identify optimal beamforming angles and transmit power values for multiple transmitters and receivers. The model determines the best steering vectors and power levels to achieve maximum channel capacity while minimizing energy consumption and mutual interference. Its performance is compared to conventional optimization methods, demonstrating its effectiveness in enhancing the efficiency and reliability of 5G and 6G networks.
(35) A Fully-Integrated Four-Channel Phased Array D-Band Transceiver Achieving 10 GBit/s at 10 m
C. Herold, A. Karakuzulu, A. Malignaggi, M. Scheide, N. Maletic, K. Krishnegowda, C. Carta
Proc. 20th IEEE Radio & Wireless Week (RWW 2025), 30 (2025)
(6G-RIC)
(36) European Test Symposium Teams: an Anniversary Snapshot
M. Jenihhin, J. Raik, A. Jutman, N. Cherezova, R. Ubar, L. Miclea, S. Enyedi, I.Stefan, O. Stan, C. Corches, Z. Peng, P. Eles, R. DrechslerA, S. EggersglußB, G. FeyC, A. GlowatzB, D. TilleB, G. GielenA, A. CoyetteAB, W. DobbelaereB, R. VanhoorenB, P.-Y. Chuang, E.J. Marinissen, G. Di Natale, M. Barragan, P. Maistri, S. Mir, E.-I. Vatajelu, P. Bernardi, S. Di Carlo, P. Prinetto, M. Sonza Reorda, M. Violante, H.-G. Stratigopoulos, M.K. Michael, S. Neophytou, S. Hadjitheophanous, K. Christou, M. Skitsas, A. BosioA, B. DeveautourB, P. GirardC, M. TraiolaA, A. VirazelC, F. Fernandes dos SantosA, A. KritikakouAB, G. Casagranda, M. Vallero, F. Vella, P. Rech, L.M. Bolzani PoehlsA, M. KrsticAB, M. AndjelkovicA, F. VargasA, G. Tshagharyan, G. Harutyunyan, V. Vardanian, S. Shoukourian, Y. Zorian, J. DworakA, K. NepalB, T. ManikasA, M. Taouil, M. Fieback, A. Gebregiorgis, R. Bishnoi, S. Hamdioui, A. ChatterjeeA, A. SahaA, S. KomarrajuB, K. MaC, C. AmarnathD, M. Tahoori, M. Mayahinia, M. Rajabalipanah, K. Basharkhah, N. Nosrati, Z. Jahanpeima, Z. Navabi, H.-J. WunderlichA, S. HellebrandB
Proc. 30th IEEE European Test Symposium (ETS 2025), (2025)
(37) Packet Superposition HARQ Scheme Enabled by LDPC Coupled Codes
Y. Jian, L. Lopacinski, E. Grass
Proc. IEEE Wireless Communications and Networking Conference (WCNC 2025), (2025)
DOI: 10.1109/WCNC61545.2025.10978369, (PSSS-FEC)
(38) Performance Analysis of an Advanced HARQ Scheme Based on LDPC Coupled Codes
Y. Jian, L. Lopacinski, E. Grass
Proc. 101st IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(Open 6G Hub)
(39) Performance Analysis of an Advanced HARQ Scheme Based on LDPC Coupled Codes
Y. Jian, L. Lopacinski, E. Grass
Proc. 101st IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(PSSS-FEC)
(40) Packet Superposition HARQ Scheme Enabled by LDPC Coupled Codes
Y. Jian, L. Lopacinski, E. Grass
Proc. IEEE Wireless Communications and Networking Conference (WCNC 2025), (2025)
DOI: 10.1109/WCNC61545.2025.10978369, (6G-RIC)
(41) URLLC Networks Enabled by STAR-RIS, Rate Splitting, and Multiple Antennas
E. Jorswieck, M. Soleymani, I. Santamaria, J. Gutierrez Teran
Proc. International Conference on Mobile and Miniaturized Terahertz Systems (ICMMTS 2025), (2025)
DOI: 10.1109/ICMMTS62835.2025.10926047
(42) Impact of Thermal Effects on Cryptographic Resilience: A Study of an ASIC Implementation of the Montgomery Ladder
I. Kabin, P. Langendörfer, Z. Dyka
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963949, (Total Resilience)
(43) Impact of Thermal Effects on Cryptographic Resilience: A Study of an ASIC Implementation of the Montgomery Ladder
I. Kabin, P. Langendörfer, Z. Dyka
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963949, (Resilient Systems)
(44) Development of a Universal FPGA-Based Coprocessor for 5G NR and WLAN LDPC Coding
L. Lopacinski, Y. Jian, M. Nauman, P. Shakya, M. Krstic, E. Grass
Proc. 34th European Conference on Networks and Communications & 6G Summit (EuCNC/6G Summit 2025), 268 (2025)
DOI: 10.1109/EuCNC/6GSummit63408.2025.11037065, (PSSS-FEC)
(45) Development of a Universal FPGA-Based Coprocessor for 5G NR and WLAN LDPC Coding
L. Lopacinski, Y. Jian, M. Nauman, P. Shakya, M. Krstic, E. Grass
Proc. 34th European Conference on Networks and Communications & 6G Summit (EuCNC/6G Summit 2025), 268 (2025)
DOI: 10.1109/EuCNC/6GSummit63408.2025.11037065, (COREnext)
(46) Accelerate SEU Simulation-based Fault Injection with Spatio-Temporal Graph Convolutional Networks
L. Lu, J.-C. Chen, A. Balakrishnan, M. Ulbricht, M. Krstic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 44(7), 2599 (2025)
DOI: 10.1109/TCAD.2025.3526748, (Scale4Edge)
Evaluating the sensitivity of circuits to Single Event Upset (SEU) faults has become increasingly important and challenging due to the growing complexity of circuits. Simulation-based fault injection is time-intensive, particularly for highly complex circuits. This paper proposes a novel approach using Spatio-temporal Graph Convolutional Networks (STGCN) to predict SEU fault propagation results in circuits. By representing circuits’ structure as graphs and integrating temporal features from the simulation workload, STGCNs can learn from these spatio-temporal graphs to identify SEU fault propagation patterns. To validate this method, we test it on six evaluation circuits, achieving a prediction accuracy of 93-99%. Given this performance, to accelerate SEU simulation-based fault injection, we divide SEU faults into three subsets and use a STGCN fine-tuned on the training and validation dataset to predict SEU fault propagation in the test dataset, eliminating the need for simulation and reducing the required time. To identify an efficient dataset separation method, we compare three sampling methods: spatial sampling (sampling flip-flops for injected faults), temporal sampling (sampling time points for fault injection), and hybrid sampling (incorporating both spatial and temporal sampling). The hybrid sampling approach is the most promising, optimizing the trade-off between efficiency and accuracy. This approach reduces simulation time by 50% while maintaining accuracy above 95% on the six evaluation circuits.
(47) A Software-Defined Radio Solution for Integrated mmWave Communication and Sensing
N. Maletic, M. Petri, M. Appel, E. Grass
Proc. IEEE Wireless Communications and Networking Conference (WCNC 2025), (2025)
DOI: 10.1109/WCNC61545.2025.10978623, (Open 6G Hub)
(48) Channel State Information Analysis for Jamming Attack Detection in Static and Dynamic UAV Networks – An Experimental Study
P. Mykytyn, R. Chitauro, Z. Dyka, P. Langendörfer
Proc. 21st Annual International Conference on Distributed Computing in Smart Systems and the Internet of Things (DCOSS-IoT 2025), 322 (2025)
DOI: 10.1109/DCOSS-IoT65416.2025.00060, (EMiL)
(49) Channel State Information Analysis for Jamming Attack Detection in Static and Dynamic UAV Networks – An Experimental Study
P. Mykytyn, R. Chitauro, Z. Dyka, P. Langendörfer
Proc. 21st Annual International Conference on Distributed Computing in Smart Systems and the Internet of Things (DCOSS-IoT 2025), 322 (2025)
DOI: 10.1109/DCOSS-IoT65416.2025.00060, (iCampus II)
(50) OTFS Sensing with SDR: Experimental Results and Analysis
M. Nauman, L. Lopacinski, N. Maletic, M. Scheide, J. Gutiérrez Teran, M. Krstic, E. Grass
Proc. 101st IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(PSSS-FEC)
(51) OTFS Modulation: Synchronization Challenges, Solutions, and Experimental Results
M. Nauman, L. Lopacinski, N. Maletic, M. Scheide, J. Gutiérrez Teran, M. Krstic, E. Grass
Proc. 14th International ITG Conference on Systems, Communications, and Coding (SCC 2025), (2025)
DOI: 10.1109/IEEECONF62907.2025.10949106, (PSSS-FEC)
(52) Machine Learning-Based Error Detection and Function Approximation for Reliable Computing
J. Nedeljkovic, G. Nikolic, T. Nikolic, M. Andjelkovic, M. Krstic
Proc. 60th International Scientific Conference on Information, Communication and Energy Systems and Technologies (ICEST 2025), 1 (2025)
DOI: 10.1109/ICEST66328.2025.11098454, (AIDA4Edge)
(53) Evaluation of Machine Learning Models for Enhancing System Reliability
J. Nedeljkovic, G. Nikolic, M. Andjelkovic, T. Nikolic
Proc. 12th International Conference on Electrical, Electronic and Computing Engineering (IcETRAN 2025), (2025)
DOI: 10.1109/IcETRAN66854.2025.11114229, (AIDA4Edge)
(54) A Fully Asynchronous Unsourced Random Access Scheme
M. Özates, M. Kazemi, G. Liva, D. Gündüz
Proc. 26th IEEE Workshop on Signal Processing and Artificial Intelligence for Wireless Communications (SPAWC 2025), (2025)
DOI: 10.1109/SPAWC66079.2025.11143497, (6G-SENSES)
(55) ODMA-Based Cell-Free Unsourced Random Access with Successive Interference Cancellation
M. Özates, M. Kazemi, E. Jorswieck, D. Gündüz
Proc. 101st IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(6G-SENSES)
(56) Green ICT – Measurement Hubs and Testbeds for mm-Wave and Sub-THz Communication Devices
G. Panic, D. Cvetkovski, N. Maletic
Proc. 12th International Conference on Electrical, Electronic, and Computing Engineering (IcETRAN 2025), (2025)
DOI: 10.1109/IcETRAN66854.2025.11114094, (GreenICT)
(57) Messung ökobilanzrelevanter Parameter von MIMO-Kommunikationssystemen in der IHP-Antennenmesskammer
G. Panic, D. Cvetkovski
zu finden unter: https://greenict.de/messung-okobilanzrelevanter-parameter-von-mimo-kommunikationssystemen-in-der-ihp-antennenmesskammer/
(GreenICT)
(58) SQNR Approximation Analysis of the FP24 Format of Laplacian Source in a Wide Variance Range
S. Peric, Z. Peric, B. Denic, M. Dincic, A. Jovanovic, M. Andjelkovic
Proc. 60th International Scientific Conference on Information, Communication and Energy Systems and Technologies (ICEST 2025), 1 (2025)
DOI: 10.1109/ICEST66328.2025.11098267, (AIDA4Edge)
(59) Demonstration: Real-Time mmWave Integrated Communication and Sensing
M. Petri, N. Maletic
Proc. IEEE Wireless Communications and Networking Conference (WCNC 2025), (2025)
DOI: 10.1109/WCNC61545.2025.10978398, (Open 6G Hub)
(60) A mmWave JCAS System for Real-Time High-Data Rate Communication and RADAR Sensing
M. Petri, N. Maletic
IEEE Access 13, 117700 (2025)
DOI: 10.1109/ACCESS.2025.3586645, (Open 6G Hub)
This paper presents a real-time millimeter-wave (mmWave) joint communication and sensing (JCAS) system, supporting bi-directional data communication with up to 5.8 Gbit/s coded data rate as well as mono-static radio detection and ranging (RADAR) with a range resolution of 6.7 cm and up to 2.1 kHz sensing rate. The same hardware resources, i.e. an orthogonal frequency-division multiplexing (OFDM) baseband processor and a beam-steering phased array antenna frontend, the same signal waveform and the same frequency channel are used for both sensing and communication. After a description of one intended use case and the design constraints, the system architecture is described in detail. The focus is on two main modules, i.e. the advanced extensible interface 4 (AXI4) stream crossbar switch and the sensing controller, while changes of the basic OFDM baseband processor design are also explained. For the sensing function, the used hardware-based OFDM baseband processor does not provide a sufficiently precise synchronization of received frames, so a method for the temporal alignment of the received channel impulse responses (CIRs) for different beams is developed and assessed. The evaluation of the system performance and the measurement results highlight that it is possible to perform very precise sensing with an OFDM baseband processor purely developed for data communication. The presented method for the CIR alignment does not depend on the baseband signal processing and can be used in any JCAS system with full duplex sensing.
(61) Horizontal Attack against EC kP Accelerator under Laser Illumination
D. Petryk, I. Kabin, P. Langendörfer, Z. Dyka
Electronics (MDPI) 14(10), 2072 (2025)
DOI: 10.3390/electronics14102072, (Resilient Systems)
Devices employing cryptographic approaches have to be resistant to physical attacks. Side-Channel Analysis (SCA) and Fault Injection (FI) attacks are frequently used to reveal cryptographic keys. In this paper, we present a combined SCA and laser illumination attack against an Elliptic Curve Scalar Multiplication accelerator, while using different equipment for the measurement of its power traces, i.e., we performed the measurements using a current probe from Riscure and a differential probe from Teledyne LeCroy, with an attack success of 70% and 90%, respectively. Our experiments showed that laser illumination increased the power consumption of the chip, especially its static power consumption, but the success of the horizontal power analysis attacks changed insignificantly. After applying 100% of the laser beam output power and illuminating the smallest area of 143 µm2, we observed an offset of 17 mV in the measured trace. We assume that using a laser with a high laser beam power, as well as concentrating on measuring and analysing only static current, can significantly improve the attack’s success. The attacks exploiting the Static Current under Laser Illumination (SCuLI attacks) are novel, and their potential has not yet been fully investigated. These attacks can be especially dangerous against cryptographic chips manufactured in downscaling technologies. If such attacks are feasible, appropriate countermeasures have to be proposed in the future.
(62) Horizontal Side-Channel Analysis Attack against Elliptic Curve Scalar Multiplication Accelerator under Laser Illumination
D. Petryk, I. Kabin, P. Langendörfer, Z. Dyka
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963958, (Total Resilience)
(63) SCA Test Results Depend on the Measurement Equipment: Riscure vs. Teledyne LeCroy
D. Petryk, Z. Dyka, P. Langendörfer, I. Kabin
Proc. 3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec 2025), (2025)
(Resilient Systems)
(64) Horizontal Side-Channel Analysis Attack against Elliptic Curve Scalar Multiplication Accelerator under Laser Illumination
D. Petryk, I. Kabin, P. Langendörfer, Z. Dyka
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963958, (Resilient Systems)
(65) SCA Test Results Depend on the Measurement Equipment: Riscure vs. Teledyne LeCroy
D. Petryk, Z. Dyka, P. Langendörfer, I. Kabin
Proc. 3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec 2025), (2025)
(Total Resilience)
(66) Vulnerable or Not: SCA Test Results Strongly Depend on the Measurement Equipment
D. Petryk, I. Kabin, Z. Dyka
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Total Resilience)
(67) Vulnerable or Not: SCA Test Results Strongly Depend on the Measurement Equipment
D. Petryk, I. Kabin, Z. Dyka
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Resilient Systems)
(68) Sensitivity of Logic Cells to Laser Fault Injections: An Overview of Experimental Results for IHP Technologies
D. Petryk, P. Langendörfer, Z. Dyka
IEEE Transactions on Device and Materials Reliability 25(3), 410 (2025)
DOI: 10.1109/TDMR.2025.3596380, (Resilient Systems)
In this work, we provide an overview of our front-side Fault Injection (FI) experiments with different logic cells manufactured in two IHP BiCMOS technologies using Riscure equipment for laser FIs. We were able to inject faults into different types of cells including standard library cells as well as into two types of radiation tolerant flip-flops. Experimenting with radiation-tolerant flip-flops faults were injected illuminating areas with PMOS transistors in OFF state. We determined the cells areas, which were sensitive to the laser FI attacks. Only few works discussed this aspect in the past determining NMOS transistors as the sensitive part of the logic cells. Knowledge about the areas which are sensitive to the laser FI attacks can be generalized experimenting with other technologies and used in future by designers to implement corresponding countermeasure(s) at the initial stage of chip development.
(69) Horizontal Attack against EC kP Accelerator under Laser Illumination
D. Petryk, I. Kabin, P. Langendörfer, Z. Dyka
Electronics (MDPI) 14(10), 2072 (2025)
DOI: 10.3390/electronics14102072, (Total Resilience)
Devices employing cryptographic approaches have to be resistant to physical attacks. Side-Channel Analysis (SCA) and Fault Injection (FI) attacks are frequently used to reveal cryptographic keys. In this paper, we present a combined SCA and laser illumination attack against an Elliptic Curve Scalar Multiplication accelerator, while using different equipment for the measurement of its power traces, i.e., we performed the measurements using a current probe from Riscure and a differential probe from Teledyne LeCroy, with an attack success of 70% and 90%, respectively. Our experiments showed that laser illumination increased the power consumption of the chip, especially its static power consumption, but the success of the horizontal power analysis attacks changed insignificantly. After applying 100% of the laser beam output power and illuminating the smallest area of 143 µm2, we observed an offset of 17 mV in the measured trace. We assume that using a laser with a high laser beam power, as well as concentrating on measuring and analysing only static current, can significantly improve the attack’s success. The attacks exploiting the Static Current under Laser Illumination (SCuLI attacks) are novel, and their potential has not yet been fully investigated. These attacks can be especially dangerous against cryptographic chips manufactured in downscaling technologies. If such attacks are feasible, appropriate countermeasures have to be proposed in the future.
(70) Classification of Epileptic Seizures by Simple Machine Learning Techniques: Application to Animals’ Electroencephalography Signals
I. Pidvalnyi, A. Kostenko, O. Sudakov, D. Isaev, O. Maximyuk, O. Krishtal, O. Iegorova, I. Kabin, Z. Dyka, S. Ortmann, P. Langendörfer
IEEE Access 13, 8951 (2025)
DOI: 10.1109/ACCESS.2025.3527866, (DFG-Resilient Systems for Real Time Prediction of Epileptic Seizures)
Detection and prediction of the onset of seizures are among the most challenging problems in epilepsy diagnostics and treatment. Small electronic devices capable of doing that will improve the quality of life for epilepsy patients while also open new opportunities for pharmacological intervention. This paper presents a novel approach using machine learning techniques to detect seizures onset using electroencephalography (EEG) signals. The proposed approach was tested on EEG data recorded in rats with pilocarpine model of temporal lobe epilepsy. A principal component analysis was applied for feature selection before using a support vector machine for the detection of seizures. Hjorth's parameters and Daubechies discrete wavelet transform coefficients were found to be the most informative features of EEG data. We found that the support vector machine approach had a classification sensitivity of 90% and a specificity of 74% for detecting ictal episodes. Changing the epoch parameter from one to twenty-one seconds results in changing the redistribution of principal components’ values to 10% but does not affect the classification result. Support vector machines are accessible and convenient methods for classification that have achieved promising classification quality, and are rather lightweight compared to other machine learning methods. So we suggest their future use in mobile devices for early epileptic seizure and preictal episodes detection.
(71) Classification of Epileptic Seizures by Simple Machine Learning Techniques: Application to Animals’ Electroencephalography Signals
I. Pidvalnyi, A. Kostenko, O. Sudakov, D. Isaev, O. Maximyuk, O. Krishtal, O. Iegorova, I. Kabin, Z. Dyka, S. Ortmann, P. Langendörfer
IEEE Access 13, 8951 (2025)
DOI: 10.1109/ACCESS.2025.3527866, (Total Resilience)
Detection and prediction of the onset of seizures are among the most challenging problems in epilepsy diagnostics and treatment. Small electronic devices capable of doing that will improve the quality of life for epilepsy patients while also open new opportunities for pharmacological intervention. This paper presents a novel approach using machine learning techniques to detect seizures onset using electroencephalography (EEG) signals. The proposed approach was tested on EEG data recorded in rats with pilocarpine model of temporal lobe epilepsy. A principal component analysis was applied for feature selection before using a support vector machine for the detection of seizures. Hjorth's parameters and Daubechies discrete wavelet transform coefficients were found to be the most informative features of EEG data. We found that the support vector machine approach had a classification sensitivity of 90% and a specificity of 74% for detecting ictal episodes. Changing the epoch parameter from one to twenty-one seconds results in changing the redistribution of principal components’ values to 10% but does not affect the classification result. Support vector machines are accessible and convenient methods for classification that have achieved promising classification quality, and are rather lightweight compared to other machine learning methods. So we suggest their future use in mobile devices for early epileptic seizure and preictal episodes detection.
(72) HyRPF: Hybrid RRAM Prototyping on FPGA
D. Reiser, J. Knödtel, L. Almeeva, J. Wen, A. Baroni, M. Krstic, M. Reichenbach
Proc. 24th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2024) in: Lecture Notes in Computer Science, LNCS 15226, 199 (2025)
DOI: 10.1007/978-3-031-78377-7_14
(73) Rate Analysis and Optimization of LoS Beyond Diagonal RIS-Assisted MIMO Systems
I. Santamaria, J. Gutiérrez Teran, M. Soleymani, E. Jorswieck
IEEE Communications Letters 29(6), 1325 (2025)
DOI: 10.1109/LCOMM.2025.3560380, (6G-SENSES)
In this letter, we derive an expression for the achievable rate in a multiple-input multiple-output (MIMO) system assisted by a beyond-diagonal reconfigurable intelligent surface (BD-RIS) when the channels to and from the BD-RIS are line-of-sight (LoS) while the direct link is non-line-of-sight (NLoS). The rate expression allows to derive the optimal unitary and symmetric scattering BD-RIS matrix in closed form. Our simulation results show that the proposed solution is competitive even under the more usual Ricean channel fading model when the direct link is weak.
(74) Interference Minimization in Beyond-Diagonal RIS-assisted MIMO Interference Channels
I. Santamaria, M. Soleymani, E. Jorswieck, J. Gutiérrez Teran
IEEE Open Journal of Vehicular Technology 6, 1005 (2025)
DOI: 10.1109/OJVT.2025.3555425, (6G-SENSES)
This paper proposes a two-stage approach for passive and active beamforming in multiple-input multiple-output (MIMO) interference channels (ICs) assisted by a beyond-diagonal reconfigurable intelligent surface (BD-RIS). In the first stage, the passive BD-RIS is designed to minimize the aggregate interference power at all receivers, a cost function called interference leakage (IL). To this end, we propose an optimization algorithm in the manifold of unitary matrices and a suboptimal but computationally efficient solution. In the second stage, users' active precoders are designed under different criteria such as minimizing the IL (min-IL), maximizing the signal-to-interference-plus-noise ratio (max-SINR), or maximizing the sum rate (max-SR). The residual interference not cancelled by the BD-RIS is treated as noise by the precoders. Our simulation results show that the max-SR precoders provide more than 20% sum rate improvement compared to other designs, especially when the BD-RIS has a moderate number of elements (M<20) and users transmit with high power, in which case the residual interference is still significant.
(75) Impact of Different Antenna Arrangements and Transmitter Tilt to D-Band LoS MIMO Channel
P. Shakya, D. Cvetkovski, K. KrishneGowda, L. Lopancinski, E. Grass
Proc. IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(6G-RIC)
(76) Impact of Different Antenna Arrangements and Transmitter Tilt to D-Band LoS MIMO Channel
P. Shakya, D. Cvetkovski, K. KrishneGowda, L. Lopancinski, E. Grass
Proc. IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(PSSS-FEC)
(77) Enhanced Miss Forest and Multivariate Time Series Prediction of Wind Speed Using Deep Learning
T. Sidhaarth, P.A. Obla, N.N. Patil, Z. Stamenkovic, S.P. Raja
Journal of Circuits, Systems, and Computers (JCSC) 34(12), 2530006 (2025)
DOI: 10.1142/S0218126625300065
As environmental concerns become increasingly serious, renewable energy sources are being prioritized to meet growing demands, among which wind energy stands out as a technologically efficient option. However, the unpredictable nature of offshore wind energy continues to pose challenges for reliable integration into power grids. This study tackles this problem by focusing on improving wind speed prediction by employing a modified Miss Forest algorithm for time series imputation, which achieved the lowest NRMSE: 0.0079, 0.0156 and, 0.0730 among the other imputation methods when compared across three datasets. Alongside the Miss Forest, deep learning models such as Bayesian Optimized Stacked Long Short-Term Memory (BO-SLSTM), Deep Long Short-Term Memory (DLSTM), Gated Recurrent Unit (GRU), Convolutional Neural Network (CNN), and a hybrid Convolutional Long Short-Term Memory (CNN-LSTM) model were applied on real-time wind speed data from an offshore site in Gujarat, India. Furthermore, the Friedman Test was conducted to assess the statistical difference in model performance, yielding a p-value of 0.721, indicating no significant difference among the models. Among the models, the DLSTM demonstrated the best performance solely in terms of the error metrics, while CNN proved to be the most computationally efficient.
(78) Resistance Test Discovered an Inherent Vulnerability of Cryptographic ASICs to Simple SCA
A.A. Sigourou, Z. Dyka, I. Kabin
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Total Resilience)
(79) Resistance Test Discovered an Inherent Vulnerability of Cryptographic ASICs to Simple SCA
A.A. Sigourou, Z. Dyka, I. Kabin
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Resilient Systems)
(80) Distinguishability between Multiplication and Squaring Operations: A New Marker
A.A. Sigourou, Z. Dyka, P. Langendörfer, I. Kabin
Proc. 3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec 2025), (2025)
(Total Resilience)
(81) Distinguishability between Multiplication and Squaring Operations: A New Marker
A.A. Sigourou, Z. Dyka, P. Langendörfer, I. Kabin
Proc. 3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec 2025), (2025)
(Resilient Systems)
(82) Atomic Patterns: Field Operation Distinguishability on Cryptographic ASICs
A.A. Sigourou, Z. Dyka, P. Langendörfer, I. Kabin
Proc. IEEE International Conference on Cyber Security and Resilience (CSR 2025), 990 (2025)
DOI: 10.1109/CSR64739.2025.11130154, (Total Resilience)
(83) Atomic Patterns: Field Operation Distinguishability on Cryptographic ASICs
A.A. Sigourou, Z. Dyka, P. Langendörfer, I. Kabin
Proc. IEEE International Conference on Cyber Security and Resilience (CSR 2025), 990 (2025)
DOI: 10.1109/CSR64739.2025.11130154, (Resilient Systems)
(84) Revisiting Atomic Patterns for Elliptic Curve Scalar Multiplication Revealing Inherent Vulnerability to Simple SCA
A.A. Sigourou, Z. Dyka, S.H. Li , P. Langendörfer, I. Kabin
Proc. 12th IFIP International Conference on New Technologies, Mobility and Security (NTMS 2025), 252 (2025)
DOI: 10.1109/NTMS65597.2025.11076762, (Total Resilience)
(85) Machine Learning Techniques for Smart Agriculture
Z. Stamenkovic
Proc. 12th International Conference on Electrical, Electronic and Computing Engineering (ICETRAN 2025), 95 (2025)
(86) On-Chip Cross-Layer Sensing for Mission-Mode Monitoring of Resilient Systems: Towards Silicon Lifecycle Management
F. Vargas
Proc. 37. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(87) On-Chip Aging Sensor Core for Silicon Lifecycle Management
F. Vargas, A. Balakrishnan
Proc. IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963953
(88) Self-Aware Silicon: Enhancing Lifecycle Management with Intelligent Testing and Data Insights
F. Vargas, M. Andjelkovic, M. Krstic, A. Kar, S. Deshwal, Y. Chauhan, H. Amrouch, D. Tille, S. Huhn
Proc. 30th IEEE European Test Symposium (ETS 2025), (2025)
DOI: 10.1109/ETS63895.2025.11049649
(89) Particle Filter Localization using a Hybrid Sub-6 GHz and mmWave System
R. Vasist, V. Sark, J. Gutiérrez Teran, E. Grass
Proc. 101st IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(BeGREEN)
(90) A Cross-Layer Methodology for Assessing Silent Data Corruption Effects on DLA Families
A. Veronesi, M. Krstic, D. Bertozzi
Proc. 37. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(91) RRAMulator: An Efficient FPGA-based Emulator for RRAM Crossbar with Device Variability and Energy Consumption Evaluation
J. Wen, F. Vargas, F. Zhu, D. Reiser, A. Baroni, M. Fritscher, E. Perez, M. Reichenbach, Ch. Wenger, M. Krstic
Microelectronics Reliability 168, 115630 (2025)
DOI: 10.1016/j.microrel.2025.115630, (6G-RIC)
The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current–voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector–matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.
(92) ReDiM: An Efficient Strategy for Read Disturb Mitigation in RRAM-Based Accelerators
J. Wen, A. Baroni, A. Mistroni, E. Perez, C. Zambelli, Ch. Wenger, M. Krstic, L.M. Bolzani Pöhls
Proc. 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2025), (2025)
DOI: 10.1109/IOLTS65288.2025.11117065, (INSEKT)
(93) ReDiM: An Efficient Strategy for Read Disturb Mitigation in RRAM-Based Accelerators
J. Wen, A. Baroni, A. Mistroni, E. Perez, C. Zambelli, Ch. Wenger, M. Krstic, L.M. Bolzani Pöhls
Proc. 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2025), (2025)
DOI: 10.1109/IOLTS65288.2025.11117065, (6G-RIC)
(94) ImSTDP: Implicit Timing On-Chip STDP Learning
D. Zhao, O. Schrape, Z. Stamenkovic, M. Krstic
IEEE Transactions on Circuits and Systems I 72(2), 868 (2025)
DOI: 10.1109/TCSI.2024.3450958
Spike-Timing-Dependent Plasticity (STDP) is a biological-plausible learning mechanism widely adopted for building Spiking Neural Networks (SNNs). It determines plasticity polarity and synapse strength change according to the timing difference between pre-and postsynaptic spikes. The learning curves of STDP differ in temporal window size, magnitude and polarity across different synapse types and brain regions and even within a cell, in different dendritic compartments. To accelerate on-chip STDP learning, various implementations have been proposed. However, they either introduce significant latency due to costly counter-based time difference calculation and substantial area cost due to the implementation of weight change LUTs, or lose biologically-plausible timing information due to oversimplification. For low-cost and efficient on-chip learning, a high-throughput Implicit-timing STDP (ImSTDP) with optimized SR depth and a low-cost register-based Implicit-Timing Look-up (ITL) are proposed. ASIC implementation in 22 nm technology demonstrates that ImSTDP can achieve up to 2 × throughput improvement and 3.61 × power efficiency improvement at 27% less area cost compared to the cutting-edge counter-LUT on-chip STDP learning solution.
S. Aleksic, P. Obla, S.P. Raja, Z. Stamenkovic
Proc. 10th International Conference on Radiation Applications (RAP 2025), abstr. book 158 (2025)
(2) Large Fractional Bandwidth D-Band Power Amplifier for 6G Communications in 130-nm SiGe BiCMOS Technology
M.K. Ali, T. Herbel, G. Panic, D. Kissinger
Proc. 16th German Microwave Conference (GeMiC 2025), 615 (2025)
DOI: 10.23919/GeMiC64734.2025.10979019, (6GKom)
(3) Optical Transport Network Optimization Supporting Integrated Sensing and Communication Services
M. Anastasopoulos, J. Gutiérrez Teran, A. Tzanakaki
Proc. 50th Optical Fiber Communications Conference and Exposition (OFC 2025), W2A.48 (2025)
(6G-SENSES)
(4) Demonstration of a Multi-Technology 6G Transport Network Integrating THz and Optical Network Technologies Empowered by Federated Learning
M. Anastasopoulos, A. Tzanakaki, Y. Jian, L. Lopacinski, J. Gutiérrez Teran, I. Mesogiti, E. Theodoropoulou, G. Lyberopoulos
Journal of Optical Communications and Networking 17(8),C156 (2025)
DOI: 10.1364/JOCN.551626, (6G-SENSES)
This paper proposes a 6G architecture that adopts a multi-technology transport network integrating THz links and optical network technologies to interconnect the 6G radio access network and core domains. The proposed solution operates in a self-organized manner, taking advantage of the software defined networking (SDN) control of the optical network, while suitable SDN control is purposely developed for the THz solution. An end-to-end (E2E) Service Management and Orchestration (SMO) layer is adopted, offering intelligence capabilities in service provisioning and resource allocation across the 6G infrastructure through the adoption of a federated learning (FL) scheme. The proposed architecture and the developed control scheme are validated through an experimental demonstration. To the best of the authors’ knowledge, this is the first experimental demonstration of an autonomously controlled 6G network implementation integrating optical network technologies and THz links in a common transport network. The developed intelligent management framework empowered by FL to jointly optimize THz and multi-vendor optical network equipment supporting 6G services is also experimentally showcased.
(5) Comparison of Gate-Level Techniques for Mitigation of Single Event Transients in Combinational Logic
M. Andjelkovic, M. Krstic
Proc. 16th IEEE CASS Latin American Symposium on Circuts and Systems (LASCAS 2025), (2025)
(Open 6G Hub)
(6) Comparison of Gate-Level Techniques for Mitigation of Single Event Transients in Combinational Logic
M. Andjelkovic, M. Krstic
Proc. 16th IEEE CASS Latin American Symposium on Circuts and Systems (LASCAS 2025), (2025)
(6G-TakeOff)
(7) Analysis and Modeling of Single Event Transient Generation in Standard Combinational Cells
M. Andjelkovic, M. Krstic
Journal of Electronic Testing 41, 287 (2025)
DOI: 10.1007/s10836-025-06175-5, (6G-TakeOff)
Singe Event Transients (SETs) are one of the most common causes of data corruption and malfunction in digitial integrated circuits (ICs) employed in applications involving exposure to high-energy particles, such as space missions. Therefore, the ICs intended to operate in ionizing radiation environments should be designed with special measures to ensure sufficient tolerance to SETs. To achieve this, the SET generation and propagation effects should be well understood and properly assessed for a given design. In this paper, we investigate the SET generation in standard digital combinational cells. Using SPICE simulations, we have analyzed the dependence of generated SET pulse width on various design and operating parameters. The characterization was done for standard cells designed in IHP’s 130 nm process, using a bias-dependent current source to inject SETs. Employing analytical fitting to the simulation results, a model for the width of generated SET pulse in terms of particle’s Linear Energy Transfer (LET), drive strength of target gate, drive strength of load gate, supply voltage and temperature was formulated. The proposed model is defined as the sum of multiple components, enabling to identify the contribution of individual parameters. It was shown that the average relative error of the proposed model with respect to the results from SPICE simulations is below 10 % for LET greater than 2 MeVcm2mg-1, confirming the model's very good accuracy. The model could be used as a basis of an automated tool-flow for the analysis of SET effects in complex digital designs.
(8) Prediction of Single Event Transient Propagation Using Machine Learning Models
M. Andjelkovic, J.-C. Chen, J. Aleksic, V. Padmakumar, M. Marjanovic, N, Zazatis, T.R. Lenka, D. Dankovic, C. Sotiriou, F. Vargas
Proc. 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD 2025), (2025)
DOI: 10.1109/SMACD65553.2025.11092057, (TWIN-RELECT)
(9) Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT)
M. Andjelkovic, F. Vargas, M. Krstic, L. Dilillo, A. Michez, F. Wrobel, D. Bertozzi, M. Lujan, C. Georgakidis, N. Chatzivangelis, K. Tsilingiri, N. Zatatis, G.-I. Pagliaroutis, P. Tsoumanis, C. Sotiriou
Proc. 28th Design, Automation and Test in Europe Conference (DATE 2025), (2025)
DOI: 10.23919/DATE64628.2025.10992721, (TWIN-RELECT)
(10) Heterogeneous Integration of Advanced CMOS and Emerging Devices: Challenges and Solutions
L.M. Bolzani Poehls, A.L. Chinazzo, M. Benkhelifa, A. Kar, H. Amrouch, M. Krstic
Proc. 30th IEEE European Test Symposium (ETS 2025), (2025)
DOI: 10.1109/ETS63895.2025.11049636, (INSEKT)
(11) Heterogeneous Integration of Advanced CMOS and Emerging Devices: Challenges and Solutions
L.M. Bolzani Poehls, A.L. Chinazzo, M. Benkhelifa, A. Kar, H. Amrouch, M. Krstic
Proc. 30th IEEE European Test Symposium (ETS 2025), (2025)
DOI: 10.1109/ETS63895.2025.11049636, (TAICHIP)
(12) Towards Adaptive RISC-V based Systems for Non-Terrestrial Sub-THz Communication
H. Borchert, M. Ulbricht, M. Andjelkovic, D. Göhringer, M. Krstic
Proc. International Conference on Mobile and Miniaturized Terahertz Systems (ICMMTS 2025), (2025)
DOI: 10.1109/ICMMTS62835.2025.10926015, (Scale4Edge)
(13) Towards Adaptive RISC-V based Systems for Non-Terrestrial Sub-THz Communication
H. Borchert, M. Ulbricht, M. Andjelkovic, D. Göhringer, M. Krstic
Proc. International Conference on Mobile and Miniaturized Terahertz Systems (ICMMTS 2025), (2025)
DOI: 10.1109/ICMMTS62835.2025.10926015, (6G-TakeOff)
(14) Towards Adaptive RISC-V based Systems for Non-Terrestrial Sub-THz Communication
H. Borchert, M. Ulbricht, M. Andjelkovic, D. Göhringer, M. Krstic
Proc. International Conference on Mobile and Miniaturized Terahertz Systems (ICMMTS 2025), (2025)
DOI: 10.1109/ICMMTS62835.2025.10926015, (COREnext)
(15) Ultra-Low-Latency Data Link Layer TX Buffer Architecture for Wireless Communications
H. Borchert, K. KrishneGowda, M. Krstic
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2025), (2025)
DOI: 10.1109/ISVLSI65124.2025.11130195, (6G-RIC)
(16) Ultra-Low-Latency Data Link Layer TX Buffer Architecture for Wireless Communications
H. Borchert, K. KrishneGowda, M. Krstic
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2025), (2025)
DOI: 10.1109/ISVLSI65124.2025.11130195, (Open 6G Hub)
(17) D-Band Demonstration of Quasi-Optical and Analog Beam Reconfiguration using Phased Array and Lens for 6G Applications
M.A. Campo, S. Bruni, A. Lauer, M. Wleklinski, U. Gollor, W. Wischmann, A. Friedrich, C. Oikonomopoulos, O. Litschke, C. Herold, A. Malignaggi, N. Moroni, K.Krishnegowda, C. Carta, W. Keusgen
IEEE Transactions on Antennas and Propagation 73(8), 5064 (2025)
DOI: 10.1109/TAP.2025.3557716
In this paper, a hybrid quasi-optic and analogue beamforming approach is presented, involving an elliptical lens with an active focal plane array at D-band (110-170 GHz). Beamwidth reconfigurability and steering in two planes with enhanced performance are demonstrated. The quasi-optic technique minimizes the beam squint over frequency. Analogue phase shift in the focal plane array is used to increase the lens steering range. A prototype including two 4-channel D-band transceivers with on-chip antennas has been built as demonstrator. The resulting active focal plane array consists of 2x4 antenna elements, which are tuned in amplitude and phase to reconfigure the beam. The advantages of using a resonant leaky-wave cavity combined with a coherent array of feeds are discussed and quantified. Radiation pattern measurements performed with the calibrated active antenna validate the beam reconfiguration concept in two planes at 140 GHz. A steering loss reduction ranging from 2 to 4.5 dB is achieved in the whole D-band at 22° scan angle by applying beam steering in the feed radiation.
(18) Next-Gen TETRISC SoC - A Quad-Heterogeneous Design for Adaptive Fault Tolerance
J.-C. Chen, L. Lu, M. Ulbricht, M. Krstic
Proc. RISC-V Summit Europe (RISC-V 2024)
(Scale4Edge)
(19) Next-Gen TETRISC SoC - A Quad-Heterogeneous Design for Adaptive Fault Tolerance
J.-C. Chen, L. Lu, M. Ulbricht, M. Krstic
Proc. RISC-V Summit Europe (RISC-V 2024)
(Open 6G Hub)
(20) Dynamic Fault Mitigation for Space Radiation using Fault Injection and Machine Learning
J.-C. Chen, L. Lu, M. Andjelkovic, F. Vargas, M. Krstic
Journal of Electronic Testing 41, 273 (2025)
DOI: 10.1007/s10836-025-06183-5, (Open 6G Hub)
In aerospace applications, the demand for highly reliable systems necessitates advanced dynamic fault mitigation strategies to achieve the trade-off between system reliability, performance, and power efficiency in dynamic space radiation environments. However, traditional fault mitigation methods fall short in simulating space radiation dynamics, particularly during solar events, thus hindering the effective optimization of dynamic systems. This paper presents a novel methodology that integrates space radiation-driven fault injection with machine learning-enhanced dynamic Parity per Byte with Duplication (PBD) fault mitigation strategies. The methodology utilizes historical space radiation data, creating time-series fault datasets for precise simulation of dynamic space environments. These datasets are integrated into fault injection platforms and a fault prediction model training framework to assess the effectiveness of dynamic error correction strategies. The proposed approach was validated using several historical solar events on dynamic PBD-based RAM scrubbing. The results demonstrate the dynamic PBD method’s effectiveness in mitigating fault accumulation during SPEs, significantly enhancing RAM scrubbing performance by up to 13 times compared to five traditional static methods.
(21) N-Modular Redundancy Controller Generator for Adaptive Fault Tolerance Systems
J.-C. Chen, M. Ulbricht, M. Krstic
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Open 6G Hub)
(22) N-Modular Redundancy Controller Generator for Adaptive Fault Tolerance Systems
J.-C. Chen, M. Ulbricht, M. Krstic
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Scale4Edge)
(23) Dynamic Fault Mitigation for Space Radiation using Fault Injection and Machine Learning
J.-C. Chen, L. Lu, M. Andjelkovic, F. Vargas, M. Krstic
Journal of Electronic Testing 41, 273 (2025)
DOI: 10.1007/s10836-025-06183-5, (Scale4Edge)
In aerospace applications, the demand for highly reliable systems necessitates advanced dynamic fault mitigation strategies to achieve the trade-off between system reliability, performance, and power efficiency in dynamic space radiation environments. However, traditional fault mitigation methods fall short in simulating space radiation dynamics, particularly during solar events, thus hindering the effective optimization of dynamic systems. This paper presents a novel methodology that integrates space radiation-driven fault injection with machine learning-enhanced dynamic Parity per Byte with Duplication (PBD) fault mitigation strategies. The methodology utilizes historical space radiation data, creating time-series fault datasets for precise simulation of dynamic space environments. These datasets are integrated into fault injection platforms and a fault prediction model training framework to assess the effectiveness of dynamic error correction strategies. The proposed approach was validated using several historical solar events on dynamic PBD-based RAM scrubbing. The results demonstrate the dynamic PBD method’s effectiveness in mitigating fault accumulation during SPEs, significantly enhancing RAM scrubbing performance by up to 13 times compared to five traditional static methods.
(24) A Combined Strategy for Testing RRAMs after Manufacturing and during Lifetime
T. Copetti, S. Chakraborty, L.M. Bolzani Poehls
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963957
(25) RRAMs: A Lifecycle Management Strategy for Manufacturing and On-Line Testing
T.S. Copetti, L. Bolzani Poehls
Proc. 37. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(26) D-Band Line-of-Sight MIMO Link Demonstration
D. Cvetkovski, C. Herold, E. Grass
Proc. 24th IFIP International Conference on Networking (NETWORKING 2025)
(6G-RIC)
In this work, preliminary results from the prototyping phase of a 2x2 D-Band Line-of-Sight MIMO link are presented. Aiming to demonstrate ultra-high throughput for point-to-point fixed wireless links, line-of-sight MIMO is implemented and evaluated with the large modulation bandwidth that is available in the D-Band (110 - 170 GHz) of the millimeter-wave frequency range. The link demonstration is performed in a hardware-in-the-loop setup, at a 2 m range in an indoor conference hall environment. It is based on IHP’s D-Band 130-nm SiGe BiCMOS analog front-ends operating at a carrier frequency of 135 GHz, in combination with dielectric lenses. In order to obtain a near-orthogonal MIMO channel in line-of-sight conditions, the setup is relying on optimal arrangement between the transmit and receive antennas, according to the Rayleigh criterion. By performing spatial multiplexing of 2 QPSK-modulated data streams with 4 GHz modulation bandwidth, an aggregated throughput of 16 Gb/s is achieved during a live link demonstration. As the system is in its early development phase, it is subject to ongoing work to further enhance the link range and throughput.
(27) Case Study: NASCERR: In-Mission Self-Tuning Error Correction Approach for Space Applications
L. De Albuquerque, C. Luz Salles Cavalcante, D. Alencar, E. Mallet de Chauny Druesne, J.M. Matos Sobreira, M.A. Almeida Bezerra, A.A. da Silva, J.E. Silva Filho, J. Silveira, F.L. Vargas
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/GAST60528.2024.10520763
(28) Low-Loss GSG Bondwire Chip-to-Chip Interconnects from DC to 330 GHz
F.A. Dürrwald, F. Protze, D. Cvetkovski, T. Meister, R. Kraemer, F. Ellinger
Proc. 14th International Conference on Modern Circuits and Systems Technologies (MOCAST 2025), (2025)
DOI: 10.1109/MOCAST65744.2025.11083949, (DFG BAUDOT)
(29) A Fully Integrated Modular 2x4 220-260 GHz Beam-Forming Transmitter and Receiver with 50 Gbps Wireless Transmission in SiGe:C BiCMOS
M.H. Eissa, N. Maletic, M. Wietstruck, V. Sark, A. Malignaggi, W. Abdullah, C. Carta, G. Kahmen
IEEE Transactions on Terahertz Science and Technology 15(5), 805 (2025)
DOI: 10.1109/TTHZ.2025.3573157, (Open 6G Hub)
This article presents a 220-260 GHz fully integrated phased-array wireless system featuring direct conversion RF beam-forming. The system is constructed using fully integrated transmitter (Tx) and receiver (Rx) chips with on-chip antenna array. A 4-channel Tx and Rx are designed and fabricated in a 130nm SiGe BiCMOS process with fT / fmax = 300 / 500 GHz. A modular design approach enables the chips as building units for 2xN phased arrays and multiple-input multiple-output (MIMO) systems. A comprehensive design approach for the Tx and Rx chips focusing on key design decisions is presented in this work. The transmitter is equipped with a local oscillator (LO) multiplication chain, IQ up−conversion mixer, active RF splitting network, vector modulator phase shifter (VMPS), temperature sensors, and high output power amplifiers (PA). The PA with power−combining boost the effective isotropic radiated power (EIRP) and reduces the need for external lenses. The receiver is equipped with an LO chain, IQ down−conversion mixer, active RF combining network, VMPS, and low noise amplifiers (LNA). In both Tx and Rx the antenna array is composed of four differential double-folded dipole antennas with local backside etching (LBE). The Tx and Rx chips consume 4.4W and 1.84W of power respectively from a 3.5V supply while each occupying 25mm2 of silicon area. With a measured Tx array effective isotropic radiated power (EIRP) of 24 dBm, a beamforming wireless link is demonstrated supporting up to 50 Gbps of data rates across 85 cm of link distance with no need for focusing lenses and ±30º of scanning capability. With these capabilities, the presented modular chips enable future scaling for 2xN antenna arrays for sensing and communication applications.
(30) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (6G-RIC)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(31) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (iCampus II)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(32) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (HYB-RISC)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(33) Optimization of Beamforming and Transmit Power using DQN and Comparison with Traditional Techniques
P. Geranmayeh, E. Grass
IEEE Access 13, 94275 (2025)
DOI: 10.1109/ACCESS.2025.3573096, (IHP - Humboldt-Universität Joint-Lab)
As Artificial Intelligence (AI) and Machine Learning (ML) technologies continue to evolve, their integration into 5G and 6G networks has become critical for improving performance and efficiency. These technologies enhance wireless communication by leveraging deep neural networks and data-driven methods to optimize resource allocation, signal detection, and channel coding. They also address the growing need to reduce energy consumption in next-generation networks. Deep Q-Networks (DQN) play a key role in this transformation by enabling dynamic resource management, adaptive beamforming, and efficient network slicing. The use of DQN can improve spectrum utilization, power consumption, and beamforming in massive MIMO systems, supporting demands like eMBB and URLLC. In 6G, it is considered for optimizing resource allocation, dynamic beamforming, RIS control for Terahertz communication, and complex network slicing. This article focuses on maximizing channel capacity by deploying DQN to identify optimal beamforming angles and transmit power values for multiple transmitters and receivers. The model determines the best steering vectors and power levels to achieve maximum channel capacity while minimizing energy consumption and mutual interference. Its performance is compared to conventional optimization methods, demonstrating its effectiveness in enhancing the efficiency and reliability of 5G and 6G networks.
(34) Optimization of Beamforming and Transmit Power using DQN and Comparison with Traditional Techniques
P. Geranmayeh, E. Grass
IEEE Access 13, 94275 (2025)
DOI: 10.1109/ACCESS.2025.3573096, (5G-REMOTE)
As Artificial Intelligence (AI) and Machine Learning (ML) technologies continue to evolve, their integration into 5G and 6G networks has become critical for improving performance and efficiency. These technologies enhance wireless communication by leveraging deep neural networks and data-driven methods to optimize resource allocation, signal detection, and channel coding. They also address the growing need to reduce energy consumption in next-generation networks. Deep Q-Networks (DQN) play a key role in this transformation by enabling dynamic resource management, adaptive beamforming, and efficient network slicing. The use of DQN can improve spectrum utilization, power consumption, and beamforming in massive MIMO systems, supporting demands like eMBB and URLLC. In 6G, it is considered for optimizing resource allocation, dynamic beamforming, RIS control for Terahertz communication, and complex network slicing. This article focuses on maximizing channel capacity by deploying DQN to identify optimal beamforming angles and transmit power values for multiple transmitters and receivers. The model determines the best steering vectors and power levels to achieve maximum channel capacity while minimizing energy consumption and mutual interference. Its performance is compared to conventional optimization methods, demonstrating its effectiveness in enhancing the efficiency and reliability of 5G and 6G networks.
(35) A Fully-Integrated Four-Channel Phased Array D-Band Transceiver Achieving 10 GBit/s at 10 m
C. Herold, A. Karakuzulu, A. Malignaggi, M. Scheide, N. Maletic, K. Krishnegowda, C. Carta
Proc. 20th IEEE Radio & Wireless Week (RWW 2025), 30 (2025)
(6G-RIC)
(36) European Test Symposium Teams: an Anniversary Snapshot
M. Jenihhin, J. Raik, A. Jutman, N. Cherezova, R. Ubar, L. Miclea, S. Enyedi, I.Stefan, O. Stan, C. Corches, Z. Peng, P. Eles, R. DrechslerA, S. EggersglußB, G. FeyC, A. GlowatzB, D. TilleB, G. GielenA, A. CoyetteAB, W. DobbelaereB, R. VanhoorenB, P.-Y. Chuang, E.J. Marinissen, G. Di Natale, M. Barragan, P. Maistri, S. Mir, E.-I. Vatajelu, P. Bernardi, S. Di Carlo, P. Prinetto, M. Sonza Reorda, M. Violante, H.-G. Stratigopoulos, M.K. Michael, S. Neophytou, S. Hadjitheophanous, K. Christou, M. Skitsas, A. BosioA, B. DeveautourB, P. GirardC, M. TraiolaA, A. VirazelC, F. Fernandes dos SantosA, A. KritikakouAB, G. Casagranda, M. Vallero, F. Vella, P. Rech, L.M. Bolzani PoehlsA, M. KrsticAB, M. AndjelkovicA, F. VargasA, G. Tshagharyan, G. Harutyunyan, V. Vardanian, S. Shoukourian, Y. Zorian, J. DworakA, K. NepalB, T. ManikasA, M. Taouil, M. Fieback, A. Gebregiorgis, R. Bishnoi, S. Hamdioui, A. ChatterjeeA, A. SahaA, S. KomarrajuB, K. MaC, C. AmarnathD, M. Tahoori, M. Mayahinia, M. Rajabalipanah, K. Basharkhah, N. Nosrati, Z. Jahanpeima, Z. Navabi, H.-J. WunderlichA, S. HellebrandB
Proc. 30th IEEE European Test Symposium (ETS 2025), (2025)
(37) Packet Superposition HARQ Scheme Enabled by LDPC Coupled Codes
Y. Jian, L. Lopacinski, E. Grass
Proc. IEEE Wireless Communications and Networking Conference (WCNC 2025), (2025)
DOI: 10.1109/WCNC61545.2025.10978369, (PSSS-FEC)
(38) Performance Analysis of an Advanced HARQ Scheme Based on LDPC Coupled Codes
Y. Jian, L. Lopacinski, E. Grass
Proc. 101st IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(Open 6G Hub)
(39) Performance Analysis of an Advanced HARQ Scheme Based on LDPC Coupled Codes
Y. Jian, L. Lopacinski, E. Grass
Proc. 101st IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(PSSS-FEC)
(40) Packet Superposition HARQ Scheme Enabled by LDPC Coupled Codes
Y. Jian, L. Lopacinski, E. Grass
Proc. IEEE Wireless Communications and Networking Conference (WCNC 2025), (2025)
DOI: 10.1109/WCNC61545.2025.10978369, (6G-RIC)
(41) URLLC Networks Enabled by STAR-RIS, Rate Splitting, and Multiple Antennas
E. Jorswieck, M. Soleymani, I. Santamaria, J. Gutierrez Teran
Proc. International Conference on Mobile and Miniaturized Terahertz Systems (ICMMTS 2025), (2025)
DOI: 10.1109/ICMMTS62835.2025.10926047
(42) Impact of Thermal Effects on Cryptographic Resilience: A Study of an ASIC Implementation of the Montgomery Ladder
I. Kabin, P. Langendörfer, Z. Dyka
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963949, (Total Resilience)
(43) Impact of Thermal Effects on Cryptographic Resilience: A Study of an ASIC Implementation of the Montgomery Ladder
I. Kabin, P. Langendörfer, Z. Dyka
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963949, (Resilient Systems)
(44) Development of a Universal FPGA-Based Coprocessor for 5G NR and WLAN LDPC Coding
L. Lopacinski, Y. Jian, M. Nauman, P. Shakya, M. Krstic, E. Grass
Proc. 34th European Conference on Networks and Communications & 6G Summit (EuCNC/6G Summit 2025), 268 (2025)
DOI: 10.1109/EuCNC/6GSummit63408.2025.11037065, (PSSS-FEC)
(45) Development of a Universal FPGA-Based Coprocessor for 5G NR and WLAN LDPC Coding
L. Lopacinski, Y. Jian, M. Nauman, P. Shakya, M. Krstic, E. Grass
Proc. 34th European Conference on Networks and Communications & 6G Summit (EuCNC/6G Summit 2025), 268 (2025)
DOI: 10.1109/EuCNC/6GSummit63408.2025.11037065, (COREnext)
(46) Accelerate SEU Simulation-based Fault Injection with Spatio-Temporal Graph Convolutional Networks
L. Lu, J.-C. Chen, A. Balakrishnan, M. Ulbricht, M. Krstic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 44(7), 2599 (2025)
DOI: 10.1109/TCAD.2025.3526748, (Scale4Edge)
Evaluating the sensitivity of circuits to Single Event Upset (SEU) faults has become increasingly important and challenging due to the growing complexity of circuits. Simulation-based fault injection is time-intensive, particularly for highly complex circuits. This paper proposes a novel approach using Spatio-temporal Graph Convolutional Networks (STGCN) to predict SEU fault propagation results in circuits. By representing circuits’ structure as graphs and integrating temporal features from the simulation workload, STGCNs can learn from these spatio-temporal graphs to identify SEU fault propagation patterns. To validate this method, we test it on six evaluation circuits, achieving a prediction accuracy of 93-99%. Given this performance, to accelerate SEU simulation-based fault injection, we divide SEU faults into three subsets and use a STGCN fine-tuned on the training and validation dataset to predict SEU fault propagation in the test dataset, eliminating the need for simulation and reducing the required time. To identify an efficient dataset separation method, we compare three sampling methods: spatial sampling (sampling flip-flops for injected faults), temporal sampling (sampling time points for fault injection), and hybrid sampling (incorporating both spatial and temporal sampling). The hybrid sampling approach is the most promising, optimizing the trade-off between efficiency and accuracy. This approach reduces simulation time by 50% while maintaining accuracy above 95% on the six evaluation circuits.
(47) A Software-Defined Radio Solution for Integrated mmWave Communication and Sensing
N. Maletic, M. Petri, M. Appel, E. Grass
Proc. IEEE Wireless Communications and Networking Conference (WCNC 2025), (2025)
DOI: 10.1109/WCNC61545.2025.10978623, (Open 6G Hub)
(48) Channel State Information Analysis for Jamming Attack Detection in Static and Dynamic UAV Networks – An Experimental Study
P. Mykytyn, R. Chitauro, Z. Dyka, P. Langendörfer
Proc. 21st Annual International Conference on Distributed Computing in Smart Systems and the Internet of Things (DCOSS-IoT 2025), 322 (2025)
DOI: 10.1109/DCOSS-IoT65416.2025.00060, (EMiL)
(49) Channel State Information Analysis for Jamming Attack Detection in Static and Dynamic UAV Networks – An Experimental Study
P. Mykytyn, R. Chitauro, Z. Dyka, P. Langendörfer
Proc. 21st Annual International Conference on Distributed Computing in Smart Systems and the Internet of Things (DCOSS-IoT 2025), 322 (2025)
DOI: 10.1109/DCOSS-IoT65416.2025.00060, (iCampus II)
(50) OTFS Sensing with SDR: Experimental Results and Analysis
M. Nauman, L. Lopacinski, N. Maletic, M. Scheide, J. Gutiérrez Teran, M. Krstic, E. Grass
Proc. 101st IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(PSSS-FEC)
(51) OTFS Modulation: Synchronization Challenges, Solutions, and Experimental Results
M. Nauman, L. Lopacinski, N. Maletic, M. Scheide, J. Gutiérrez Teran, M. Krstic, E. Grass
Proc. 14th International ITG Conference on Systems, Communications, and Coding (SCC 2025), (2025)
DOI: 10.1109/IEEECONF62907.2025.10949106, (PSSS-FEC)
(52) Machine Learning-Based Error Detection and Function Approximation for Reliable Computing
J. Nedeljkovic, G. Nikolic, T. Nikolic, M. Andjelkovic, M. Krstic
Proc. 60th International Scientific Conference on Information, Communication and Energy Systems and Technologies (ICEST 2025), 1 (2025)
DOI: 10.1109/ICEST66328.2025.11098454, (AIDA4Edge)
(53) Evaluation of Machine Learning Models for Enhancing System Reliability
J. Nedeljkovic, G. Nikolic, M. Andjelkovic, T. Nikolic
Proc. 12th International Conference on Electrical, Electronic and Computing Engineering (IcETRAN 2025), (2025)
DOI: 10.1109/IcETRAN66854.2025.11114229, (AIDA4Edge)
(54) A Fully Asynchronous Unsourced Random Access Scheme
M. Özates, M. Kazemi, G. Liva, D. Gündüz
Proc. 26th IEEE Workshop on Signal Processing and Artificial Intelligence for Wireless Communications (SPAWC 2025), (2025)
DOI: 10.1109/SPAWC66079.2025.11143497, (6G-SENSES)
(55) ODMA-Based Cell-Free Unsourced Random Access with Successive Interference Cancellation
M. Özates, M. Kazemi, E. Jorswieck, D. Gündüz
Proc. 101st IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(6G-SENSES)
(56) Green ICT – Measurement Hubs and Testbeds for mm-Wave and Sub-THz Communication Devices
G. Panic, D. Cvetkovski, N. Maletic
Proc. 12th International Conference on Electrical, Electronic, and Computing Engineering (IcETRAN 2025), (2025)
DOI: 10.1109/IcETRAN66854.2025.11114094, (GreenICT)
(57) Messung ökobilanzrelevanter Parameter von MIMO-Kommunikationssystemen in der IHP-Antennenmesskammer
G. Panic, D. Cvetkovski
zu finden unter: https://greenict.de/messung-okobilanzrelevanter-parameter-von-mimo-kommunikationssystemen-in-der-ihp-antennenmesskammer/
(GreenICT)
(58) SQNR Approximation Analysis of the FP24 Format of Laplacian Source in a Wide Variance Range
S. Peric, Z. Peric, B. Denic, M. Dincic, A. Jovanovic, M. Andjelkovic
Proc. 60th International Scientific Conference on Information, Communication and Energy Systems and Technologies (ICEST 2025), 1 (2025)
DOI: 10.1109/ICEST66328.2025.11098267, (AIDA4Edge)
(59) Demonstration: Real-Time mmWave Integrated Communication and Sensing
M. Petri, N. Maletic
Proc. IEEE Wireless Communications and Networking Conference (WCNC 2025), (2025)
DOI: 10.1109/WCNC61545.2025.10978398, (Open 6G Hub)
(60) A mmWave JCAS System for Real-Time High-Data Rate Communication and RADAR Sensing
M. Petri, N. Maletic
IEEE Access 13, 117700 (2025)
DOI: 10.1109/ACCESS.2025.3586645, (Open 6G Hub)
This paper presents a real-time millimeter-wave (mmWave) joint communication and sensing (JCAS) system, supporting bi-directional data communication with up to 5.8 Gbit/s coded data rate as well as mono-static radio detection and ranging (RADAR) with a range resolution of 6.7 cm and up to 2.1 kHz sensing rate. The same hardware resources, i.e. an orthogonal frequency-division multiplexing (OFDM) baseband processor and a beam-steering phased array antenna frontend, the same signal waveform and the same frequency channel are used for both sensing and communication. After a description of one intended use case and the design constraints, the system architecture is described in detail. The focus is on two main modules, i.e. the advanced extensible interface 4 (AXI4) stream crossbar switch and the sensing controller, while changes of the basic OFDM baseband processor design are also explained. For the sensing function, the used hardware-based OFDM baseband processor does not provide a sufficiently precise synchronization of received frames, so a method for the temporal alignment of the received channel impulse responses (CIRs) for different beams is developed and assessed. The evaluation of the system performance and the measurement results highlight that it is possible to perform very precise sensing with an OFDM baseband processor purely developed for data communication. The presented method for the CIR alignment does not depend on the baseband signal processing and can be used in any JCAS system with full duplex sensing.
(61) Horizontal Attack against EC kP Accelerator under Laser Illumination
D. Petryk, I. Kabin, P. Langendörfer, Z. Dyka
Electronics (MDPI) 14(10), 2072 (2025)
DOI: 10.3390/electronics14102072, (Resilient Systems)
Devices employing cryptographic approaches have to be resistant to physical attacks. Side-Channel Analysis (SCA) and Fault Injection (FI) attacks are frequently used to reveal cryptographic keys. In this paper, we present a combined SCA and laser illumination attack against an Elliptic Curve Scalar Multiplication accelerator, while using different equipment for the measurement of its power traces, i.e., we performed the measurements using a current probe from Riscure and a differential probe from Teledyne LeCroy, with an attack success of 70% and 90%, respectively. Our experiments showed that laser illumination increased the power consumption of the chip, especially its static power consumption, but the success of the horizontal power analysis attacks changed insignificantly. After applying 100% of the laser beam output power and illuminating the smallest area of 143 µm2, we observed an offset of 17 mV in the measured trace. We assume that using a laser with a high laser beam power, as well as concentrating on measuring and analysing only static current, can significantly improve the attack’s success. The attacks exploiting the Static Current under Laser Illumination (SCuLI attacks) are novel, and their potential has not yet been fully investigated. These attacks can be especially dangerous against cryptographic chips manufactured in downscaling technologies. If such attacks are feasible, appropriate countermeasures have to be proposed in the future.
(62) Horizontal Side-Channel Analysis Attack against Elliptic Curve Scalar Multiplication Accelerator under Laser Illumination
D. Petryk, I. Kabin, P. Langendörfer, Z. Dyka
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963958, (Total Resilience)
(63) SCA Test Results Depend on the Measurement Equipment: Riscure vs. Teledyne LeCroy
D. Petryk, Z. Dyka, P. Langendörfer, I. Kabin
Proc. 3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec 2025), (2025)
(Resilient Systems)
(64) Horizontal Side-Channel Analysis Attack against Elliptic Curve Scalar Multiplication Accelerator under Laser Illumination
D. Petryk, I. Kabin, P. Langendörfer, Z. Dyka
Proc. 26th IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963958, (Resilient Systems)
(65) SCA Test Results Depend on the Measurement Equipment: Riscure vs. Teledyne LeCroy
D. Petryk, Z. Dyka, P. Langendörfer, I. Kabin
Proc. 3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec 2025), (2025)
(Total Resilience)
(66) Vulnerable or Not: SCA Test Results Strongly Depend on the Measurement Equipment
D. Petryk, I. Kabin, Z. Dyka
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Total Resilience)
(67) Vulnerable or Not: SCA Test Results Strongly Depend on the Measurement Equipment
D. Petryk, I. Kabin, Z. Dyka
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Resilient Systems)
(68) Sensitivity of Logic Cells to Laser Fault Injections: An Overview of Experimental Results for IHP Technologies
D. Petryk, P. Langendörfer, Z. Dyka
IEEE Transactions on Device and Materials Reliability 25(3), 410 (2025)
DOI: 10.1109/TDMR.2025.3596380, (Resilient Systems)
In this work, we provide an overview of our front-side Fault Injection (FI) experiments with different logic cells manufactured in two IHP BiCMOS technologies using Riscure equipment for laser FIs. We were able to inject faults into different types of cells including standard library cells as well as into two types of radiation tolerant flip-flops. Experimenting with radiation-tolerant flip-flops faults were injected illuminating areas with PMOS transistors in OFF state. We determined the cells areas, which were sensitive to the laser FI attacks. Only few works discussed this aspect in the past determining NMOS transistors as the sensitive part of the logic cells. Knowledge about the areas which are sensitive to the laser FI attacks can be generalized experimenting with other technologies and used in future by designers to implement corresponding countermeasure(s) at the initial stage of chip development.
(69) Horizontal Attack against EC kP Accelerator under Laser Illumination
D. Petryk, I. Kabin, P. Langendörfer, Z. Dyka
Electronics (MDPI) 14(10), 2072 (2025)
DOI: 10.3390/electronics14102072, (Total Resilience)
Devices employing cryptographic approaches have to be resistant to physical attacks. Side-Channel Analysis (SCA) and Fault Injection (FI) attacks are frequently used to reveal cryptographic keys. In this paper, we present a combined SCA and laser illumination attack against an Elliptic Curve Scalar Multiplication accelerator, while using different equipment for the measurement of its power traces, i.e., we performed the measurements using a current probe from Riscure and a differential probe from Teledyne LeCroy, with an attack success of 70% and 90%, respectively. Our experiments showed that laser illumination increased the power consumption of the chip, especially its static power consumption, but the success of the horizontal power analysis attacks changed insignificantly. After applying 100% of the laser beam output power and illuminating the smallest area of 143 µm2, we observed an offset of 17 mV in the measured trace. We assume that using a laser with a high laser beam power, as well as concentrating on measuring and analysing only static current, can significantly improve the attack’s success. The attacks exploiting the Static Current under Laser Illumination (SCuLI attacks) are novel, and their potential has not yet been fully investigated. These attacks can be especially dangerous against cryptographic chips manufactured in downscaling technologies. If such attacks are feasible, appropriate countermeasures have to be proposed in the future.
(70) Classification of Epileptic Seizures by Simple Machine Learning Techniques: Application to Animals’ Electroencephalography Signals
I. Pidvalnyi, A. Kostenko, O. Sudakov, D. Isaev, O. Maximyuk, O. Krishtal, O. Iegorova, I. Kabin, Z. Dyka, S. Ortmann, P. Langendörfer
IEEE Access 13, 8951 (2025)
DOI: 10.1109/ACCESS.2025.3527866, (DFG-Resilient Systems for Real Time Prediction of Epileptic Seizures)
Detection and prediction of the onset of seizures are among the most challenging problems in epilepsy diagnostics and treatment. Small electronic devices capable of doing that will improve the quality of life for epilepsy patients while also open new opportunities for pharmacological intervention. This paper presents a novel approach using machine learning techniques to detect seizures onset using electroencephalography (EEG) signals. The proposed approach was tested on EEG data recorded in rats with pilocarpine model of temporal lobe epilepsy. A principal component analysis was applied for feature selection before using a support vector machine for the detection of seizures. Hjorth's parameters and Daubechies discrete wavelet transform coefficients were found to be the most informative features of EEG data. We found that the support vector machine approach had a classification sensitivity of 90% and a specificity of 74% for detecting ictal episodes. Changing the epoch parameter from one to twenty-one seconds results in changing the redistribution of principal components’ values to 10% but does not affect the classification result. Support vector machines are accessible and convenient methods for classification that have achieved promising classification quality, and are rather lightweight compared to other machine learning methods. So we suggest their future use in mobile devices for early epileptic seizure and preictal episodes detection.
(71) Classification of Epileptic Seizures by Simple Machine Learning Techniques: Application to Animals’ Electroencephalography Signals
I. Pidvalnyi, A. Kostenko, O. Sudakov, D. Isaev, O. Maximyuk, O. Krishtal, O. Iegorova, I. Kabin, Z. Dyka, S. Ortmann, P. Langendörfer
IEEE Access 13, 8951 (2025)
DOI: 10.1109/ACCESS.2025.3527866, (Total Resilience)
Detection and prediction of the onset of seizures are among the most challenging problems in epilepsy diagnostics and treatment. Small electronic devices capable of doing that will improve the quality of life for epilepsy patients while also open new opportunities for pharmacological intervention. This paper presents a novel approach using machine learning techniques to detect seizures onset using electroencephalography (EEG) signals. The proposed approach was tested on EEG data recorded in rats with pilocarpine model of temporal lobe epilepsy. A principal component analysis was applied for feature selection before using a support vector machine for the detection of seizures. Hjorth's parameters and Daubechies discrete wavelet transform coefficients were found to be the most informative features of EEG data. We found that the support vector machine approach had a classification sensitivity of 90% and a specificity of 74% for detecting ictal episodes. Changing the epoch parameter from one to twenty-one seconds results in changing the redistribution of principal components’ values to 10% but does not affect the classification result. Support vector machines are accessible and convenient methods for classification that have achieved promising classification quality, and are rather lightweight compared to other machine learning methods. So we suggest their future use in mobile devices for early epileptic seizure and preictal episodes detection.
(72) HyRPF: Hybrid RRAM Prototyping on FPGA
D. Reiser, J. Knödtel, L. Almeeva, J. Wen, A. Baroni, M. Krstic, M. Reichenbach
Proc. 24th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2024) in: Lecture Notes in Computer Science, LNCS 15226, 199 (2025)
DOI: 10.1007/978-3-031-78377-7_14
(73) Rate Analysis and Optimization of LoS Beyond Diagonal RIS-Assisted MIMO Systems
I. Santamaria, J. Gutiérrez Teran, M. Soleymani, E. Jorswieck
IEEE Communications Letters 29(6), 1325 (2025)
DOI: 10.1109/LCOMM.2025.3560380, (6G-SENSES)
In this letter, we derive an expression for the achievable rate in a multiple-input multiple-output (MIMO) system assisted by a beyond-diagonal reconfigurable intelligent surface (BD-RIS) when the channels to and from the BD-RIS are line-of-sight (LoS) while the direct link is non-line-of-sight (NLoS). The rate expression allows to derive the optimal unitary and symmetric scattering BD-RIS matrix in closed form. Our simulation results show that the proposed solution is competitive even under the more usual Ricean channel fading model when the direct link is weak.
(74) Interference Minimization in Beyond-Diagonal RIS-assisted MIMO Interference Channels
I. Santamaria, M. Soleymani, E. Jorswieck, J. Gutiérrez Teran
IEEE Open Journal of Vehicular Technology 6, 1005 (2025)
DOI: 10.1109/OJVT.2025.3555425, (6G-SENSES)
This paper proposes a two-stage approach for passive and active beamforming in multiple-input multiple-output (MIMO) interference channels (ICs) assisted by a beyond-diagonal reconfigurable intelligent surface (BD-RIS). In the first stage, the passive BD-RIS is designed to minimize the aggregate interference power at all receivers, a cost function called interference leakage (IL). To this end, we propose an optimization algorithm in the manifold of unitary matrices and a suboptimal but computationally efficient solution. In the second stage, users' active precoders are designed under different criteria such as minimizing the IL (min-IL), maximizing the signal-to-interference-plus-noise ratio (max-SINR), or maximizing the sum rate (max-SR). The residual interference not cancelled by the BD-RIS is treated as noise by the precoders. Our simulation results show that the max-SR precoders provide more than 20% sum rate improvement compared to other designs, especially when the BD-RIS has a moderate number of elements (M<20) and users transmit with high power, in which case the residual interference is still significant.
(75) Impact of Different Antenna Arrangements and Transmitter Tilt to D-Band LoS MIMO Channel
P. Shakya, D. Cvetkovski, K. KrishneGowda, L. Lopancinski, E. Grass
Proc. IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(6G-RIC)
(76) Impact of Different Antenna Arrangements and Transmitter Tilt to D-Band LoS MIMO Channel
P. Shakya, D. Cvetkovski, K. KrishneGowda, L. Lopancinski, E. Grass
Proc. IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(PSSS-FEC)
(77) Enhanced Miss Forest and Multivariate Time Series Prediction of Wind Speed Using Deep Learning
T. Sidhaarth, P.A. Obla, N.N. Patil, Z. Stamenkovic, S.P. Raja
Journal of Circuits, Systems, and Computers (JCSC) 34(12), 2530006 (2025)
DOI: 10.1142/S0218126625300065
As environmental concerns become increasingly serious, renewable energy sources are being prioritized to meet growing demands, among which wind energy stands out as a technologically efficient option. However, the unpredictable nature of offshore wind energy continues to pose challenges for reliable integration into power grids. This study tackles this problem by focusing on improving wind speed prediction by employing a modified Miss Forest algorithm for time series imputation, which achieved the lowest NRMSE: 0.0079, 0.0156 and, 0.0730 among the other imputation methods when compared across three datasets. Alongside the Miss Forest, deep learning models such as Bayesian Optimized Stacked Long Short-Term Memory (BO-SLSTM), Deep Long Short-Term Memory (DLSTM), Gated Recurrent Unit (GRU), Convolutional Neural Network (CNN), and a hybrid Convolutional Long Short-Term Memory (CNN-LSTM) model were applied on real-time wind speed data from an offshore site in Gujarat, India. Furthermore, the Friedman Test was conducted to assess the statistical difference in model performance, yielding a p-value of 0.721, indicating no significant difference among the models. Among the models, the DLSTM demonstrated the best performance solely in terms of the error metrics, while CNN proved to be the most computationally efficient.
(78) Resistance Test Discovered an Inherent Vulnerability of Cryptographic ASICs to Simple SCA
A.A. Sigourou, Z. Dyka, I. Kabin
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Total Resilience)
(79) Resistance Test Discovered an Inherent Vulnerability of Cryptographic ASICs to Simple SCA
A.A. Sigourou, Z. Dyka, I. Kabin
Proc. 37. ITG/GMM/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(Resilient Systems)
(80) Distinguishability between Multiplication and Squaring Operations: A New Marker
A.A. Sigourou, Z. Dyka, P. Langendörfer, I. Kabin
Proc. 3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec 2025), (2025)
(Total Resilience)
(81) Distinguishability between Multiplication and Squaring Operations: A New Marker
A.A. Sigourou, Z. Dyka, P. Langendörfer, I. Kabin
Proc. 3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec 2025), (2025)
(Resilient Systems)
(82) Atomic Patterns: Field Operation Distinguishability on Cryptographic ASICs
A.A. Sigourou, Z. Dyka, P. Langendörfer, I. Kabin
Proc. IEEE International Conference on Cyber Security and Resilience (CSR 2025), 990 (2025)
DOI: 10.1109/CSR64739.2025.11130154, (Total Resilience)
(83) Atomic Patterns: Field Operation Distinguishability on Cryptographic ASICs
A.A. Sigourou, Z. Dyka, P. Langendörfer, I. Kabin
Proc. IEEE International Conference on Cyber Security and Resilience (CSR 2025), 990 (2025)
DOI: 10.1109/CSR64739.2025.11130154, (Resilient Systems)
(84) Revisiting Atomic Patterns for Elliptic Curve Scalar Multiplication Revealing Inherent Vulnerability to Simple SCA
A.A. Sigourou, Z. Dyka, S.H. Li , P. Langendörfer, I. Kabin
Proc. 12th IFIP International Conference on New Technologies, Mobility and Security (NTMS 2025), 252 (2025)
DOI: 10.1109/NTMS65597.2025.11076762, (Total Resilience)
(85) Machine Learning Techniques for Smart Agriculture
Z. Stamenkovic
Proc. 12th International Conference on Electrical, Electronic and Computing Engineering (ICETRAN 2025), 95 (2025)
(86) On-Chip Cross-Layer Sensing for Mission-Mode Monitoring of Resilient Systems: Towards Silicon Lifecycle Management
F. Vargas
Proc. 37. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(87) On-Chip Aging Sensor Core for Silicon Lifecycle Management
F. Vargas, A. Balakrishnan
Proc. IEEE Latin American Test Symposium (LATS 2025), (2025)
DOI: 10.1109/LATS65346.2025.10963953
(88) Self-Aware Silicon: Enhancing Lifecycle Management with Intelligent Testing and Data Insights
F. Vargas, M. Andjelkovic, M. Krstic, A. Kar, S. Deshwal, Y. Chauhan, H. Amrouch, D. Tille, S. Huhn
Proc. 30th IEEE European Test Symposium (ETS 2025), (2025)
DOI: 10.1109/ETS63895.2025.11049649
(89) Particle Filter Localization using a Hybrid Sub-6 GHz and mmWave System
R. Vasist, V. Sark, J. Gutiérrez Teran, E. Grass
Proc. 101st IEEE Vehicular Technology Conference (VTC-Spring 2025), (2025)
(BeGREEN)
(90) A Cross-Layer Methodology for Assessing Silent Data Corruption Effects on DLA Families
A. Veronesi, M. Krstic, D. Bertozzi
Proc. 37. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2025), (2025)
(91) RRAMulator: An Efficient FPGA-based Emulator for RRAM Crossbar with Device Variability and Energy Consumption Evaluation
J. Wen, F. Vargas, F. Zhu, D. Reiser, A. Baroni, M. Fritscher, E. Perez, M. Reichenbach, Ch. Wenger, M. Krstic
Microelectronics Reliability 168, 115630 (2025)
DOI: 10.1016/j.microrel.2025.115630, (6G-RIC)
The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current–voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector–matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.
(92) ReDiM: An Efficient Strategy for Read Disturb Mitigation in RRAM-Based Accelerators
J. Wen, A. Baroni, A. Mistroni, E. Perez, C. Zambelli, Ch. Wenger, M. Krstic, L.M. Bolzani Pöhls
Proc. 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2025), (2025)
DOI: 10.1109/IOLTS65288.2025.11117065, (INSEKT)
(93) ReDiM: An Efficient Strategy for Read Disturb Mitigation in RRAM-Based Accelerators
J. Wen, A. Baroni, A. Mistroni, E. Perez, C. Zambelli, Ch. Wenger, M. Krstic, L.M. Bolzani Pöhls
Proc. 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2025), (2025)
DOI: 10.1109/IOLTS65288.2025.11117065, (6G-RIC)
(94) ImSTDP: Implicit Timing On-Chip STDP Learning
D. Zhao, O. Schrape, Z. Stamenkovic, M. Krstic
IEEE Transactions on Circuits and Systems I 72(2), 868 (2025)
DOI: 10.1109/TCSI.2024.3450958
Spike-Timing-Dependent Plasticity (STDP) is a biological-plausible learning mechanism widely adopted for building Spiking Neural Networks (SNNs). It determines plasticity polarity and synapse strength change according to the timing difference between pre-and postsynaptic spikes. The learning curves of STDP differ in temporal window size, magnitude and polarity across different synapse types and brain regions and even within a cell, in different dendritic compartments. To accelerate on-chip STDP learning, various implementations have been proposed. However, they either introduce significant latency due to costly counter-based time difference calculation and substantial area cost due to the implementation of weight change LUTs, or lose biologically-plausible timing information due to oversimplification. For low-cost and efficient on-chip learning, a high-throughput Implicit-timing STDP (ImSTDP) with optimized SR depth and a low-cost register-based Implicit-Timing Look-up (ITL) are proposed. ASIC implementation in 22 nm technology demonstrates that ImSTDP can achieve up to 2 × throughput improvement and 3.61 × power efficiency improvement at 27% less area cost compared to the cutting-edge counter-LUT on-chip STDP learning solution.
