Script list Publications
(1) Wave Digital Emulation of an Enhanced Compact Model for RRAM Devices with Multilevel Capability
B. Al Beattie, E. Perez-Bosch Quesada, M. Uhlmann, E. Perez, G. Kahmen, E. Solan, K. Ochs
IEEE Transactions on Nanotechnology 22, 753 (2023)
DOI: 10.1109/TNANO.2023.3328821, (KI-PRO)
The reliable and compact modeling of RRAM devices is crucial for supporting the development of novel technologies including them. The latter includes a wide range of applications, such as in-memory computing in neuromorphic networks or memristive logic. A major advantage of the considered HfO2-based RRAM devices is their CMOS-compatibility, which allows them to already be utilized in present applications. However, one problem with RRAMs is that their fabrication still leads to device variabilities. This makes it challenging to test the functionality of aspiring technologies utilizing them in an experimental fashion.
This work is dedicated to the compact modeling and efficient emulation of 1T-1R RRAM devices. Specifically, we aim to provide an enhanced model, based on the Stanford-PKU model, that can be used on any simulation platform such as SPICE, VERLIOGA, or even standard ODE solvers to simulate multilevel capable RRAM devices. Furthermore, we provide an algorithmic model, based on the wave digital concept, which allows for emulating the considered RRAM device in real-time. Using the latter, we show the hysteresis of our enhanced model to exhibit astounding resemblance with real device measurements.
(2) Wave Digital Emulation of an Enhanced Compact Model for RRAM Devices with Multilevel Capability
B. Al Beattie, E. Perez-Bosch Quesada, M. Uhlmann, E. Perez, G. Kahmen, E. Solan, K. Ochs
IEEE Transactions on Nanotechnology 22, 753 (2023)
DOI: 10.1109/TNANO.2023.3328821, (KI-IoT)
The reliable and compact modeling of RRAM devices is crucial for supporting the development of novel technologies including them. The latter includes a wide range of applications, such as in-memory computing in neuromorphic networks or memristive logic. A major advantage of the considered HfO2-based RRAM devices is their CMOS-compatibility, which allows them to already be utilized in present applications. However, one problem with RRAMs is that their fabrication still leads to device variabilities. This makes it challenging to test the functionality of aspiring technologies utilizing them in an experimental fashion.
This work is dedicated to the compact modeling and efficient emulation of 1T-1R RRAM devices. Specifically, we aim to provide an enhanced model, based on the Stanford-PKU model, that can be used on any simulation platform such as SPICE, VERLIOGA, or even standard ODE solvers to simulate multilevel capable RRAM devices. Furthermore, we provide an algorithmic model, based on the wave digital concept, which allows for emulating the considered RRAM device in real-time. Using the latter, we show the hysteresis of our enhanced model to exhibit astounding resemblance with real device measurements.
(3) Wave Digital Emulation of an Enhanced Compact Model for RRAM Devices with Multilevel Capability
B. Al Beattie, E. Perez-Bosch Quesada, M. Uhlmann, E. Perez, G. Kahmen, E. Solan, K. Ochs
IEEE Transactions on Nanotechnology 22, 753 (2023)
DOI: 10.1109/TNANO.2023.3328821, (MIMEC)
The reliable and compact modeling of RRAM devices is crucial for supporting the development of novel technologies including them. The latter includes a wide range of applications, such as in-memory computing in neuromorphic networks or memristive logic. A major advantage of the considered HfO2-based RRAM devices is their CMOS-compatibility, which allows them to already be utilized in present applications. However, one problem with RRAMs is that their fabrication still leads to device variabilities. This makes it challenging to test the functionality of aspiring technologies utilizing them in an experimental fashion.
This work is dedicated to the compact modeling and efficient emulation of 1T-1R RRAM devices. Specifically, we aim to provide an enhanced model, based on the Stanford-PKU model, that can be used on any simulation platform such as SPICE, VERLIOGA, or even standard ODE solvers to simulate multilevel capable RRAM devices. Furthermore, we provide an algorithmic model, based on the wave digital concept, which allows for emulating the considered RRAM device in real-time. Using the latter, we show the hysteresis of our enhanced model to exhibit astounding resemblance with real device measurements.
(4) Polarization-Tuned Fano Resonances in All-Dielectric Short-Wave Infrared Metasurface
A. Attiaoui, G. Daligou, S. Assali, O. Skibitzki, T. Schroeder, O. Moutanabbir
Advanced Materials 35(28), 2300595 (2023)
DOI: 10.1002/adma.202300595, (NHEQuanLEA)
The short-wave infrared (SWIR) is an underexploited portion of the electromagnetic spectrum in metasurface-based nanophotonics despite its strategic importance in sensing and imaging applications. This is mainly attributed to the lack of material systems to tailor light-matter interactions in this range. Herein, we address this limitation and demonstrate an all-dielectric silicon-integrated metasurface enabling polarization-induced Fano resonance control at SWIR frequencies. The platform consists of a two-dimensional Si/Ge0.9Sn0.1 core/shell nanowire array on a silicon wafer. By tuning the light polarization, we show that the metasurface reflectance can be efficiently engineered due to Fano resonances emerging from the electric and magnetic dipoles competition. The interference of optically induced dipoles in high-index nanowire arrays offers additional degrees of freedom to tailor the directional scattering and the flow of light while enabling sharp polarization-modulated resonances. This tunablity is harnessed in nanosensors yielding an efficient detection of 10−2 changes in the refractive index of the surrounding medium.
(5) Structural and Electrical Characterization of Cerium-Tin Oxide Heterolayers for Hydrogen Sensing
C.A. Chavarin, I. Costina, Ch. Wenger, M. Ratzke, C. Morales Sanchez, Y. Kosto, I. Flege, I.A. Fischer
Proc. 10. MikroSystemTechnik Kongress (MST 2023), 1 (2023)
(iCampus II)
(6) Efficient Circuit Simulation of a Memristive Crossbar Array with Synaptic Weight Variability
N. Dersch, E. Perez-Bosch Quesada, E. Perez, Ch. Wenger, Ch. Roemer, M. Schwarz, A. Kloes
Solid-State Electronics 209, 108760 (2023)
DOI: 10.1016/j.sse.2023.108760, (KI-IoT)
In this paper, we present a method for highly-efficient circuit simulation of a hardware-based artificial neural network realized in a memristive crossbar array. The statistical variability of the devices is considered by a noise-based simulation technique. For the simulation of a crossbar array with 8 synaptic weights in Cadence Virtuoso the new approach shows a more than 200x speed improvement compared to a Monte Carlo approach, yielding the same results. In addition, first results of an ANN with more than 15000 memristive devices classifying test data of the MNIST dataset are shown, for which the speed improvement is expected to be several orders of magnitude. Furthermore, the influence on the classification of parasitic resistances of the connection lines in the crossbar is shown.
(7) A RRAM Characterization System with Flexible Readout Operations using an Integrating ADC
R. Jia, S. Pechmann, A. Baroni, Ch. Wenger, A. Hagelauer
Proc. 18th International Conference on PhD Research in Microelectronics and Electronics (PRIME 2023), 245 (2023)
DOI: 10.1109/PRIME58259.2023.10161880, (MIMEC)
(8) Monolithic Integration of InP Nanowires with CMOS Fabricated Silicon Nanotips Wafer
A. Kamath, O. Skibitzki, D. Spirito, S. Dadgostar, I.M. Martinez, M. Schmidbauer, C. Richter, A. Kwasniewski, J. Serrano, J. Jimenez, C. Golz, M.A. Schubert, J.W. Tomm, N. Gang, F. Hatami
Physical Review Materials 7(10), 103801 (2023)
DOI: 10.1103/PhysRevMaterials.7.103801, (NHEQuanLEA)
The integration of both optical and electronic components on a single chip, despite several challenges, holds the promise of compatibility with complementary metal-oxide semiconductor (CMOS) technology and high scalability. Among all candidate materials, III-V semiconductors exhibit great potential for optoelectronics and quantum-optics based devices, such as light emitters and harvesters. The control over geometry, and dimensionality of the III-V nanostructures, enables one to modify the band structures, and hence provide a powerful tool for tailoring the optoelectronic properties of III-V compounds. One of the most creditable approaches towards such growth control is the combination of using a patterned wafer and the self-assembled epitaxy. This work presents monolithically integrated catalyst-free InP nanowires grown selectively on Si nanotip-patterned, CMOS compatible (001) Si substrates using gas-source molecular-beam epitaxy. We use nanoheteroepitaxy approach to selectively grow InP nanowires on Si nanotips, which holds benefits due to its peculiar substrate design. In addition, our methodology allows the switching of dimensionality of the InP structures between one-dimensional nanowires and three-dimensional bulklike InP nanoislands by thermally modifying the shape of silicon nanotips surrounded by the silicon dioxide layer during the thermal cleaning of the substrate. The structural and optical characterization of nanowires indicates the coexistence of both zincblende and wurtzite InP crystal phases in nanowires. The two different crystal structures were aligned with a type-II band alignment. The luminescence from InP nanowires was measured up to 300 K, which reveals their promising optical quality for integrated photonics and optoelectronic applications.
(9) Investigation of the Impact of Amorphous Silicon Layers Deposited by PECVD and HDP-CVD on Oxide Precipitation in Silicon
G. Kissinger, D. Kot, F. Bärwolf, M. Lisker
Materials Science in Semiconductor Processing 164, 107614 (2023)
DOI: 10.1016/j.mssp.2023.107614, (Future Silicon Wafers)
The effect of deposited a-Si layers with different layer stress on oxide precipitation was investigated in order to find out if intrinsic point defects affecting oxide precipitation are generated at the interface a-Si/Si and if possibly hydrogen affects the oxide precipitation. A thermal cycle of nucleation at 650 °C for 4 h or 8 h followed by stabilization at 780 °C for 3 h, and growth at 1000 °C for 16 h was applied. It was found that there are no signs for the injection of intrinsic point defects from the interface a-Si/Si into the Si substrate during the applied thermal treatment. However if a-Si is deposited on 1000 nm silicon oxide, deposited previously from TEOS in a plasma process, silicon self-interstitials seem to be injected from the interface silicon oxide/Si into the silicon substrate retarding oxide precipitation in the initial stage of nucleation annealing at 650 °C. There are also no signs of any impact of the layer stress on oxide precipitation or self-interstitial injection. The concentration of hydrogen in the layers can be controlled via the RF bias power. The hydrogen concentration is reduced markedly already during annealing at 650 °C. Part of the hydrogen diffuses into the silicon substrate and enhances oxide precipitation if its initial concentration in the layers is higher than 1.5 × 1022 cm−3. For a-Si deposited on 1000 nm silicon oxide, the enhancement effect appears for hydrogen concentrations in the layer higher than approximately 2.8 × 1022 cm−3.
(10) Stochastic Switching of Memristors and Consideration in Circuit Simulation
A. Kloes, C. Bischoff, J. Leise, E. Perez-Bosch Quesada, Ch. Wenger, E. Perez
Solid State Electronics 201, 108606 (2023)
DOI: 10.1016/j.sse.2022.108321, (KI-IoT)
We explore the stochastic switching of oxide-based memristive devices by using the Stanford model for circuit simulation. From measurements, the device-to-device (D2D) and cycle-to-cycle (C2C) statistical variation is extracted. In the low-resistive state (LRS) dispersion by D2D variability is dominant. In the high-resistive state (HRS) C2C dispersion becomes the main source of fluctuation. A statistical procedure for the extraction of parameters of the compact model is presented. Thereby, in a circuit simulation the typical D2D and C2C fluctuations of the current-voltage (I-V) characteristics can be emulated by extracting statistical parameters of key model parameters. The statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of memory cells or can be used to emulate the synaptic behavior of these devices in artificial neural networks realized by a crossbar array of memristors.
(11) AC Electrokinetic Immobilization of Single Biomolecules on Nano-Electrode Arrays
X. Knigge, Ch. Wenger, F.F. Bier, R. Hölzel
Proc. 4th European Biosensor Symposium (EBS 2023), 109 (2023)
(12) TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance
D. Maldonado, A. Cantudo, E. Perez, R. Romero-Zaliz, E. Perez-Bosch Quesada, M.K. Mahadevaiah, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Frontiers in Neuroscience 17, 1271956 (2023)
DOI: 10.3389/fnins.2023.1271956, (KI-IoT)
We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.
(13) Strain Engineered Electrically Pumped SiGeSn Microring Lasers on Si
B. Marzban, L. Seidel, T. Liu, K. Wu, V. Kiyek, M.H. Zoellner, Z. Ikonic, J. Schulze, D. Grützmacher, G. Capellini, M. Oehme, J. Witzens, D. Buca
ACS Photonics 10(1), 217 (2023)
DOI: 10.1021/acsphotonics.2c01508, (DFG GeSn Laser)
SiGeSn holds great promise for enabling fully group-IV integrated photonics operating at wavelengths extending in the mid-infrared range. Here, we demonstrate an electrically pumped GeSn microring laser based on SiGeSn/GeSn heterostructures. The ring shape allows for enhanced strain relaxation, leading to enhanced optical properties, and better guiding of the carriers into the optically active region. We have engineered a partial undercut of the ring to further promote strain relaxation while maintaining adequate heat sinking. Lasing is measured up to 90 K, with a 75 K T0. Scaling of the threshold current density as the inverse of the outer circumference is linked to optical losses at the etched surface, limiting device performance. Modeling is consistent with experiments across the range of explored inner and outer radii. These results will guide additional device optimization, aiming at improving electrical injection and using stressors to increase the bandgap directness of the active material.
(14) Combination of Multiple Operando and In-Situ Characterization Techniques in a Single Cluster System for Atomic Layer Deposition: Unraveling the Early Stages of Growth of Ultrathin Al2O3 Films on Metallic Ti Substrates
C. Morales, A. Mahmoodinezhad, R. Tschammer, J. Kosto, C.A. Chavarin, M.A. Schubert, Ch. Wenger, K. Henkel, J.I. Flege
Inorganics 11(12), 477 (2023)
DOI: 10.3390/inorganics11120477, (iCampus II)
This work presents a new ultra-high vacuum cluster tool to perform systematic studies of the early growth stages of atomic layer deposited (ALD) ultrathin films following a surface science approach. By combining operando (spectroscopic ellipsometry and quadrupole mass spectroscopy) and in-situ (X-ray photoelectron spectroscopy) characterization techniques, the cluster allows to follow the evolution of substrate, film, and intermediate states as a function of the total number of ALD cycles, as well as perform a constant diagnosis and evaluation of the ALD process, detecting possible malfunctions that could affect the growth, reproducibility, and conclusions derived from data analysis. Besides, the home-made ALD reactor allows the use of multiple precursors and oxidants and its operation under pump- and flow-type modes. To illustrate our experimental approach, we revisit the well-known thermal ALD growth of Al2O3 using trimethylaluminum and water. We deeply discuss the role of the metallic Ti thin film substrate at room temperature and 200 °C, highlighting the differences between the hetero-deposition (< 10 cycles) and the homo-deposition (> 10 cycles) growth regimes at both conditions. This surface science approach will benefit our understanding of the ALD process, paving the way towards more efficient and controllable manufacturing processes.
(15) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (MIMEC)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(16) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (KI-PRO)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(17) Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing
E. Perez-Bosch Quesada, T. Rizzi, A. Gupta, M.K Mahadevaiah, M.A. Schubert, S. Pechmann, R. Jia, M. Uhlmann, A. Hagelauer, Ch. Wenger, E. Perez
Proc. 14th Spanish Conference on Electron Devices (CDE 2023), (2023)
DOI: 10.1109/CDE58627.2023.10339525, (MIMEC)
(18) A Comparison of Resistive Switching Parameters for Memristive Devices with HfO2 Monolayers and Al2O3/HfO2 Bilayers at the Wafer Scale
E. Perez, D. Maldonado, M.K. Mahadevaiah, E. Perez-Bosch Quesada, A. Cantudo, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Proc. 14th Spanish Conference on Electron Devices (CDE 2023), (2023)
DOI: 10.1109/CDE58627.2023.10339417, (KI-IoT)
(19) Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale
E. Perez, D. Maldonado, E. Perez-Bosch Quesada, M.K. Mahadevaiah, F. Jimenez-Molinos, Ch. Wenger, J.B. Rodan
IEEE Transactions on Electron Devices 70(1), 360 (2023)
DOI: 10.1109/TED.2021.3072868, (KI-IoT)
The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.
(20) Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations
D. Reiser, M. Reichenbach, T. Rizzi, A. Baroni, M. Fritscher, Ch. Wenger, C. Zambelli, D. Bertozzi
Proc. 21st IEEE Interregional New Circuits And Systems Conference (NEWCAS 2023), (2023)
DOI: 10.1109/NEWCAS57931.2023.10198076
(21) Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-based FPGAs
T. Rizzi, A. Baroni, A. Glukhov, D. Bertozzi, Ch. Wenger, D. Ielmini, C. Zambelli
IEEE Transactions on Device and Materials Reliability 23(3), 328 (2023)
DOI: 10.1109/TDMR.2023.3259015
Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations.
(22) Exploring the NBTI Aging and PVT Effects on RRAM-based FPGA Multiplexers Performance
T. Rizzi, A. Baroni, D. Bertozzi, Ch. Wenger, D. Ielmini, C. Zambelli
Proc. IEEE International Integrated Reliability Workshop (IIRW 2023), (2023)
(MIMEC)
(23) Selective Epitaxy of Germanium by Reduced Pressure Chemical Vapor Deposition: Effect of Area Growth Size on Morphology, Strain, and Optical Emission
D. Ryzhak, A.A. Corley-Wiciak, P. Steglich, Y. Yamamoto, J. Frigerio, D. Spirito, G. Capellini
Proc. 14th International WorkShop on New Group IV Semiconductor Nanoelectronics (El4GroupIV 2023), 27 (2023)
(VISIR2)
(24) AC Field Assisted Deposition of Influenza Viruses on Nanoelectrodes
S. Stanke, Ch. Wenger, F.F. Bier, R. Hölzel
Proc. 4th European Biosensor Symposium (EBS 2023), 160 (2023)
(25) Redox-Based Bi-Layer Metal Oxide Memristive Devices
F. Zahari, S. Park, M.K. Mahadevaiah, Ch. Wenger, H. Kohlstedt, M. Ziegler
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Redox-Based Bi-Layer Metal Oxide Memristive Devices, Springer Series on Bio- and Neurosystems (SSBN) 16, Springer, 87 (2023)
DOI: 10.1007/978-3-031-36705-2_3, (NeuroMem)
(26) Neuromorphic Circuits with Redox-Based Memristive Devices
F. Zahari, M. Ziegler, P. Doerwald, Ch. Wenger, H. Kohlstedt
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Redox-Based Bi-Layer Metal Oxide Memristive Devices, Springer Series on Bio- and Neurosystems (SSBN) 16, Springer, 43 (2023)
DOI: 10.1007/978-3-031-36705-2_2, (NeuroMem)
B. Al Beattie, E. Perez-Bosch Quesada, M. Uhlmann, E. Perez, G. Kahmen, E. Solan, K. Ochs
IEEE Transactions on Nanotechnology 22, 753 (2023)
DOI: 10.1109/TNANO.2023.3328821, (KI-PRO)
The reliable and compact modeling of RRAM devices is crucial for supporting the development of novel technologies including them. The latter includes a wide range of applications, such as in-memory computing in neuromorphic networks or memristive logic. A major advantage of the considered HfO2-based RRAM devices is their CMOS-compatibility, which allows them to already be utilized in present applications. However, one problem with RRAMs is that their fabrication still leads to device variabilities. This makes it challenging to test the functionality of aspiring technologies utilizing them in an experimental fashion.
This work is dedicated to the compact modeling and efficient emulation of 1T-1R RRAM devices. Specifically, we aim to provide an enhanced model, based on the Stanford-PKU model, that can be used on any simulation platform such as SPICE, VERLIOGA, or even standard ODE solvers to simulate multilevel capable RRAM devices. Furthermore, we provide an algorithmic model, based on the wave digital concept, which allows for emulating the considered RRAM device in real-time. Using the latter, we show the hysteresis of our enhanced model to exhibit astounding resemblance with real device measurements.
(2) Wave Digital Emulation of an Enhanced Compact Model for RRAM Devices with Multilevel Capability
B. Al Beattie, E. Perez-Bosch Quesada, M. Uhlmann, E. Perez, G. Kahmen, E. Solan, K. Ochs
IEEE Transactions on Nanotechnology 22, 753 (2023)
DOI: 10.1109/TNANO.2023.3328821, (KI-IoT)
The reliable and compact modeling of RRAM devices is crucial for supporting the development of novel technologies including them. The latter includes a wide range of applications, such as in-memory computing in neuromorphic networks or memristive logic. A major advantage of the considered HfO2-based RRAM devices is their CMOS-compatibility, which allows them to already be utilized in present applications. However, one problem with RRAMs is that their fabrication still leads to device variabilities. This makes it challenging to test the functionality of aspiring technologies utilizing them in an experimental fashion.
This work is dedicated to the compact modeling and efficient emulation of 1T-1R RRAM devices. Specifically, we aim to provide an enhanced model, based on the Stanford-PKU model, that can be used on any simulation platform such as SPICE, VERLIOGA, or even standard ODE solvers to simulate multilevel capable RRAM devices. Furthermore, we provide an algorithmic model, based on the wave digital concept, which allows for emulating the considered RRAM device in real-time. Using the latter, we show the hysteresis of our enhanced model to exhibit astounding resemblance with real device measurements.
(3) Wave Digital Emulation of an Enhanced Compact Model for RRAM Devices with Multilevel Capability
B. Al Beattie, E. Perez-Bosch Quesada, M. Uhlmann, E. Perez, G. Kahmen, E. Solan, K. Ochs
IEEE Transactions on Nanotechnology 22, 753 (2023)
DOI: 10.1109/TNANO.2023.3328821, (MIMEC)
The reliable and compact modeling of RRAM devices is crucial for supporting the development of novel technologies including them. The latter includes a wide range of applications, such as in-memory computing in neuromorphic networks or memristive logic. A major advantage of the considered HfO2-based RRAM devices is their CMOS-compatibility, which allows them to already be utilized in present applications. However, one problem with RRAMs is that their fabrication still leads to device variabilities. This makes it challenging to test the functionality of aspiring technologies utilizing them in an experimental fashion.
This work is dedicated to the compact modeling and efficient emulation of 1T-1R RRAM devices. Specifically, we aim to provide an enhanced model, based on the Stanford-PKU model, that can be used on any simulation platform such as SPICE, VERLIOGA, or even standard ODE solvers to simulate multilevel capable RRAM devices. Furthermore, we provide an algorithmic model, based on the wave digital concept, which allows for emulating the considered RRAM device in real-time. Using the latter, we show the hysteresis of our enhanced model to exhibit astounding resemblance with real device measurements.
(4) Polarization-Tuned Fano Resonances in All-Dielectric Short-Wave Infrared Metasurface
A. Attiaoui, G. Daligou, S. Assali, O. Skibitzki, T. Schroeder, O. Moutanabbir
Advanced Materials 35(28), 2300595 (2023)
DOI: 10.1002/adma.202300595, (NHEQuanLEA)
The short-wave infrared (SWIR) is an underexploited portion of the electromagnetic spectrum in metasurface-based nanophotonics despite its strategic importance in sensing and imaging applications. This is mainly attributed to the lack of material systems to tailor light-matter interactions in this range. Herein, we address this limitation and demonstrate an all-dielectric silicon-integrated metasurface enabling polarization-induced Fano resonance control at SWIR frequencies. The platform consists of a two-dimensional Si/Ge0.9Sn0.1 core/shell nanowire array on a silicon wafer. By tuning the light polarization, we show that the metasurface reflectance can be efficiently engineered due to Fano resonances emerging from the electric and magnetic dipoles competition. The interference of optically induced dipoles in high-index nanowire arrays offers additional degrees of freedom to tailor the directional scattering and the flow of light while enabling sharp polarization-modulated resonances. This tunablity is harnessed in nanosensors yielding an efficient detection of 10−2 changes in the refractive index of the surrounding medium.
(5) Structural and Electrical Characterization of Cerium-Tin Oxide Heterolayers for Hydrogen Sensing
C.A. Chavarin, I. Costina, Ch. Wenger, M. Ratzke, C. Morales Sanchez, Y. Kosto, I. Flege, I.A. Fischer
Proc. 10. MikroSystemTechnik Kongress (MST 2023), 1 (2023)
(iCampus II)
(6) Efficient Circuit Simulation of a Memristive Crossbar Array with Synaptic Weight Variability
N. Dersch, E. Perez-Bosch Quesada, E. Perez, Ch. Wenger, Ch. Roemer, M. Schwarz, A. Kloes
Solid-State Electronics 209, 108760 (2023)
DOI: 10.1016/j.sse.2023.108760, (KI-IoT)
In this paper, we present a method for highly-efficient circuit simulation of a hardware-based artificial neural network realized in a memristive crossbar array. The statistical variability of the devices is considered by a noise-based simulation technique. For the simulation of a crossbar array with 8 synaptic weights in Cadence Virtuoso the new approach shows a more than 200x speed improvement compared to a Monte Carlo approach, yielding the same results. In addition, first results of an ANN with more than 15000 memristive devices classifying test data of the MNIST dataset are shown, for which the speed improvement is expected to be several orders of magnitude. Furthermore, the influence on the classification of parasitic resistances of the connection lines in the crossbar is shown.
(7) A RRAM Characterization System with Flexible Readout Operations using an Integrating ADC
R. Jia, S. Pechmann, A. Baroni, Ch. Wenger, A. Hagelauer
Proc. 18th International Conference on PhD Research in Microelectronics and Electronics (PRIME 2023), 245 (2023)
DOI: 10.1109/PRIME58259.2023.10161880, (MIMEC)
(8) Monolithic Integration of InP Nanowires with CMOS Fabricated Silicon Nanotips Wafer
A. Kamath, O. Skibitzki, D. Spirito, S. Dadgostar, I.M. Martinez, M. Schmidbauer, C. Richter, A. Kwasniewski, J. Serrano, J. Jimenez, C. Golz, M.A. Schubert, J.W. Tomm, N. Gang, F. Hatami
Physical Review Materials 7(10), 103801 (2023)
DOI: 10.1103/PhysRevMaterials.7.103801, (NHEQuanLEA)
The integration of both optical and electronic components on a single chip, despite several challenges, holds the promise of compatibility with complementary metal-oxide semiconductor (CMOS) technology and high scalability. Among all candidate materials, III-V semiconductors exhibit great potential for optoelectronics and quantum-optics based devices, such as light emitters and harvesters. The control over geometry, and dimensionality of the III-V nanostructures, enables one to modify the band structures, and hence provide a powerful tool for tailoring the optoelectronic properties of III-V compounds. One of the most creditable approaches towards such growth control is the combination of using a patterned wafer and the self-assembled epitaxy. This work presents monolithically integrated catalyst-free InP nanowires grown selectively on Si nanotip-patterned, CMOS compatible (001) Si substrates using gas-source molecular-beam epitaxy. We use nanoheteroepitaxy approach to selectively grow InP nanowires on Si nanotips, which holds benefits due to its peculiar substrate design. In addition, our methodology allows the switching of dimensionality of the InP structures between one-dimensional nanowires and three-dimensional bulklike InP nanoislands by thermally modifying the shape of silicon nanotips surrounded by the silicon dioxide layer during the thermal cleaning of the substrate. The structural and optical characterization of nanowires indicates the coexistence of both zincblende and wurtzite InP crystal phases in nanowires. The two different crystal structures were aligned with a type-II band alignment. The luminescence from InP nanowires was measured up to 300 K, which reveals their promising optical quality for integrated photonics and optoelectronic applications.
(9) Investigation of the Impact of Amorphous Silicon Layers Deposited by PECVD and HDP-CVD on Oxide Precipitation in Silicon
G. Kissinger, D. Kot, F. Bärwolf, M. Lisker
Materials Science in Semiconductor Processing 164, 107614 (2023)
DOI: 10.1016/j.mssp.2023.107614, (Future Silicon Wafers)
The effect of deposited a-Si layers with different layer stress on oxide precipitation was investigated in order to find out if intrinsic point defects affecting oxide precipitation are generated at the interface a-Si/Si and if possibly hydrogen affects the oxide precipitation. A thermal cycle of nucleation at 650 °C for 4 h or 8 h followed by stabilization at 780 °C for 3 h, and growth at 1000 °C for 16 h was applied. It was found that there are no signs for the injection of intrinsic point defects from the interface a-Si/Si into the Si substrate during the applied thermal treatment. However if a-Si is deposited on 1000 nm silicon oxide, deposited previously from TEOS in a plasma process, silicon self-interstitials seem to be injected from the interface silicon oxide/Si into the silicon substrate retarding oxide precipitation in the initial stage of nucleation annealing at 650 °C. There are also no signs of any impact of the layer stress on oxide precipitation or self-interstitial injection. The concentration of hydrogen in the layers can be controlled via the RF bias power. The hydrogen concentration is reduced markedly already during annealing at 650 °C. Part of the hydrogen diffuses into the silicon substrate and enhances oxide precipitation if its initial concentration in the layers is higher than 1.5 × 1022 cm−3. For a-Si deposited on 1000 nm silicon oxide, the enhancement effect appears for hydrogen concentrations in the layer higher than approximately 2.8 × 1022 cm−3.
(10) Stochastic Switching of Memristors and Consideration in Circuit Simulation
A. Kloes, C. Bischoff, J. Leise, E. Perez-Bosch Quesada, Ch. Wenger, E. Perez
Solid State Electronics 201, 108606 (2023)
DOI: 10.1016/j.sse.2022.108321, (KI-IoT)
We explore the stochastic switching of oxide-based memristive devices by using the Stanford model for circuit simulation. From measurements, the device-to-device (D2D) and cycle-to-cycle (C2C) statistical variation is extracted. In the low-resistive state (LRS) dispersion by D2D variability is dominant. In the high-resistive state (HRS) C2C dispersion becomes the main source of fluctuation. A statistical procedure for the extraction of parameters of the compact model is presented. Thereby, in a circuit simulation the typical D2D and C2C fluctuations of the current-voltage (I-V) characteristics can be emulated by extracting statistical parameters of key model parameters. The statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of memory cells or can be used to emulate the synaptic behavior of these devices in artificial neural networks realized by a crossbar array of memristors.
(11) AC Electrokinetic Immobilization of Single Biomolecules on Nano-Electrode Arrays
X. Knigge, Ch. Wenger, F.F. Bier, R. Hölzel
Proc. 4th European Biosensor Symposium (EBS 2023), 109 (2023)
(12) TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance
D. Maldonado, A. Cantudo, E. Perez, R. Romero-Zaliz, E. Perez-Bosch Quesada, M.K. Mahadevaiah, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Frontiers in Neuroscience 17, 1271956 (2023)
DOI: 10.3389/fnins.2023.1271956, (KI-IoT)
We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.
(13) Strain Engineered Electrically Pumped SiGeSn Microring Lasers on Si
B. Marzban, L. Seidel, T. Liu, K. Wu, V. Kiyek, M.H. Zoellner, Z. Ikonic, J. Schulze, D. Grützmacher, G. Capellini, M. Oehme, J. Witzens, D. Buca
ACS Photonics 10(1), 217 (2023)
DOI: 10.1021/acsphotonics.2c01508, (DFG GeSn Laser)
SiGeSn holds great promise for enabling fully group-IV integrated photonics operating at wavelengths extending in the mid-infrared range. Here, we demonstrate an electrically pumped GeSn microring laser based on SiGeSn/GeSn heterostructures. The ring shape allows for enhanced strain relaxation, leading to enhanced optical properties, and better guiding of the carriers into the optically active region. We have engineered a partial undercut of the ring to further promote strain relaxation while maintaining adequate heat sinking. Lasing is measured up to 90 K, with a 75 K T0. Scaling of the threshold current density as the inverse of the outer circumference is linked to optical losses at the etched surface, limiting device performance. Modeling is consistent with experiments across the range of explored inner and outer radii. These results will guide additional device optimization, aiming at improving electrical injection and using stressors to increase the bandgap directness of the active material.
(14) Combination of Multiple Operando and In-Situ Characterization Techniques in a Single Cluster System for Atomic Layer Deposition: Unraveling the Early Stages of Growth of Ultrathin Al2O3 Films on Metallic Ti Substrates
C. Morales, A. Mahmoodinezhad, R. Tschammer, J. Kosto, C.A. Chavarin, M.A. Schubert, Ch. Wenger, K. Henkel, J.I. Flege
Inorganics 11(12), 477 (2023)
DOI: 10.3390/inorganics11120477, (iCampus II)
This work presents a new ultra-high vacuum cluster tool to perform systematic studies of the early growth stages of atomic layer deposited (ALD) ultrathin films following a surface science approach. By combining operando (spectroscopic ellipsometry and quadrupole mass spectroscopy) and in-situ (X-ray photoelectron spectroscopy) characterization techniques, the cluster allows to follow the evolution of substrate, film, and intermediate states as a function of the total number of ALD cycles, as well as perform a constant diagnosis and evaluation of the ALD process, detecting possible malfunctions that could affect the growth, reproducibility, and conclusions derived from data analysis. Besides, the home-made ALD reactor allows the use of multiple precursors and oxidants and its operation under pump- and flow-type modes. To illustrate our experimental approach, we revisit the well-known thermal ALD growth of Al2O3 using trimethylaluminum and water. We deeply discuss the role of the metallic Ti thin film substrate at room temperature and 200 °C, highlighting the differences between the hetero-deposition (< 10 cycles) and the homo-deposition (> 10 cycles) growth regimes at both conditions. This surface science approach will benefit our understanding of the ALD process, paving the way towards more efficient and controllable manufacturing processes.
(15) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (MIMEC)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(16) Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
E. Perez-Bosch Quesada, M.K Mahadevaiah, T. Rizzi, J. Wen, M. Ulbricht, M. Krstic, Ch. Wenger, E. Perez
IEEE Transactions on Electron Devices 70(4), 2009 (2023)
DOI: 10.1109/TED.2023.3244509, (KI-PRO)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing systems for artificial intelligence applications. RRAM technology enables parallel vector-matrix multiplication (VMM) operations performed during the inference phase of artificial neural networks, setting the resistive state of the devices as synaptic weights within the neural network. The stochastic nature of such technology must be taken into consideration in order to minimize the accuracy degradation due to undesirable resistive changes after a certain number of operations. In this study, we program two different RRAM sub-arrays composed by 8-by-8 one-transistor-one resistor (1T1R) cells following two different distributions of conductive levels and we analyze their robustness during 1000 consecutive VMM operations. The resistance of the devices under study is monitored during the whole experiment and we could observe different resistive drift/relaxation phenomena that degrades the accuracy of the operations. The trade-off between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities is evaluated in both, analog and digital domain for future implementation of in-memory computing hardware systems.
(17) Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing
E. Perez-Bosch Quesada, T. Rizzi, A. Gupta, M.K Mahadevaiah, M.A. Schubert, S. Pechmann, R. Jia, M. Uhlmann, A. Hagelauer, Ch. Wenger, E. Perez
Proc. 14th Spanish Conference on Electron Devices (CDE 2023), (2023)
DOI: 10.1109/CDE58627.2023.10339525, (MIMEC)
(18) A Comparison of Resistive Switching Parameters for Memristive Devices with HfO2 Monolayers and Al2O3/HfO2 Bilayers at the Wafer Scale
E. Perez, D. Maldonado, M.K. Mahadevaiah, E. Perez-Bosch Quesada, A. Cantudo, F. Jimenez-Molinos, Ch. Wenger, J.B. Roldan
Proc. 14th Spanish Conference on Electron Devices (CDE 2023), (2023)
DOI: 10.1109/CDE58627.2023.10339417, (KI-IoT)
(19) Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale
E. Perez, D. Maldonado, E. Perez-Bosch Quesada, M.K. Mahadevaiah, F. Jimenez-Molinos, Ch. Wenger, J.B. Rodan
IEEE Transactions on Electron Devices 70(1), 360 (2023)
DOI: 10.1109/TED.2021.3072868, (KI-IoT)
The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.
(20) Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations
D. Reiser, M. Reichenbach, T. Rizzi, A. Baroni, M. Fritscher, Ch. Wenger, C. Zambelli, D. Bertozzi
Proc. 21st IEEE Interregional New Circuits And Systems Conference (NEWCAS 2023), (2023)
DOI: 10.1109/NEWCAS57931.2023.10198076
(21) Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-based FPGAs
T. Rizzi, A. Baroni, A. Glukhov, D. Bertozzi, Ch. Wenger, D. Ielmini, C. Zambelli
IEEE Transactions on Device and Materials Reliability 23(3), 328 (2023)
DOI: 10.1109/TDMR.2023.3259015
Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations.
(22) Exploring the NBTI Aging and PVT Effects on RRAM-based FPGA Multiplexers Performance
T. Rizzi, A. Baroni, D. Bertozzi, Ch. Wenger, D. Ielmini, C. Zambelli
Proc. IEEE International Integrated Reliability Workshop (IIRW 2023), (2023)
(MIMEC)
(23) Selective Epitaxy of Germanium by Reduced Pressure Chemical Vapor Deposition: Effect of Area Growth Size on Morphology, Strain, and Optical Emission
D. Ryzhak, A.A. Corley-Wiciak, P. Steglich, Y. Yamamoto, J. Frigerio, D. Spirito, G. Capellini
Proc. 14th International WorkShop on New Group IV Semiconductor Nanoelectronics (El4GroupIV 2023), 27 (2023)
(VISIR2)
(24) AC Field Assisted Deposition of Influenza Viruses on Nanoelectrodes
S. Stanke, Ch. Wenger, F.F. Bier, R. Hölzel
Proc. 4th European Biosensor Symposium (EBS 2023), 160 (2023)
(25) Redox-Based Bi-Layer Metal Oxide Memristive Devices
F. Zahari, S. Park, M.K. Mahadevaiah, Ch. Wenger, H. Kohlstedt, M. Ziegler
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Redox-Based Bi-Layer Metal Oxide Memristive Devices, Springer Series on Bio- and Neurosystems (SSBN) 16, Springer, 87 (2023)
DOI: 10.1007/978-3-031-36705-2_3, (NeuroMem)
(26) Neuromorphic Circuits with Redox-Based Memristive Devices
F. Zahari, M. Ziegler, P. Doerwald, Ch. Wenger, H. Kohlstedt
Bio-Inspired Information Pathways, 1st Edition, Editors: M. Ziegler, T. Mussenbrock, H. Kohlstedt, Chapter. Redox-Based Bi-Layer Metal Oxide Memristive Devices, Springer Series on Bio- and Neurosystems (SSBN) 16, Springer, 43 (2023)
DOI: 10.1007/978-3-031-36705-2_2, (NeuroMem)
