Script list Publications
(1) Characterization of HBT-based Avalanche Noise Sources using Standard Test Structures for Measurement of Transistor Scattering Parameters
E. Bernardini, G. Schiavolini, G. Orecchini, G. Fischer, C. Carta, F. Alimenti
Proc. IEEE Radio and Wireless Week (RWW 2025), 50 (2025)
DOI: 10.1109/SiRF63957.2025.11076623, (AMX IP)
(2) D-Band Demonstration of Quasi-Optical and Analog Beam Reconfiguration using Phased Array and Lens for 6G Applications
M.A. Campo, S. Bruni, A. Lauer, M. Wleklinski, U. Gollor, W. Wischmann, A. Friedrich, C. Oikonomopoulos, O. Litschke, C. Herold, A. Malignaggi, N. Moroni, K.Krishnegowda, C. Carta, W. Keusgen
IEEE Transactions on Antennas and Propagation 73(8), 5064 (2025)
DOI: 10.1109/TAP.2025.3557716
In this paper, a hybrid quasi-optic and analogue beamforming approach is presented, involving an elliptical lens with an active focal plane array at D-band (110-170 GHz). Beamwidth reconfigurability and steering in two planes with enhanced performance are demonstrated. The quasi-optic technique minimizes the beam squint over frequency. Analogue phase shift in the focal plane array is used to increase the lens steering range. A prototype including two 4-channel D-band transceivers with on-chip antennas has been built as demonstrator. The resulting active focal plane array consists of 2x4 antenna elements, which are tuned in amplitude and phase to reconfigure the beam. The advantages of using a resonant leaky-wave cavity combined with a coherent array of feeds are discussed and quantified. Radiation pattern measurements performed with the calibrated active antenna validate the beam reconfiguration concept in two planes at 140 GHz. A steering loss reduction ranging from 2 to 4.5 dB is achieved in the whole D-band at 22° scan angle by applying beam steering in the feed radiation.
(3) A Fully Integrated Modular 2x4 220-260 GHz Beam-Forming Transmitter and Receiver with 50 Gbps Wireless Transmission in SiGe:C BiCMOS
M.H. Eissa, N. Maletic, M. Wietstruck, V. Sark, A. Malignaggi, W. Abdullah, C. Carta, G. Kahmen
IEEE Transactions on Terahertz Science and Technology 15(5), 805 (2025)
DOI: 10.1109/TTHZ.2025.3573157, (Open 6G Hub)
This article presents a 220-260 GHz fully integrated phased-array wireless system featuring direct conversion RF beam-forming. The system is constructed using fully integrated transmitter (Tx) and receiver (Rx) chips with on-chip antenna array. A 4-channel Tx and Rx are designed and fabricated in a 130nm SiGe BiCMOS process with fT / fmax = 300 / 500 GHz. A modular design approach enables the chips as building units for 2xN phased arrays and multiple-input multiple-output (MIMO) systems. A comprehensive design approach for the Tx and Rx chips focusing on key design decisions is presented in this work. The transmitter is equipped with a local oscillator (LO) multiplication chain, IQ up−conversion mixer, active RF splitting network, vector modulator phase shifter (VMPS), temperature sensors, and high output power amplifiers (PA). The PA with power−combining boost the effective isotropic radiated power (EIRP) and reduces the need for external lenses. The receiver is equipped with an LO chain, IQ down−conversion mixer, active RF combining network, VMPS, and low noise amplifiers (LNA). In both Tx and Rx the antenna array is composed of four differential double-folded dipole antennas with local backside etching (LBE). The Tx and Rx chips consume 4.4W and 1.84W of power respectively from a 3.5V supply while each occupying 25mm2 of silicon area. With a measured Tx array effective isotropic radiated power (EIRP) of 24 dBm, a beamforming wireless link is demonstrated supporting up to 50 Gbps of data rates across 85 cm of link distance with no need for focusing lenses and ±30º of scanning capability. With these capabilities, the presented modular chips enable future scaling for 2xN antenna arrays for sensing and communication applications.
(4) A 4-bit 40 GS/s Power Efficient DAC for 6G Communicatio Systems
A.S. Elsayed, P. Ostrovskyy, C. Carta
Proc. 16th German Microwave Confernace (GeMIC 2025), 661 (2025)
DOI: 10.23919/GeMiC64734.2025.10979014, (6G-RIC)
(5) Varactors for Integrated RF Circuits in a 130 nm BiCMOS Technology
M. Elviretti, A. Malignaggi, N. Pelagalli, H. Rücker, L. Menicucci Salamanca, Ch. Wipf, C. Carta, A. Mai
Proc. 16th German Microwave Conference (GeMiC 2025), 368 (2025)
DOI: 10.23919/GeMiC64734.2025.10979116, (SICHER)
(6) A Compact 245-310 GHz Balun in 130-nm SiGe BiCMOS Technology
A. Franzese, B. Sütbas, V. Ertürk, T. Mausolf, D. Bierbüsse, R. Negra, E. Shokrolahzade, M. Spirito, C. Carta
Proc. 24th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 61 (2025)
DOI: 10.1109/SiRF63957.2025.11076759, (Open 6G Hub)
(7) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (HYB-RISC)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(8) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (iCampus II)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(9) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (6G-RIC)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(10) A High-Gain 240-325-GHz Power Amplifier for IEEE 802.15.3d Applications in an Advanced BiCMOS Technology
A. Gadallah, A. Malignaggi, B. Sütbas, H. Rücker, D. Kissinger, M.H. Eissa
Proc. 25th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2025), 19 (2025)
DOI: 10.1109/SiRF63957.2025.11076715, (Open 6G Hub)
(11) Hardware-Software Platform Enabling Joint Communication and Radar Sensing at 25 GHz with 1 GHz Bandwidth
S. George, P. Sen, M. Ramzan, M. Umar, Y. Richhariya, J. Adler, C. Carta
Proc. IEEE/MTT-S International Microwave Symposium (IMS 2025), 25 (2025)
DOI: 10.1109/IMS40360.2025.11103844
(12) A Fully-Integrated Four-Channel Phased Array D-Band Transceiver Achieving 10 GBit/s at 10 m
C. Herold, A. Karakuzulu, A. Malignaggi, M. Scheide, N. Maletic, K. Krishnegowda, C. Carta
Proc. 20th IEEE Radio & Wireless Week (RWW 2025), 30 (2025)
(6G-RIC)
(13) Compact and Broadband Up and Down Conversion Mixers for Frequency Interleaving Systems
C. Herold, M. Kravchenko, A. Malignaggi, C. Carta
Proc. 16th German Microwave Conference (GeMiC 2025), 646 (2025)
DOI: 10.23919/GeMiC64734.2025.10978986, (6G-RIC)
(14) Design Considerations for Integrated SiGe BiCMOS Phase-Locked Loops in the Millimeter-Wave Band
F. Herzel, C. Carta, A. Ergintav, G. Fischer
Proc. 32st IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2025), 87 (2025)
DOI: 10.23919/MIXDES66264.2025.11092042, (AMX IP)
(15) Design Considerations for Integrated SiGe BiCMOS Phase-Locked Loops in the Millimeter-Wave Band
F. Herzel, C. Carta, A. Ergintav, G. Fischer
Proc. 32st IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2025), abstr. book 38 (2025)
(AMX IP)
(16) 44 GHz Bandwidth Optical Receiver Monolithically Integrated in a SiGe ePIC BiCMOS Technology
F. Iseini, N. Pelagalli, A. Malignaggi, A. Peczek, C. Carta, G. Kahmen
20th IEEE Radio & Wireless Week (RWW 2025), 12 (2025)
DOI: 10.1109/SiRF63957.2025.11076882, (100G)
(17) Broadband and Compact 112 Gbit/s Transimpedance Amplifier in a SiGe Copper Backend Technology
F. Iseini, A. Malignaggi, F. Korndörfer, C. Carta, G. Kahmen
Proc. 16th German Microwave Conference (GeMiC 2025), 601 (2025)
DOI: 10.23919/GeMiC64734.2025.10979095, (100G)
(18) Broadband and Power-Efficient Optoelectronic Transmitter Monolithically Integrated in a SiGe BiCMOS ePIC Technology
F. Iseini, A. Malignaggi, A. Peczek, C. Carta, G. Kahmen
Proc. IEEE/MTT-S International Microwave Symposium (IMS 2025), 741 (2025)
DOI: 10.1109/IMS40360.2025.11103858, (100G)
(19) A W-Band Down Conversion Mixer in EPIC 250 nm BiCMOS Technology for Monolithic Optoelectronic Radio Applications
E. Jimenez Tuero, F. Korndörfer, A. Malignaggi, F. Gerfers, C. Carta
Proc. 16th German Microwave Conference (GeMiC 2025), 128 (2025)
DOI: 10.23919/GeMiC64734.2025.10979145, (100G)
(20) Optimal Galvanic Cell Design for Powering Ingestible Devices in Varying Gastrointestinal Conditions
C. Kitchen, V. Erturk, L. Ordelia, A. Swaminathan, S. Sangodoyin
ACS Applied Energy Materials 8(10), 6545 (2025)
DOI: 10.1021/acsaem.5c00463
Energy harvesting using galvanic cells in the gastrointestinal (GI) tract can provide supplementary power and prolong the service life of ingestible devices. This paper explores the impact of electrode type, dimension, and varying gastrointestinal (GI) conditions on the performance of galvanic cells for powering ingestible devices. In vitro experiments were conducted with varying cathodes and anode combinations in synthetic gastric fluid (SGF) under a load resistance sweep to measure the voltage of the galvanic cell. Eighteen tests assessed the peak power, energy capacity, and longevity of each electrode pair. Galvanic cell performance was also evaluated under simulated 1 GI conditions, including varying pH, salt concentration, added foreign substances, and simulated intestinal conditions. Pt and Pd cathodes showed the highest peak power and energy capacity, while Mo was cost-effective for transient applications. Mg was optimal for short-term use, while Zn or the AZ31B Mg alloy was preferred for long-term applications. Energy generation decreased with increasing pH but improved with higher salt concentration. Large substances in gastric fluid hindered performance, and energy generation in intestinal fluids was less efficient. Larger cathode-to-anode size ratios increased efficiency, while larger anodes provided greater longevity. This study successfully characterized the effects of electrode combinations, GI conditions, and dimensions on the performance of galvanic cells, offering insight into the design of supplementary power sources for ingestible devices. These findings aid the development of galvanic cells for short-term and long-term applications in ingestible devices.
(21) A 434 MHz Low-Power Receiver System Based on a Switched Passive Input Network with Surface Acoustic Wave Resonator
G. Meller, M. Methfessel, F. Protze, J. Wagner, F. Ellinger
Proc. 16th German Microwave Conference (GeMiC 2025), 183 (2025)
DOI: 10.23919/GeMiC64734.2025.10979051, (WakeMeUp)
(22) Low Insertion Loss D-Band SP4T Switch using Reverse Saturated SiGe HBTs
N. Moroni, A. Malignaggi, C. Herold, C. Carta
Proc. 16th German Microwave Conference (GeMiC 2025), 443 (2025)
DOI: 10.23919/GeMiC64734.2025.10979062, (6G-RIC)
(23) TX to RX Compact Leakage Cancellation Impedance Tuner for 60 GHz Monostatic Doppler Radar
A. Mushtaq, T. Mausolf, W. Miesch, N. Uddin, W. Winkler, D. Kissinger
IEEE Journal of Microwaves 5(1), 84 (2025)
DOI: 10.1109/JMW.2024.3516476
Monostatic radar shares a single antenna between the transmitter (TX) and receiver (RX) and offers an advantage of the reduced sensor size. However, due to the limited isolation of the coupler, the TX signal leaking into the RX significantly degrades the performance of the monostatic doppler radar. This paper presents the design of an ultra-compact impedance tuner (IT) which is connected to the lumped Rat-Race coupler to minimize the TX to RX leakage signal. The IT offers 5-bit phase control and 8-bit magnitude control via the Serial Peripheral Interface (SPI); moreover, it uses SiGe transistors in reverse saturation to enhance the impedance tuning performance. The size of the IT is only 0.04 mm2 and its power consumption is 4 mW at 3.3V power supply. A two-channel 60 GHz monostatic doppler phased array radar chip has been designed and fabricated in 130 nm SiGe BiCMOS technology for vital signs monitoring application. The measured TX to RX isolation due to the Rat-Race coupler is 22 dB; moreover, IT provides the additional isolation of 27 dB, giving total TX to RX isolation of 49 dB at 60 GHz. The design, simulation and measurements of the IT and its measured leakage cancellation performance is reported in this paper.
(24) A 50 Gb/s Rad-Hard Quad TIA IC for Onboard Satellite Interconnects
P. Ostrovskyy, A. Lujambio, D. Lobato
Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2025), (2025)
DOI: 10.1109/ISCAS56072.2025.11044295, (SIPhoDiAS)
(25) Impact of the Series Resistance on Switching Characteristics of 1T1R HfO2-based RRAM Devices
E. Perez, D. Maldonado, S. Pechmann, K.D.S. Reddy, M. Uhlmann, A. Hagelauer, J.B. Roldan, Ch. Wenger
Proc. 15th Spanish Conference on Electron Devices (CDE 2025), (2025)
DOI: 10.1109/CDE66381.2025.11038868, (KI-IoT)
(26) A 40 Gb/s Rad-Hard Quad VCSEL Driver in 130nm SiGe BiCMOS for Intrasatellite Optical Interconnects
I. Sourikopoulos, A. Osman, G. Psyllakis, P. Ostrovskyy, A. Lujambio, L. Stampoulidis
Proc. 15th SPIE International Conference on Space Optics (ICSO 2024), 13699, 136993J (2025)
DOI: 10.1117/12.3075237, (SIPhoDiAS)
(27) Medizinradar für häusliche Krankenpflege
B. Sütbas
99 Zukunftsobjekte aus der Lausitz, 1st Edition, Editor: J. Staemmler, Ch.Links Verlag, 185 (2025)
(iCampus)
(28) A Review and Performance Comparison of Key Radar Transceiver Building Blocks at J-Band in IHP SG13G2 and SG13G3 BiCMOS Technologies
B. Sütbas, R. Hasan, A. Gadallah, M.H. Eissa, C. Carta
Proc. 16th German Microwave Conference (GeMiC 2025), 362 (2025)
DOI: 10.23919/GeMiC64734.2025.10979135, (iCampus II)
(29) Medizinradar für häusliche Krankenpflege
B. Sütbas
99 Zukunftsobjekte aus der Lausitz, 1st Edition, Editor: J. Staemmler, Ch.Links Verlag, 185 (2025)
(iCampus II)
(30) A V-Band VSPS using Deep-Saturated SiGe HBTs with 0.34 dB Amplitude and 0.7° Phase Errors
B. Sütbas, M.H. Eissa, G. Kahmen
Proc. 25th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2025), 23 (2025)
DOI: 10.1109/SiRF63957.2025.11076626, (iCampus II)
(31) A V-Band VSPS using Deep-Saturated SiGe HBTs with 0.34 dB Amplitude and 0.7° Phase Errors
B. Sütbas, M.H. Eissa, G. Kahmen
Proc. 25th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2025), 23 (2025)
DOI: 10.1109/SiRF63957.2025.11076626, (iCampus)
E. Bernardini, G. Schiavolini, G. Orecchini, G. Fischer, C. Carta, F. Alimenti
Proc. IEEE Radio and Wireless Week (RWW 2025), 50 (2025)
DOI: 10.1109/SiRF63957.2025.11076623, (AMX IP)
(2) D-Band Demonstration of Quasi-Optical and Analog Beam Reconfiguration using Phased Array and Lens for 6G Applications
M.A. Campo, S. Bruni, A. Lauer, M. Wleklinski, U. Gollor, W. Wischmann, A. Friedrich, C. Oikonomopoulos, O. Litschke, C. Herold, A. Malignaggi, N. Moroni, K.Krishnegowda, C. Carta, W. Keusgen
IEEE Transactions on Antennas and Propagation 73(8), 5064 (2025)
DOI: 10.1109/TAP.2025.3557716
In this paper, a hybrid quasi-optic and analogue beamforming approach is presented, involving an elliptical lens with an active focal plane array at D-band (110-170 GHz). Beamwidth reconfigurability and steering in two planes with enhanced performance are demonstrated. The quasi-optic technique minimizes the beam squint over frequency. Analogue phase shift in the focal plane array is used to increase the lens steering range. A prototype including two 4-channel D-band transceivers with on-chip antennas has been built as demonstrator. The resulting active focal plane array consists of 2x4 antenna elements, which are tuned in amplitude and phase to reconfigure the beam. The advantages of using a resonant leaky-wave cavity combined with a coherent array of feeds are discussed and quantified. Radiation pattern measurements performed with the calibrated active antenna validate the beam reconfiguration concept in two planes at 140 GHz. A steering loss reduction ranging from 2 to 4.5 dB is achieved in the whole D-band at 22° scan angle by applying beam steering in the feed radiation.
(3) A Fully Integrated Modular 2x4 220-260 GHz Beam-Forming Transmitter and Receiver with 50 Gbps Wireless Transmission in SiGe:C BiCMOS
M.H. Eissa, N. Maletic, M. Wietstruck, V. Sark, A. Malignaggi, W. Abdullah, C. Carta, G. Kahmen
IEEE Transactions on Terahertz Science and Technology 15(5), 805 (2025)
DOI: 10.1109/TTHZ.2025.3573157, (Open 6G Hub)
This article presents a 220-260 GHz fully integrated phased-array wireless system featuring direct conversion RF beam-forming. The system is constructed using fully integrated transmitter (Tx) and receiver (Rx) chips with on-chip antenna array. A 4-channel Tx and Rx are designed and fabricated in a 130nm SiGe BiCMOS process with fT / fmax = 300 / 500 GHz. A modular design approach enables the chips as building units for 2xN phased arrays and multiple-input multiple-output (MIMO) systems. A comprehensive design approach for the Tx and Rx chips focusing on key design decisions is presented in this work. The transmitter is equipped with a local oscillator (LO) multiplication chain, IQ up−conversion mixer, active RF splitting network, vector modulator phase shifter (VMPS), temperature sensors, and high output power amplifiers (PA). The PA with power−combining boost the effective isotropic radiated power (EIRP) and reduces the need for external lenses. The receiver is equipped with an LO chain, IQ down−conversion mixer, active RF combining network, VMPS, and low noise amplifiers (LNA). In both Tx and Rx the antenna array is composed of four differential double-folded dipole antennas with local backside etching (LBE). The Tx and Rx chips consume 4.4W and 1.84W of power respectively from a 3.5V supply while each occupying 25mm2 of silicon area. With a measured Tx array effective isotropic radiated power (EIRP) of 24 dBm, a beamforming wireless link is demonstrated supporting up to 50 Gbps of data rates across 85 cm of link distance with no need for focusing lenses and ±30º of scanning capability. With these capabilities, the presented modular chips enable future scaling for 2xN antenna arrays for sensing and communication applications.
(4) A 4-bit 40 GS/s Power Efficient DAC for 6G Communicatio Systems
A.S. Elsayed, P. Ostrovskyy, C. Carta
Proc. 16th German Microwave Confernace (GeMIC 2025), 661 (2025)
DOI: 10.23919/GeMiC64734.2025.10979014, (6G-RIC)
(5) Varactors for Integrated RF Circuits in a 130 nm BiCMOS Technology
M. Elviretti, A. Malignaggi, N. Pelagalli, H. Rücker, L. Menicucci Salamanca, Ch. Wipf, C. Carta, A. Mai
Proc. 16th German Microwave Conference (GeMiC 2025), 368 (2025)
DOI: 10.23919/GeMiC64734.2025.10979116, (SICHER)
(6) A Compact 245-310 GHz Balun in 130-nm SiGe BiCMOS Technology
A. Franzese, B. Sütbas, V. Ertürk, T. Mausolf, D. Bierbüsse, R. Negra, E. Shokrolahzade, M. Spirito, C. Carta
Proc. 24th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 61 (2025)
DOI: 10.1109/SiRF63957.2025.11076759, (Open 6G Hub)
(7) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (HYB-RISC)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(8) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (iCampus II)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(9) RISC-V CPU Design using RRAM-CMOS Standard Cells
M. Fritscher, M. Uhlmann, P. Ostrovskyy, D. Reiser, J.-C. Chen, J. Wen, C. Schulze, G. Kahmen, D. Fey, M. Reichenbach, M. Kristic, Ch. Wenger
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33(9),
DOI: 10.1109/TVLSI.2025.3554476, (6G-RIC)
The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors this enables us to construct a NAND standard cell which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS NAND gate. We illustrate achievable area savings with a halfadder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.
(10) A High-Gain 240-325-GHz Power Amplifier for IEEE 802.15.3d Applications in an Advanced BiCMOS Technology
A. Gadallah, A. Malignaggi, B. Sütbas, H. Rücker, D. Kissinger, M.H. Eissa
Proc. 25th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2025), 19 (2025)
DOI: 10.1109/SiRF63957.2025.11076715, (Open 6G Hub)
(11) Hardware-Software Platform Enabling Joint Communication and Radar Sensing at 25 GHz with 1 GHz Bandwidth
S. George, P. Sen, M. Ramzan, M. Umar, Y. Richhariya, J. Adler, C. Carta
Proc. IEEE/MTT-S International Microwave Symposium (IMS 2025), 25 (2025)
DOI: 10.1109/IMS40360.2025.11103844
(12) A Fully-Integrated Four-Channel Phased Array D-Band Transceiver Achieving 10 GBit/s at 10 m
C. Herold, A. Karakuzulu, A. Malignaggi, M. Scheide, N. Maletic, K. Krishnegowda, C. Carta
Proc. 20th IEEE Radio & Wireless Week (RWW 2025), 30 (2025)
(6G-RIC)
(13) Compact and Broadband Up and Down Conversion Mixers for Frequency Interleaving Systems
C. Herold, M. Kravchenko, A. Malignaggi, C. Carta
Proc. 16th German Microwave Conference (GeMiC 2025), 646 (2025)
DOI: 10.23919/GeMiC64734.2025.10978986, (6G-RIC)
(14) Design Considerations for Integrated SiGe BiCMOS Phase-Locked Loops in the Millimeter-Wave Band
F. Herzel, C. Carta, A. Ergintav, G. Fischer
Proc. 32st IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2025), 87 (2025)
DOI: 10.23919/MIXDES66264.2025.11092042, (AMX IP)
(15) Design Considerations for Integrated SiGe BiCMOS Phase-Locked Loops in the Millimeter-Wave Band
F. Herzel, C. Carta, A. Ergintav, G. Fischer
Proc. 32st IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2025), abstr. book 38 (2025)
(AMX IP)
(16) 44 GHz Bandwidth Optical Receiver Monolithically Integrated in a SiGe ePIC BiCMOS Technology
F. Iseini, N. Pelagalli, A. Malignaggi, A. Peczek, C. Carta, G. Kahmen
20th IEEE Radio & Wireless Week (RWW 2025), 12 (2025)
DOI: 10.1109/SiRF63957.2025.11076882, (100G)
(17) Broadband and Compact 112 Gbit/s Transimpedance Amplifier in a SiGe Copper Backend Technology
F. Iseini, A. Malignaggi, F. Korndörfer, C. Carta, G. Kahmen
Proc. 16th German Microwave Conference (GeMiC 2025), 601 (2025)
DOI: 10.23919/GeMiC64734.2025.10979095, (100G)
(18) Broadband and Power-Efficient Optoelectronic Transmitter Monolithically Integrated in a SiGe BiCMOS ePIC Technology
F. Iseini, A. Malignaggi, A. Peczek, C. Carta, G. Kahmen
Proc. IEEE/MTT-S International Microwave Symposium (IMS 2025), 741 (2025)
DOI: 10.1109/IMS40360.2025.11103858, (100G)
(19) A W-Band Down Conversion Mixer in EPIC 250 nm BiCMOS Technology for Monolithic Optoelectronic Radio Applications
E. Jimenez Tuero, F. Korndörfer, A. Malignaggi, F. Gerfers, C. Carta
Proc. 16th German Microwave Conference (GeMiC 2025), 128 (2025)
DOI: 10.23919/GeMiC64734.2025.10979145, (100G)
(20) Optimal Galvanic Cell Design for Powering Ingestible Devices in Varying Gastrointestinal Conditions
C. Kitchen, V. Erturk, L. Ordelia, A. Swaminathan, S. Sangodoyin
ACS Applied Energy Materials 8(10), 6545 (2025)
DOI: 10.1021/acsaem.5c00463
Energy harvesting using galvanic cells in the gastrointestinal (GI) tract can provide supplementary power and prolong the service life of ingestible devices. This paper explores the impact of electrode type, dimension, and varying gastrointestinal (GI) conditions on the performance of galvanic cells for powering ingestible devices. In vitro experiments were conducted with varying cathodes and anode combinations in synthetic gastric fluid (SGF) under a load resistance sweep to measure the voltage of the galvanic cell. Eighteen tests assessed the peak power, energy capacity, and longevity of each electrode pair. Galvanic cell performance was also evaluated under simulated 1 GI conditions, including varying pH, salt concentration, added foreign substances, and simulated intestinal conditions. Pt and Pd cathodes showed the highest peak power and energy capacity, while Mo was cost-effective for transient applications. Mg was optimal for short-term use, while Zn or the AZ31B Mg alloy was preferred for long-term applications. Energy generation decreased with increasing pH but improved with higher salt concentration. Large substances in gastric fluid hindered performance, and energy generation in intestinal fluids was less efficient. Larger cathode-to-anode size ratios increased efficiency, while larger anodes provided greater longevity. This study successfully characterized the effects of electrode combinations, GI conditions, and dimensions on the performance of galvanic cells, offering insight into the design of supplementary power sources for ingestible devices. These findings aid the development of galvanic cells for short-term and long-term applications in ingestible devices.
(21) A 434 MHz Low-Power Receiver System Based on a Switched Passive Input Network with Surface Acoustic Wave Resonator
G. Meller, M. Methfessel, F. Protze, J. Wagner, F. Ellinger
Proc. 16th German Microwave Conference (GeMiC 2025), 183 (2025)
DOI: 10.23919/GeMiC64734.2025.10979051, (WakeMeUp)
(22) Low Insertion Loss D-Band SP4T Switch using Reverse Saturated SiGe HBTs
N. Moroni, A. Malignaggi, C. Herold, C. Carta
Proc. 16th German Microwave Conference (GeMiC 2025), 443 (2025)
DOI: 10.23919/GeMiC64734.2025.10979062, (6G-RIC)
(23) TX to RX Compact Leakage Cancellation Impedance Tuner for 60 GHz Monostatic Doppler Radar
A. Mushtaq, T. Mausolf, W. Miesch, N. Uddin, W. Winkler, D. Kissinger
IEEE Journal of Microwaves 5(1), 84 (2025)
DOI: 10.1109/JMW.2024.3516476
Monostatic radar shares a single antenna between the transmitter (TX) and receiver (RX) and offers an advantage of the reduced sensor size. However, due to the limited isolation of the coupler, the TX signal leaking into the RX significantly degrades the performance of the monostatic doppler radar. This paper presents the design of an ultra-compact impedance tuner (IT) which is connected to the lumped Rat-Race coupler to minimize the TX to RX leakage signal. The IT offers 5-bit phase control and 8-bit magnitude control via the Serial Peripheral Interface (SPI); moreover, it uses SiGe transistors in reverse saturation to enhance the impedance tuning performance. The size of the IT is only 0.04 mm2 and its power consumption is 4 mW at 3.3V power supply. A two-channel 60 GHz monostatic doppler phased array radar chip has been designed and fabricated in 130 nm SiGe BiCMOS technology for vital signs monitoring application. The measured TX to RX isolation due to the Rat-Race coupler is 22 dB; moreover, IT provides the additional isolation of 27 dB, giving total TX to RX isolation of 49 dB at 60 GHz. The design, simulation and measurements of the IT and its measured leakage cancellation performance is reported in this paper.
(24) A 50 Gb/s Rad-Hard Quad TIA IC for Onboard Satellite Interconnects
P. Ostrovskyy, A. Lujambio, D. Lobato
Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2025), (2025)
DOI: 10.1109/ISCAS56072.2025.11044295, (SIPhoDiAS)
(25) Impact of the Series Resistance on Switching Characteristics of 1T1R HfO2-based RRAM Devices
E. Perez, D. Maldonado, S. Pechmann, K.D.S. Reddy, M. Uhlmann, A. Hagelauer, J.B. Roldan, Ch. Wenger
Proc. 15th Spanish Conference on Electron Devices (CDE 2025), (2025)
DOI: 10.1109/CDE66381.2025.11038868, (KI-IoT)
(26) A 40 Gb/s Rad-Hard Quad VCSEL Driver in 130nm SiGe BiCMOS for Intrasatellite Optical Interconnects
I. Sourikopoulos, A. Osman, G. Psyllakis, P. Ostrovskyy, A. Lujambio, L. Stampoulidis
Proc. 15th SPIE International Conference on Space Optics (ICSO 2024), 13699, 136993J (2025)
DOI: 10.1117/12.3075237, (SIPhoDiAS)
(27) Medizinradar für häusliche Krankenpflege
B. Sütbas
99 Zukunftsobjekte aus der Lausitz, 1st Edition, Editor: J. Staemmler, Ch.Links Verlag, 185 (2025)
(iCampus)
(28) A Review and Performance Comparison of Key Radar Transceiver Building Blocks at J-Band in IHP SG13G2 and SG13G3 BiCMOS Technologies
B. Sütbas, R. Hasan, A. Gadallah, M.H. Eissa, C. Carta
Proc. 16th German Microwave Conference (GeMiC 2025), 362 (2025)
DOI: 10.23919/GeMiC64734.2025.10979135, (iCampus II)
(29) Medizinradar für häusliche Krankenpflege
B. Sütbas
99 Zukunftsobjekte aus der Lausitz, 1st Edition, Editor: J. Staemmler, Ch.Links Verlag, 185 (2025)
(iCampus II)
(30) A V-Band VSPS using Deep-Saturated SiGe HBTs with 0.34 dB Amplitude and 0.7° Phase Errors
B. Sütbas, M.H. Eissa, G. Kahmen
Proc. 25th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2025), 23 (2025)
DOI: 10.1109/SiRF63957.2025.11076626, (iCampus II)
(31) A V-Band VSPS using Deep-Saturated SiGe HBTs with 0.34 dB Amplitude and 0.7° Phase Errors
B. Sütbas, M.H. Eissa, G. Kahmen
Proc. 25th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2025), 23 (2025)
DOI: 10.1109/SiRF63957.2025.11076626, (iCampus)
