Open Source Design Enablement

Design analog, digital, mixed-signal and RF ASICs for IHP's SG13G2 technology using open-source EDA tools.

The IHP Open Source PDK provides chip designers, researchers, educators and EDA developers with open access to process data, device models, design rules, libraries and tool integrations for IHP's 130 nm SG13G2 SiGe BiCMOS and SG13CMOS5L technologies.

It enables open chip design, EDA development, education and collaborative research using a real semiconductor technology and an expanding ecosystem of open-source design tools.

Access the OpenPDK on GitHub | Read the documentation | Explore Open-Silicon MPW access

Current status – Alpha release

The IHP Open Source PDK is currently provided as an alpha release.

The SG13G2 technology and the commercial PDK have already been used for the development of many designs including industrial-grade, high-end products. Currently, the open-source PDK includes a functional set of libraries, which have been used in over a hundred designs fabricated at IHP. The measured and characterized integrated circuits have proven the maturity of the libraries and flows, especially in the digital and analog design domains.

In 2026 we have introduced a variant of SG13G2 PDK called SG13CMOS5L, which provides access to a subset of the design primitives and reduced metal stack. This PDK variant provides an economically viable technology platform with fast turnaround times, that can be adopted by universities and used in the class room as a tape out experience.

Developers and users are invited to use the PDK, contribute to its development and provide feedback through the open-source community via GitHub and our FOSSi chat on Matrix.

What you can do with the IHP Open Source PDK

The IHP Open PDK is designed to lower the barriers to working with a real semiconductor process and supports:

• analog, digital, mixed-signal and RF chip design using open-source EDA tools,
• research projects focused on integrated circuit design,
• education and hands-on training in the field of integrated-circuit design,
• development, testing and benchmarking of open-source EDA software,
• development and sharing of reusable open-source IC designs and IP,
• collaborative projects between IHP and the open-source hardware and EDA communities,
• chip development by small research teams, start-ups and other organizations for which access to conventional design environments can be a significant barrier.

IHP also supports open-source design activities through education initiatives and access opportunities for eligible designs through its Open-Silicon MPW activities.

Supported open-source design flows

Digital design

The SG13G2 and SG13CMOS5L PDKs support open-source RTL-to-GDS design with LibreLane. The available digital design environment provides the technology files, libraries and verification resources required to develop digital designs targeting our technologies via respective design templates - SG13G2 and SG13CMOS5L. These Nix-based containers enable the development of a full, production-ready digital chip using an automated and customizable flow.

Analog and mixed-signal design

The analog design environment supports schematic capture, circuit simulation, layout design and physical verification using open-source tools including xschem, Qucs-S, ngspice, gnucap, Xyce and KLayout.

Support for Magic and Netgen provides additional options for layout and LVS workflows.

RF and electromagnetic design

For RF design and electromagnetic field evaluation, the IHP-Open-PDK ecosystem includes support for tools such as OpenEMS and AWS Palace.

SG13G2 technology

SG13G2 is IHP's 130 nm SiGe BiCMOS technology for high-performance analog, RF, mixed-signal and digital integrated circuits.

• 0.13 μm CMOS triple-well process
• SiGe NPN HBTs
  • up to 350 GHz transition frequency
  • 450 GHz maximum oscillation frequency
• two gate oxides thickness mosfet devices:
  • thin gate oxide for 1.2 V digital logic
  • thick gate oxide for 3.3 V supply voltage
• NMOS, PMOS and isolated NMOS transistors
• polysilicon resistors
• MIM/MoM/Moscap capacitors
• Svaricap device
• ESD devices
• SBD diode
• backend:
  • five thin metal layers
  • two thick metal layers, 2 μm and 3 μm
  • MIM layer

SG13CMOS5L technology

SG13CMOS5L is IHP's 130 nm CMOS technology for analog, mixed-signal and digital integrated circuits.

• 0.13 μm CMOS double well process
• two gate oxides thickness mosfet devices:
  • thin gate oxide for 1.2 V digital logic
  • thick gate oxide for 3.3 V supply voltage
• NMOS, PMOS
• polysilicon resistors
• MoM/Moscap capacitors
• Svaricap device
• ESD devices
• backend:
  • four thin metal layers
  • one thick metal layer, 2 μm

What's included in the OpenPDK

The OpenPDK provides the technology data, libraries, models and verification resources needed to develop designs with supported open-source EDA tools. Current resources include:

Digital libraries

Standard cells, I/O cells and SRAM macros, with design views and data for digital implementation and verification.

Available formats include the following views:

• CDL
• GDSII
• LEF and Tech LEF
• SPICE netlists
• Liberty
• Verilog
• xschem

Devices and simulation models

• primitive-device symbols for Xschem and Qucs-Sl
• HBT, MOS and passive-device models for ngspic, gnucap and xyce simulators
• HBT and MOS measurement data
• SG13G2/CMOS5L process specifications
• Verilog-A defined device models

Layout and physical verification

• primitive-device layout data
• KLayout technology and layer-property files
• parameterized cells for Klayout and Magic
• DRC and LVS support
• Magic and Netgen support
• layout rules manual
• GDS test structures

Design-tool integration

• xschem device symbols, settings and testbenches
• Qucs-S device symbols, example testbenches
• Ngspice and Xyce
• LibreLane support
• OpenEMS and AWS Palace tutorials, scripts and documentation
• electromagnetic-simulation support

Detailed installation instructions, tool-specific workflows and current compatibility information are maintained in the IHP Open PDK documentation.