MPW Schedule 2027 & 2028 and Price Information 2026

General Technology Description

IHP offers standard 0.13 and 0.25 μm CMOS processes which provide NMOS, PMOS, isolated NMOS and passive components such as poly resistors and MIM capacitors. In addition to the standard CMOS processes different front-end-of-line options are offered. In 0.25 μm CMOS the standard aluminum BEOL backend offers 3 thin metal layers and two TopMetal layers (TopMetal1 - fourth 2 μm thick metal layer, TopMetal2 – fifth 3 μm thick metal layer). The Al-BEOL backend for 0.13 μm process offers 5 thin and 2 thick metal layers (TM1: 2 μm TM2: 3 μm). Together with a high dielectric stack this enables increased performance of the passive RF components.

Technologies with an enhanced copper BEOL option are offered.

Technologies for MPW & Prototyping

SG13SA high-performance 0.13 µm BiCMOS with npn-HBTs up to fT / fmax= 250/340 GHz, with 3.3 V I/O CMOS and 1.2 V logic CMOS.
SG13G2A 0.13 µm BiCMOS technology with much higher bipolar performance of fT/fmax = 350/450 GHz.
SG13CMOS‍A RF CMOS technology which includes all features of SG13G2, but no bipolar HBTs
SG13CMOS5LA CMOS technology offered for open-source education designs and which includes front-end of SG13CMOS, but noisolated NMOS, further only 4 thin metal layer and one 2μm thick TopMetal and no MIM capacitor
SG13SCuFEOL process SG13S together with 8 layer Cu BEOL option from X-FAB containing 4 thin Cu layers, 2 thick 3 µm Cu layers, a thin Al layer with 2 fF/µm MIM capacitor and a 2.8 µm Al top layer.
SG13G2CuFEOL process SG13G2 together with 8 layer Cu BEOL option from X-FAB containing 4 thin Cu layers, 2 thick 3 µm Cu layers, a thin Al layer with 2 fF/µm MIM capacitor and a 2.8 µm Al top layer.
SG13G3CuIHP´s highest performance HBT’s with ft/fmax = 470/650 GHz. The process offers a 8-layer Cu-BEOL from X-FAB containing 4 thin Cu layers, 2 thick 3μm Cu layers, a thin Al layer with 2 fF/μm MIM capacitor and a 2.8 μm Aluminum top layer. This technology offers CMOS devices with 130 nm gate length and 1.2 V core voltage and high voltage CMOS devices with 3.3 V core voltage.
SG25H7_EPICA monolithic photonic BiCMOS technology combining 0.25 µm CMOS, high-performance npn HBTs (fT / fmax = >350/>500 GHz), and full photonic device set for C/O-band.
SGB25RHIs a special variant of SGB25V which includes radiation hard IP for space applications.
INTM4TM2 ‍Interposer technology which offers 2 thin and 2 thick Al-BEOL layer on a high resistivity substrate. Further is contains a MIM capacitor and a Thin film resistor. 

A cadence-based mixed signal design kit is available. For high frequency designs an analogue Design Kit in ADS can be used. IHP's reusable blocks and IPs for wireless and broadband are offered to support your designs. 

The following Modules are available

LBEThe Localized Backside Etching module is offered to remove silicon locally to improve passive properties (available in all Al-BEOL technologies).
H7PICIncludes additional photonic design layers along with BiCMOS BEOL layers on SOI wafers.
TSVAn additional option in SG13S and SG13G2 technology that provides RF grounding by vias through silicon to improve RF performance.
MEMRES (RRAM)An RRAM based fully CMOS integrated memristive module based on resistive TiN / HfO2-x / TiN switching devices in SG13G2 technology, along with a Process Design Kit including layout and VerilogA simulation model.

 

2.1 MPW Price Information 2026

Non-Commercial Access

For European non-profit and educational institutions, special discounts are offered for research projects via EUROPRACTICE. 

2.1.1 Prices for Technologies 

Process     Area Price / mm2
SGB25RH€ 3050
SG25H7_EPIC€ 9000
SG13S€ 6300
SG13C€ 4500
SG13G2€ 7300
SG13G3€ 9000
SG13SCu€ 6300
SG13G2Cu€ 7300
SG13G3Cu€ 9000

 

2.1.2 Prices for Modules

Module (Process)Price
LBE (all Al BEOL)€ 5000 per order and technology
BEOL (only) 0.13 µm (SG13)€ 1300 (per mm2)
SG25_H7PIC€ 3800 (per mm2)
TSV (S, G2)€ 12500 per order
MEMRES (G2)€ 2500 per Run + € 600 per mm2
INTM4TM2€ 900 (per mm²)

2.2 MPW Schedule

TAPE IN time is given in the column “TAPE IN”, shipment time in the corresponding table cells.

2.2.1 2027 schedule for complete technologies

TAPE INSG25SG13
PIC H7EPIC H7CMOS5LSG2    G2CuLDMOS/ MEMRESG3G3Cu
Nov 2, 26 Jul 05*       
Nov 16, 26 OS  May 10**      
Jan 10, 27   Sep 23Jun 21Jul 01 Jun 01May 11*
Mar 14, 27 OS  Jul 21**      
Apr 18, 27 OS    Nov 15 Nov 15*  
May 9, 27Nov 10Dec 16**       
Jul 25, 27    Apr 07Mar 29 Jan 11Nov 26
Aug 8, 27  Nov 15      
Oct 3, 27   Jun 19May 03May 24May 03Jul 17Jul 07
Oct 31, 27May 10Jun 29*       
Nov 14, 27 OS  Apr 07**      

* Runs with priority
** Optional runs only available if a minimum area is ordered
OS  Open-Source MPW Runs indicated in column “TAPE IN” with special conditions, which you can find here. 

Local Backside Etching (LBE) is only offered for S and G2 technology (not for Open Source Runs), shipment will be 21 days later than the standard shipment.

2.2.2 2027 BEOL (only)/Interposer runs

Aluminum Backend of Line Runs SG13 BEOL and IntM4TM2 are offered for passive structures and interposer designs only. For SG13 BEOL Metal1 and all layers above are produced. IntM4TM2 contains M4 to TM2 metal layer MIM capacitor and a ThinFilm resistor. On request Local Backside Etching (LBE) is offered for these runs. 

TAPE INSG13 BEOL**IntM4TM2TSV
Feb 22, 27 May 11 
May 9, 27   
Jun 14, 27Oct 25** Jan 17**
Aug 23, 27 OS Nov 09** 

** Optional runs only available if a minimum area is ordered
OS  Open-Source MPW Runs indicated in column “TAPE IN” with special conditions, which you can find here. 

There might be internal runs, without confirmed schedule. Feel free to ask our customer support for more details if you are interested in joining such runs.

2.2.3 2028 schedule for complete technologies

TAPE INSG25SG13
PIC H7EPIC H7CMOS5LSG2G2CuLDMOS/ MEMRESG3G3Cu
Oct 31, 27 Jun 29*       
Nov 14, 27 OS  Apr 07**      
Jan 9, 28   Sep 21Jun 19Jun 29 May 30May 05*
Mar 12, 28 OS  Jul 19**      
Apr 23, 28 OS    Nov 20 Nov 20*  
May 7, 28Jul 03Dec 14**       
Jul 23, 28    Apr 13Apr 04 Jan 15Dec 01
Aug 6, 28  Nov 13      
Oct 8, 28   Jun 25May 09May 31May 09Jul 23Jul 13
Nov 5, 28Jul 10Jul 05*       
Nov 19, 28 OS  Apr 13**      

* Runs with priority
** Optional runs only if a minimum area is ordered
OS  Open-Source MPW Runs indicated in column “TAPE IN” with special conditions, which you can find here. 

Local Backside Etching (LBE) is only offered for S and G2 technology (not for Open Source Runs), shipment will be 21 days later than the standard shipment. 

2.3 Information on Minimum Area per MPW Run

There is a minimum area requirement of only 0.8 mm² for selected technologies or module in schedule tables in chapter 2.2 and 2.3. This is valid for all technologies or modules marked with bold shipment times. For all technologies or modules marked with grey italic shipment times in brackets, minimum area order as given in the following table is required. A registration 4 weeks before TAPE out, followed by the confirmation from the foundry, is necessary in this case. By default these additional runs are without priority. A combination of 0.25 μm based runs and 0.13 μm based runs is not possible.

ProcessMin Area [mm²]Min Area1 for Discount
SG25H7_EPIC10-
SGB25RH25-
SG13S1010
SG13CMOS--
SG13G21010
SG13G310-
SG13SCu1010
SG13G2Cu1010
SG13G3Cu1010
SG25_H7PIC1212

1 Ask for special price if you need more than this area for one MPW run.

Delivery

As default 40 diced samples will be delivered. Exceptions are designs using TSV module and SG25_H7PIC. Here 25 samples will be delivered by default. The delivery includes E-test data and RF measurements.

Back lapping options:

  • 200 µm (no additional fee)
  • 300 µm (no additional fee)
  • 250 µm (additional fee)
  • 150 µm (additional fee)
  • 100 µm (additional fee)
  • 75 µm (for TSV module only)

Research Engineering Runs

IHP is offering complete mask sets only for research purpose and prototyping. If customer specific modules are added to a qualified technology, this technology is considered as non-qualified with status “early access”. Prices for Research Engineering Runs can be given upon request.

IHP's General Terms and Conditions »

For further information please contact:

Dr. René Scholz

Phone: +49 335 5625 647
Fax: +49 335 5625 327
Send e-mail »

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