Wireless and Embedded System Design

The Joint Lab "Wireless and Embedded System Design" was established in 2015 together with the Department of Computer Science of the University of Potsdam. In order to achieve better synergy, IHP runs offices and a hardware laboratory at Campus Griebnitzsee together with the computer science department right next to the computer science department building. The hardware laboratory is used for teaching and research by students, staff members of the IHP, and staff members of the computer science department. In particular, the laboratory is used by students working in joint projects.

  • Research >> click here <<

    The research focus of the Joint Lab is the development of:  

    • middleware platforms, cyber physical systems, power efficient architectures and reliable communication techniques for wireless communication systems and sensor networks with application in the areas of assisted living, industry 4.0, automotive, avionic, telematics and telemedicine applications
    • distributed and clustered systems for various levels of dependability and security
    • design and test techniques for high-performance, dependable, secure, and fault-tolerant embedded systems-on-chip (SoC)
    • low-power und low-noise SoC design methodologies for innovative circuit design like GALS, asynchronous and differential logic design

    The competences of the IHP and the Institute of Computer Science at University of Potsdam are combined in the Joint Lab in four important research fields:

    • wireless systems and sensor networks 
    • parallel systems and embedded SoC design 
    • applications for the Internet of Things and Services Multimedia
    • reliability, safety, compliance
  • Projects >> click here <<

    ENROL (DFG)

  • Publications >> click here <<

    Patents

    1. M. Krstic, G. Schoof, V. Petrovic, S. Weidling, E. Sogomonyan, M. Gössel, Schaltungsanordnung mit Detektion oder Behandlung von transienten Fehlern in einem kombinatorischen Schaltungsteil, Deutsche Patentanmeldung 102013225039.B4, Mai 2016.
    2. M. Augustin, M. Gössel, R. Kraemer, Elektronische Schaltungsanordnung zum Verarbeiten von binären Eingabewerten (Fehlertolerante Schaltungsarchitektur mit reduziertem Flächenaufwand), DE-Patentanmeldung am 29.01.2010, AZ: DE 10 2010 006 383.5.

    Journal papers

    1. F. Kuentzer, M. Krstic, Soft Error Detection and Correction Architecture for Asynchronous Bundled Data Designs,  IEEE Transactions on Circuits and Systems I: Regular Papers, Digital Object Identifier: 10.1109/TCSI.2020.299891,early access.
    2. M. Dug, St. Weidling, E. Sogomonyan, D. Jokic, M. Krstic, Full Error Detection and Correction Method Applied on Pipelined Structure Using Two Approaches, Journal of Circuits, Systems, and Computers (JCSC), 2020
    3. F.A. Kuentzer, L. Juracy, M. Moreira, A. Amory, Testing the Blade Resilient Asynchronous Template,Analog Integrated Circuits and Signal Processing (2020)
    4. F. Mühlbauer, L. Schröder, M. Schölzel, Handling of Transient and Permanent Faults in Dynamically Scheduled Super-Scalar Processors, Microelectronics Reliability 80, 176 (2018)
    5. M. Krstic, S. Weidling, V. Petrovic, E. Sogomonyan, Enhanced Architectures for Soft Error Detection and Correction in Combinational and Sequential Circuits, Microelectronics Reliability, Volume 56, Januar 2016, Seiten 212–220, DOI: doi:10.1016/j.microrel.2015.10.022.

    Conference papers

    1. F. Kuentzer, M. Herrera, O. Schrape, P. Beerel, M. Krstic, Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures, 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2020
    2. F.A. Kuentzer, L.R. Juracy, M.T. Moreira, A.M. Amory, Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template, Proc. 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2020), 86 (2020)
    3. F. Kuentzer, M. Krstic, Soft error detection and correction architecture for asynchronous bundled data designs, 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2019, Fresh Ideas Workshop
    4. F.A. Kuentzer, L.R. Juracy, M.T. Moreira, A.M. Amory, Delay Lines Test Method for the Blade Template, Proc. 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), (2019)
    5. L. Schröder, F. Mühlbauer, M. Schölzel Kombination von on-line und off-line Fehlerbehandlung in dynamisch geplanten Prozessoren, Proc. 30. GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018), 36 (2018)
    6. F. Mühlbauer, L. Schröder, M. Schölzel, A Fault Tolerant Dynamically Scheduled Processor with Partial Permanent Fault Handling, Proc. 19th IEEE Latin-American Test Symposium (LATS 2018), (2018)
    7. F. Meinel, N. Kluge, R. Wollowski, Improving Transistor Sizing for Asynchronous Circuits, Proc. 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2018), 1 (2018)
    8. M. Frohberg, S. Reinhold, P. Poppe, M. Schölzel, Test-Framework zur softwarebasierten Fehlerinjektion, -stimulation und Protokollierung von WSN-Anwendungen, Proc. 17. GI/ITG KuVS Fachgespräch Sensornetze (FGSN 2018), 39 (2018)
    9. N. Kluge, R. Wollowski, Data Path Optimisation and Delay Matching for Asynchronous Bundled-Data Balsa Circuits, 2017 International Conference On Computer Aided Design (ICCAD).
    10. F. Mühlbauer, M. Schölzel, Correcting Transient Faults Using Rollback with Low Overhead for Microcontrollers, Proc. International Workshop on Resiliency in Embedded Electronic Systems (REES 2017), 25 (2017)
    11. F. Mühlbauer, L. Schröder, P. Skoncej, M. Schölzel, Handling Manufacturing and Aging Faults with Software-based Techniques in Tiny Embedded Systems, Proc. IEEE Latin American Test Symposium (LATS 2017), (2017)
    12. F. Mühlbauer, M. Schölzel, Korrektur transienter Fehler durch Rollback mit geringem Software-Overhead für Mikrocontroller, Proc. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017), 53 (2017)
    13. F. Mühlbauer, L. Schröder, M. Schölzel, On Hardware-based Fault-Handling in Dynamically Scheduled Processors, Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), (2017)
    14. S. Weidling, M. Krstic, M. Gössel, Identifizierung fehlerbewahrender Speicherelemente zur Vermeidung der Fehlerakkumulation, ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017), Lübeck, March 05 - 07, 2017, Germany
    15. P. Skoncej, F. Mühlbauer, F. Kubicek, L. Schröder, M. Schölzel, Feasibility of Software-based Repair for Program Memories, Proc. 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2016), 199 (2016)
    16. S. Weidling, M. Krstic, V. Petrovic, E. Sogomonyan, Architektur mit reduzierter Komplexität zur Erkennung und Korrektur von transienten Fehlern in kombinatorischer und sequentieller Logik, Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2016), Siegen, March 06 - 08, 2016, Germany.
    17. F. Mühlbauer, P. Skoncej, M. Schölzel, Softwarebasierte Fehlertoleranz für Flash-Speicher von mikrocontroller-basierten Systemen, Proc. ITG/GI/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2016), (2016)
    18. F. Mühlbauer, M. Schölzel, Erkennung und Korrektur transienter Fehler durch Roll-back mit geringem Overhead, Proc. Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2016), 41 (2016)
    19. M. Frohberg, P. Poppe, N. Vetter, S. Reinhold, M. Schölzel, Cross-Plattform zur Hardware- und Betriebssystemunabhängigen Implementierung von Anwendungen und Protokollen, Proc. GI/ITG KuVS Fachgespräch Sensornetze (FGSN 2016), 47 (2016)
    20. S. Weidling, M. Krstic, V. Petrovic, M. Gössel, Neue Methodik zur Implementierung fehlertoleranter pipeline-basierter Architekturen, 27. Gesellschaft für Informatik / VDE/VDI-Gesellschaft Mikroelektronik, Mikrosystem- und Feinwerktechnik / Informationstechnische Gesellschaft im VDE – Workshop, Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2015).
    21. P. Skoncej, F. Mühlbauer, M. Schölzel, „Softwarebasierte Fehlertoleranz für Flash-Speicher von mikrocontroller-basierten Systemen“, FEES-Workshop 2015
    22. S. Taube, V. Petrovic, M. Krstic, Fault Tolerant Implementation of a SpaceWire Interface, 21st IEEE International Conference on Electronics Circuits and Systems (ICECS), December 7-10, 2014 Marseille, France.
    23. M. Krstic, S. Weidling, V. Petrovic, M. Gössel, Improved Circuitry for Soft Error Correction in Combinational Logic in Pipelined Designs, IEEE International On-Line Testing Symposium 2014.
    24. S. Zeidler, M. Goderbauer, M. Krstic, Design of a Low-Power Asynchronous Elliptic Curve Cryptography Coprocessor, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Abu Dhabi, UAE, Dec, 2013.
    25. M. Augustin, M. Gössel, R. Kraemer, Entwurf fehlertoleranter Zustandsautomaten mit variablem Schutz für spezifische Eingabesequenzen, Proc. 24. GI/GMM/ITG-Workshop: Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 47 (2012)
    26. M. Augustin, M. Gössel, R. Kraemer, Effiziente Synthese von Schaltungen mit spezifischer Fehlertoleranz, Proc. 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ), 93 (2011)
    27. M. Augustin, M. Gössel, R. Kraemer , Implementation of Selective Fault Tolerance with Convential Synthesis Tools, Proc. 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), 213 (2011)
    28. M. Augustin, M. Gössel, R. Kraemer , Selective Fault Tolerance for Finite State Machines, Proc. 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 49 (2011)
    29. M. Augustin, M. Gössel, R. Kraemer, Eine neue Fehlertoleranzmethode zur Verringerung des Flächenaufwandes von TMR-Systemen, Zuverlässigkeit und Entwurf, 4. GMM/GI/ITG-Fachtagung, (GMM-Fachbericht; 66), 89 (2010)
    30. M. Augustin, M. Gössel, R. Kraemer, Reducing the Area Overhead of TMR-Systems by Protecting Specific Signals, Proc. IEEE International On-Line Test Symposium 2010 (IOLTS 2010), (2010)

    Diploma Theses/ Master Theses/ Bachlor Theses

    1. Software Verification and Analysis of the NVIDIA Deep Learning Accelerator; F. Schmeller; Bachelor Thesis, Universität Potsdam, Germany (2021)
    2. A Multi-Tenancy Monitoring API for SAP Data Intelligence using the Prometheus Monitoring System; T. Bernhard; Bachelor Thesis, Universität Potsdam, Germany (2021)
    3. Implementierung eines Multi-Hop-Protokolls für die Kommunikation von Straßenlampen auf Grundlage einer Cross-Plattform; J. Rimatzki; Bachelor Thesis, Universität Potsdam, Germany (2019)
    4. Integration von Test- und Monitoring-Funktionalitäten in eine Sensorknoten-Middlewareplattform zur Durchführung von Tests in einem Sensornetz; P. Poppe; Master Thesis, Universität Potsdam, Germany (2019)
    5. Konzept und Implementierung einer Sensor-API in einem Betriebssystemabstraktionslayer für drahtlose Sensornetze; M. Hencke; Bachelor Thesis, Universität Potsdam, Germany (2019)
    6. Infrastruktur für verteilte Tests in drahtlosen Sensornetzen; S. Reinhold; Bachelor Thesis, Universität Potsdam, Germany (2018)
  • Education >> click here <<

    The IHP has a long tradition and extensive experience in designing and manufacturing wireless and embedded systems. This experience is passed on the students by skilled staff members of the IHP by offering courses in the field of computer engineering. By this know-how-transfer the students will receive the knowledge required to work as junior scientists in future projects hosted at the IHP and at the University of Potsdam, or in local companies working in the same field. Annually provided courses include:

    • reliability and fault tolerance
    • hardware architectures for AI applications
    • introduction to hardware and system description languages
    • chip design

    Courses include lectures and practices in the hardware laboratory. Appropriate tools and hardware for microprocessor programming and for developing and testing embedded designs are provided by the IHP.

    The following figure shows an overview of the offered courses:

    The possible recommended assignment in bachelor (ICS) and master studies (COS) are summarized in the following figures:

Prof. Dr.-Ing. Miloš Krstić

IHP 
Im Technologiepark 25
15236 Frankfurt (Oder)
Germany

Secretary:
Heike Wasgien
Phone: +49 335 5625 342
Send e-mail »

The website is designed for modern browsers. Please use a current browser.