Best paper award at IEEE Latin-​American Test Sym­po­sium for IHP re­searchers!

IHP sci­en­tists, along with re­searchers from Bran­den­burg Uni­ver­sity of Tech­nol­ogy, Uni­ver­sity of Ro­s­tock, and Uni­ver­sity of Pots­dam, won the best paper award at the 26th IEEE Latin Amer­i­can Test Sym­po­sium (LATS) 2025, held from March 11-14, in San Andrés Is­land, Colom­bia. The LATS is a rec­og­nized forum ded­i­cated to pre­sent­ing and dis­cussing sci­en­tific re­sults, emerg­ing ideas, ap­pli­ca­tions, hot top­ics and new trends in the area of electronic-​based cir­cuits and sys­tem test­ing, re­li­a­bil­ity, and se­cu­rity.

The paper, ti­tled “Cycle-​Accurate FPGA Em­u­la­tion of RRAM Cross­bar Array: Ef­fi­cient De­vice and Vari­abil­ity Mod­el­ing with En­ergy Con­sump­tion As­sess­ment” ad­dresses ac­tual chal­lenges in elec­tronic de­sign au­toma­tion (EDA). One of the key gaps here is the lack of sup­port for rapid pro­to­typ­ing, de­sign space ex­plo­ration, and system-​level sim­u­la­tions that ac­count for process-​dependent de­vice vari­abil­ity. To ad­dress this, the joint re­search be­tween IHP, BTU, Uni Ro­s­tock, and Uni Pots­dam in­tro­duces an FPGA-​based em­u­la­tion ap­proach for RRAM cross­bars, en­abling real-​time, cycle-​accurate em­u­la­tions with­out com­plex de­vice mod­els. By lever­ag­ing pre-​generated look-​up ta­bles, the group cap­tures RRAM be­hav­ior with high ac­cu­racy, while a mul­ti­vari­ate ker­nel den­sity es­ti­ma­tion (KDE) method is used to model de­vice vari­abil­ity. This ap­proach en­ables pre­cise la­tency de­ter­mi­na­tion and, when com­bined with Neu­roSim, al­lows for en­ergy con­sump­tion es­ti­ma­tion - of­fer­ing a sig­nif­i­cant speedup over tra­di­tional be­hav­ioral sim­u­la­tions.

Spe­cial Con­grat­u­la­tions to IHP team: Jianan Wen, Fabian Luis Var­gas, An­drea Ba­roni,  Markus Fritscher, Ed­uardo Perez, Chris­t­ian Wenger, and Milos Krstic!

The paper can be found here: https://iee­ex­plore.ieee.org/doc­u­ment/10534601

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