Seminare Seminars Events 06/10/2025

Efficient FPGA Programming with HLS

The 20-hour-in-person course will take place from 10 to 13 June 2025.

Description

This course explores High-Level Synthesis (HLS) methods and processes for designing efficient digital circuits, with an emphasis on hardware/software acceleration for data-intensive applications. As digital circuits grow in size and complexity, traditional hand-coded RTL design has become a significant bottleneck, slowing development cycles. Meanwhile, modern AI, ML, and DSP algorithms demand high parallel computing performance with low power consumption, challenging designers to produce hardware solutions with optimized power, performance, and area (PPA) metrics at unprecedented speeds. Designing custom hardware accelerators for each algorithm using traditional RTL is no longer practical, as it struggles to meet today’s energy efficiency and productivity requirements.

HLS addresses these challenges by shifting the design process to a higher level of abstraction, enabling designers to quickly convert complex algorithms into energy-efficient hardware implementations and easily adapt to evolving requirements. With HLS, designers use high-level languages like C/C++ to define functionality, while HLS tools handle RTL generation, boosting productivity, design exploration, and reusability.

By taking this course, participants will learn to implement and optimize digital systems using C/C++-based HLS programming, developing a solid understanding of the entire HLS design flow and its advantages and limitations compared to traditional RTL design. Participants will also gain hands-on experience with commercial HLS tools, applying their skills to practical use cases.

Registration deadline is Friday 30 May 2025.

Contents overview

Introduction to HLS: motivations, challenges, and opportunities
Hardware Platforms for Adaptive Computing
HLS flow and tools
Optimization methods and their implementation in modern HLS frameworks: Interface Synthesis, Macro-architectural & Micro-architectural Optimizations
Programming techniques for efficient HLS
Hands-on on case studies (AI/ML/DSP) using AMD Vitis platform: Optimization and performance assessment

Pre-requirements

Minimum knowledge in the following fields may help to enjoy the course:
Computer Architecture
Basic knowledge of digital design
C/C++ programming
Basic knowledge of VHDL/Verilog HDL

Registration

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Lecturer

Valentino Peluso, PhD
Assistant Professor
Department of Control and Computer Engineering
Politecnico di Torino

Valentino Peluso received the M.Sc. degree in electronic engineering and the Ph.D. degree in computer engineering from the Politecnico di Torino in 2016 and 2020 respectively. He is currently an Assistant Professor with the Department of Control and Computer Engineering, Politecnico di Torino. His main research interests focus on design automation for digital circuits and systems, with emphasis on enabling energy-efficient federated learning and deep neural networks on edge devices.