Publications 2021
Script list Publications
(1) Non-Isothermal Phase-Field Simulations of Laser-Written In-Plane SiGe Heterostructures for Photonic Applications
O. Aktas, Y. Yamamoto, M. Kaynak, A.C. Peacock
Communication Physics 4, 132 (2021)
DOI: 10.1038/s42005-021-00632-1
Advanced solid-state devices, including lasers and modulators, require semiconductor heterostructures for nanoscale engineering of the electronic bandgap and refractive index. However, existing epitaxial growth methods are limited to fabrication of vertical heterostructures grown layer by layer. Here, we report the use of finite-element-method-based phase-field modelling with thermocapillary convection to investigate laser inscription of in-plane heterostructures within silicon-germanium films. The modelling is supported by experimental work using epitaxially-grown Si0.5Ge0.5 layers. The phase-field simulations reveal that various in-plane heterostructures with single or periodic interfaces can be fabricated by controlling phase segregation through modulation of the scan speed, power, and beam position. Optical simulations are used to demonstrate the potential for two devices: graded-index waveguides with Ge-rich (>70%) cores, and waveguide Bragg gratings with nanoscale periods (100–500 nm). Periodic heterostructure formation via sub-millisecond modulation of the laser parameters opens a route for post-growth fabrication of in-plane quantum wells and superlattices in semiconductor alloy films.
(2) Physical Attacks through the Chip Backside: Threats, Challenges and Opportunities
E. Amini, K. Bartels, C. Boit, M. Eggert, N. Herfurth, T. Kiyan, T. Krachenfels, J.-P. Seifert, S. Tajik
Proc. 39th Symposium on VLSI Technology and Circuits (VLSI Symposia 2021), (2021)
DOI: 10.1109/VTS50974.2021.9441006
(3) Bestimmung der optischen Konstanten und Streueigenschaften von transparenten Kunststoffen auf Polyurethanbasis für den Einsatz in der Optoelektronik
J. Bauer, O. Fursenko, F. Heinrich, M. Gutke, B. Dietzel, E. Kornejew, O. Broedel, A. Kaltenbach, M. Burkhardt, M. Edling, S. Pulwer, P. Steglich, M. Herzog, S. Schrader
Proc. 122. Tagung der DGaO (Deutsche Gesellschaft für angewandte Optik), A17 (2021)
(4) Impedance Matching in Dielectrophoresis Experiments
N. Boldt, D.E. Malti, S. Damm, A. Barai, M. Birkholz, R. Thewes
Proc. IEEE Biomedical Circuits and Systems Conference (BioCas 2021), (2021)
(Bioelectronics)
(5) Fiber-to-Chip Light Coupling using a Graded-Index Lensed Fiber Collimator
S. Bondarenko, M. Hülsemann, A. Mai, P. Steglich
Optical Engineering 60(1), 014105 (2021)
DOI: 10.1117/1.OE.60.1.014105
Fiber-to-chip light coupling using a graded-index (GRIN) fiber collimator is investigated. Our experiments with grating couplers and strip waveguides fabricated in a photonic integrated circuit technology reveal that the peak coupling efficiency of a GRIN fiber collimator is 7.8 dB lower than that of a single-mode fiber. However, the 3-dB alignment tolerance is improved by a factor of about 5.7 giving rise to pluggable sensor solutions. This work opens a path toward a cost-effective and portable sensor platform based on pluggable photonic biosensors using GRIN fiber collimators.
(6) A 239-298 GHz Power Amplifier in an Advanced 130 nm SiGe BiCMOS Technology for Communications Applications
T. Bücher, J. Grzyb, P. Hillger, H. Rücker, B. Heinemann, U.R. Pfeiffer
Proc. 47th European Solid-State Circuits Conference (ESSCIRC 2021), 369 (2021)
DOI: 10.1109/ESSCIRC53450.2021.9567853, (DFG-Dotseven2IC)
(7) An Academic Framework for IC Physical Design Algorithms Development
D. Bulakh, A. Korshunov, A. Datsuk
Proc. International Seminar on Electron Devices Design and Production (SED 2021), (2021)
DOI: 10.1109/SED51197.2021.9444528, (Design Kit)
(8) The Wafer-Level Package Integration of a K/ Ka Band Diplexer-on-PCB
Z. Cao, M. Stocchi, M. Wietstruck, M. Kaynak
Proc. International Microwave Filter Workshop (IMFW 2021), (2021)
(FLEXCOM)
(9) N-Type Ge/Si Antennas for THz Sensing
C.A. Chavarin, E. Hardt, S. Gruessing, O. Skibitzki, I. Costina, D. Spirito, W. Seifert, W.M. Klesse, C.L. Manganelli, C. You, J. Flesch, J. Piehler, M. Missori, L. Baldassarre, B. Witzigmann, G. Capellini
Optics Express 29(5), 7680 (2021)
DOI: 10.1364/OE.418382, (DFG-ESSENCE)
Ge-on-Si plasmonics holds the promise for compact and low-cost solutions in the manipulation of THz radiation. We discuss here the plasmonic properties of doped Ge bow-tie antennas made with a low-point cost CMOS mainstream technology. These antennas display resonances between 500 and 700 GHz, probed by THz Time Domain Spectroscopy. We show surface functionalization of the antennas with a thin layer of α-lipoic acid, that red-shifts the antenna resonances by about 20 GHz. Moreover, we show that also antennas covered with a protective silicon nitride cap layer exhibit a comparable red-shift when covered with the biolayer. This suggests that the electromagnetic fields at the hotspot extend well beyond the cap layer, enabling the possibility to use the antennas with an improved protection of the plasmonic material in conjunction with microfluidics.
(10) Biomolecule Sensing in THz Range with N-Ge/Si Antennas
C.A. Chavarin, A.A. Wiciak, E. Hardt, S. Gruessing, O. Skibitzki, I. Costina, W. Seifert, W.M. Klesse, C.L. Manganelli, C. You, J. Flesch, J. Piehler, M. Missori, W. Koczorowski, L. Baldassarre, B. Witzigmann, G. Capellini, D. Spirito
Proc. 46th International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz 2021), (2021)
DOI: 10.1109/IRMMW-THz50926.2021.9567579, (DFG-ESSENCE)
(11) An Integrated Development Environment for Robust Interoperable PDK Implementation
A. Datsuk, C. Wieden, D. Bulakh, T. Krupkina
Proc. IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus 2021), 2067 (2021)
DOI: 10.1109/ElConRus51938.2021.9396695
(12) A -115 dBc/Hz Integrated Optoelectronic Oscillator in a BiCMOS Silicon Photonic Technology
G. Dziallas, A. Fatemi, A. Peczek, M. Tarar, D. Kissinger, L. Zimmermann, A. Malignaggi, G. Kahmen
Proc. IEEE MTT-S International Microwave Symposium (IMS 2021), 23 (2021)
(13) Photonic Contact Thermometry using Silicon Ring Resonators and Tuneable Laser-based Spectroscopy
R. Eisermann, S. Krenek, G. Winzer, S. Rudtsch
tm-Technisches Messen 88(10), 640 (2021)
DOI: 10.1515/teme-2021-0054, (PhotOQant)
Photonic sensors offer the possibility of purely optical measurement in contact thermometry. In this work, silicon-based ring resonators were used for this purpose. These can be manufactured with a high degree of reproducibility and uniformity due to the established semiconductor manufacturing process. For the precise characterisation of these photonic sensors, a measurement setup was developed which allows laser-based spectroscopy around 1550 nm and stable temperature control from 5 °C to 95 °C. This was characterised in detail and the resulting uncertainty influences of both the measuring set-up and the data processing were quantified. The determined temperature stability at 20 °C is better than 0.51 mK for the typical acquisition time of 10 s for a 100 nm spectrum. For a measurement of >24 h at 30 °C a standard deviation of 2.6 mK could be achieved. A hydrogen cyanide reference gas cell was used for traceable in-situ correction of the wavelength. The determined correction function has a typical uncertainty of 0.6 pm. The resonance peaks of the ring resonators showed a high optical quality of 157 000 in the average with a filter depth of up to 20 dB in the wavelength range from 1525 nm to 1565 nm. When comparing different methods for the determination of the central wavelength of the resonance peaks, an uncertainty of 0.3 pm could be identified. A temperature-dependent shift of the resonance peaks of approx. 72 pm/K was determined. This temperature sensitivity leads together with the analysed uncertainty contributions to a repeatability of better than 10 mK in the analysed temperature range from 10 °C to 90 °C.
(14) Millimeter-Wave Amplifier-Based Noise Sources in SiGe BiCMOS Technology
H. Forsten, J.H. Saijets, M. Kantanen, M. Varonen, M. Kaynak, P. Piironen
IEEE Transactions on Microwave Theory and Techniques 69(11), 4689 (2021)
DOI: 10.1109/TMTT.2021.3104028
This article describes the development and characterization of wideband millimeter-wave noise sources based on SiGe BiCMOS amplifiers. Two single-ended three-stage amplifier-based noise sources reached excess noise ratio (ENR) values over 20 dB from 120 to 220 GHz with 20 mA of the bias current from a 2.3-V supply. We also introduce a novel switchable noise source employing the Lange coupler for providing wideband matching in both ON and OFF configurations of the noise source. The Lange coupler-based noise source has better than 12-dB matching from 90 to 270 GHz with an ENR of better than 15 dB from 125 to 235 GHz.
(15) Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance
S. Fregonese, C. Mukherjee, H. Rücker, P. Chevalier, G.G. Fischer, D. Celi, M. Deng, F. Marc, C. Maneux, T. Zimmer
Proc. IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS 2021), (2021)
(SG13G3)
(16) Modeling and Analysis of the Electrolyte Voltage Drop in Dielectrophoresis Actuators
A. Frey, N. Boldt, A. Barai, M. Birkholz, I. Kuehne, R. Thewes
Proc. IEEE Biomedical Circuits and Systems Conference (BioCas 2021), (2021)
(Bioelectronics)
(17) 2D Grating Coupler Induced Polarization Crosstalk in Coherent Transceivers for Next Generation Data Center Interconnects
G. Georgieva, P.M. Seiler, Ch. Mai, K. Petermann, L. Zimmermann
Proc. Optical Fiber Communications Conference and Exhibition (OFC 2021), W1C.4 (2021)
(18) A 112 Gb/s Radiation-Hardened Mid-Board Optical Transceiver in 130-nm SiGe BiCMOS for Intra-Satellite Links
S. Giannakopoulos, I. Sourikopoulos, L. Stampoulidis, P. Ostrovskyy, F. Teply, K. Tittelbach-Helmrich, G. Panic, G. Fischer, A. Grabowski, H. Zirath, P. Ayzac, N. Venet, A. Maho, M. Sotom, S. Jones, G. Wood, I. Oxtoby
Frontiers in Physics 9, 672941 (2021)
DOI: 10.3389/fphy.2021.672941, (SIPhoDiAS)
We report the design of a 112 Gb/s radiation-hardened (RH) optical transceiver applicable to intra-satellite optical interconnects. The transceiver chipset comprises a vertical-cavity surface-emitting laser (VCSEL) driver and transimpedance amplifier (TIA) integrated circuits (ICs) with four channels per die, which are adapted for a flip-chip assembly into a mid-board optics (MBO) optical transceiver module. The ICs are designed in the IHP 130 nm SiGe BiCMOS process (SG13RH) leveraging proven robustness in radiation environments and high-speed performance featuring bipolar transistors (HBTs) with fT/fMAX values of up to 250/340 GHz. Besides hardening by technology, radiation-hardened-by-design (RHBD) components are used, including enclosed layout transistors (ELTs) and digital logic cells. We report design features of the ICs and the module, and provide performance data from post-layout simulations. We present radiation evaluation data on analog devices and digital cells, which indicate that the transceiver ICs will reliably operate at typical total ionizing dose (TID) levels and single event latch-up thresholds found in geostationary satellites.
(19) BEOL Modifications of a 130 nm SiGe BiCMOS Technology for Monolithic Integration of Thin-Film Wafer-Level Encapsulated D-Band RFMEMS Switches
A. Göritz, S. Tolunay Wipf, M. Wietstruck, M. Kaynak, M. Fraschke, A. Krüger, M. Lisker
23rd IEEE Design, Test, Integration & Packaging of MEMS/MOEMS (DTIP 2021), (2021)
DOI: 10.1109/DTIP54218.2021.9568672
(20) Functionalization of Oxide-Free Silicon Surfaces for Biosensing Applications
A. Henriksson, P. Neubauer, M. Birkholz
Advanced Materials Interfaces 2100927 (2021)
DOI: 10.1002/admi.202100927, (Bioelectronics)
As an alternative to standard silicon biofunctionalization protocol based on alkoxysilanes that bind to SiO2 on oxidized silicon substrates, several protocols to form bifunctional interlayers that directly bind to the silicon surface via a strong Si-C bond have been developed during the last decades. These interlayers are more stable, and the lack of an insulating layer between the substrate and the interlayer reduces electric noise in biosensor devices.
Si-C monolayers are not yet regularly applied as the protocols are more complex and generally require an inert gas atmosphere. However, a variety of applications and new methods to form bifunctional Si-C interlayers were recently developed. Here, we review the role these innovative protocols and interlayers can play in biofunctionalization of silicon surfaces and report their applications in electrochemical, microelectromechanical and optical biosensing. From the analysis of the current situation, it can be concluded that the advantageous properties offered with this approach in many cases more than outweigh the additional processes to form Si-C bonded interlayers and the approach is predicted expand the applications of future silicon-based biosensors.
(21) Design, Simulations and Manufacturing of a Microring Resonator Biosensor Assisted by Dielectrophoresis
A. Henriksson, M. Jäger, L. Kasper, P. Neubauer, M. Birkholz
Proc. 3rd European BioSensor Symposium (EBS 2021), abstr. (2021)
(22) Meticulous SPEM System Calibration as a Key for Extracting Correct Photon Emission Spectra
N. Herfurth, C. Boit
Proc. 28th edition of the IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2021), (2021)
DOI: 10.1109/IPFA53173.2021.9617231
(23) Erratum to “High-Power Radiation at 1 THz in Silicon: A Fully Scalable Array Using a Multi-Functional Radiating Mesh Structure”
Z. Hu, M. Kaynak, R. Han
IEEE Journal of Solid-State Circuits 56(10), 3202 (2021)
DOI: 10.1109/JSSC.2021.3080556
In the above article [1] , in (19) , a factor of 2 is missing. Equations (6) , (8) , and (19) – (27) are impacted by this error. The corrected text from the line above (19) in the Appendix of [1] is as follows.
(24) Performance Comparison of Broadband Traveling Wave Amplifiers in 130 nm SiGe:C SG13G2 and SG13G3 BiCMOS Technologies
M. Inac, A. Fatemi, F. Korndörfer, H. Rücker, F. Gerfers, A. Malignaggi
Proc. IEEE MTT-S International Microwave Symposium (IMS 2021), (2021)
(25) Performance Comparison of Broadband Traveling Wave Amplifiers in 130 nm SiGe:C SG13G2 and SG13G3 BiCMOS Technologies
M. Inac, A. Fatemi, F. Korndörfer, H. Rücker, F. Gerfers, A. Malignaggi
IEEE Microwave and Wireless Components Letters 31(6), 744 (2021)
DOI: 10.1109/LMWC.2021.3067099
In this letter, a comparison between two ultra-wideband traveling wave amplifiers (TWAs) designed in two different SiGe:C technologies consuming only 500 mW is presented. The first design utilizes the IHP’s 130-nm SiGe:C BiCMOS SG13G2 technology, featuring fT /fMAX =300 /500 GHz, while the second design uses the IHP’s 130-nm SiGe:C BiCMOS SG13G3 technology, featuring fT /fMAX =470/700 GHz. For a fair comparison, the same architecture has been used for the design of both amplifiers. On-wafer measurements of the SG13G2 amplifier show 15.3 dB gain and 87.4 GHz bandwidth, while the design in SG13G3 technology reaches 16.9 dB gain and more than 110 GHz bandwidth. There is a 1% difference in the output power efficiency where it is 4.1% and 5.1% on SG13G2 and SG13G3 technologies, respectively. In both cases, time-domain measurements show a reliable 120 Gbps non-return-to-zero (NRZ) operation. The presented SG13G3-based TWA shows state-of-the-art performance among similar SiGe BiCMOS amplifiers.
(26) Parametric Monte-Carlo Characterization of Si Ring Modulators
Y. Jo, Y. Ji, M. Kim, St. Lischke, Ch. Mai,L. Zimmermann, W.-Y. Choi
Proc. IEEE 17th International Conference on Group IV Photonics (GFP 2021)
DOI: 10.1109/GFP51802.2021.9673952, (MPW_ePIC)
(27) Modulation Linearity Characterization of Si Ring Modulators
Y. Jo, Ch. Mai, St. Lischke, L. Zimmermann, W.-Y- Choi
IEEE Journal of Lightwave Technology 39(24), 7842 (2021)
DOI: 10.1109/JLT.2021.3093463
Modulation linearity of Si ring modulators (RMs) is investigated through the numerical simulation based on the coupled-mode theory and experimental verification. Numerical values of the key parameters needed for the simulation are experimentally extracted. Simulation and measurement results agree well. With these, the influence of input optical wavelength and power on the Si RM linearity are characterized.
(28) Numerical Optimization and CW Measurements of SOI Waveguides for Ultra-Broadband C-to-O-Band Conversion
T. Kernetzky, G. Ronniger, U. Höfler, L. Zimmermann, N. Hanik
Proc. 47th European Conference Optical Communications (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9605944, (DFG ULTRA)
(29) Silicon Electronic-Photonic Integrated 25-Gb/s Ring Modulator Transmitter with a Built-In Temperature Controller
M. Kim, M.-H. Kim, Y. Jo, H.-K. Kim, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
Photonics Research 9(4), 507 (2021)
DOI: 10.1364/PRJ.413407
We demonstrate a silicon electronic-photonic integrated 25-Gb/s non-return-to-zero transmitter that includes driver circuits, depletion-type Si ring modulator, Ge photodetector, temperature sensor, on-chip heater, and temperature controller, all monolithically integrated on 0.25-μm photonic BiCMOS technology platform. The integrated transmitter successfully provides stable and optimal 25-Gb/s modulation characteristics against any external temperature fluctuation.
(30) Terahertz Signal Source and Receiver Operating Near 600 GHz and their 3-D Imaging Application
J. Kim, D. Yoon, H. Son, D. Kim, J. Yoo, J. Yun, H.J. Ng, M. Kaynak, J.-S. Rieh
IEEE Transactions on Microwave Theory and Techniques 69(5), 2762 (2021)
DOI: 10.1109/TMTT.2021.3061596
In this article, a set of oscillators and a heterodyne image receiver operating near 600 GHz have been developed, each based on a 250-nm InP heterojunction bipolar transistor (HBT) technology and a 130-nm SiGe HBT technology, respectively. The oscillators are based on the common-base cross-coupled push-push topology, which employed coupled-line loads for improved output power and efficiency with a small area. The measured oscillation frequency ranges of the three oscillators with different coupled-line lengths were 628-682, 556-610, and 509-548 GHz, respectively, with a tuning capability achieved with bias variation. The maximum output power and the dc-to-RF efficiency achieved with the oscillators were -10 dBm and 0.19%, respectively. The heterodyne receiver, which consists of a mixer, an IF amplifier, and an IF detector, exhibited a maximum responsivity of 469 kV/W and a minimum noise equivalent power (NEP) of 0.64 pW/Hz1/2. A transmission-mode 3-D THz tomography imaging setup was established with one of the fabricated oscillators and the heterodyne receiver employed as the signal source and the image detector, respectively. With the imaging setup, a successful reconstruction of 3-D images of a target object was demonstrated based on the filtered back-projection algorithm.
(31) Si Photonic-Electronic Monolithically Integrated Optical Receiver with a Built-In Temperature-Controlled Wavelength Filter
H.-K. Kim, M. Kim, M.-H. Kim, Y. Jo, St. Lischke, Ch. Mai, L. Zimmermann, W. Choi
Optics Express 29(6), 9565 (2021)
DOI: 10.1364/OE.418222
We present a Si photonic-electronic integrated ring-resonator based optical receiver that contains a temperature-controlled ring-resonator filter (RRF), a Ge photodetector, and receiver circuits in a single chip. The temperature controller automatically determines the RRF temperature at which the maximum transmission of the desired WDM signal is achieved and maintains this condition against any temperature or input wavelength fluctuation. This Si photonic-electronic integrated circuit is realized with 0.25-µm photonic BiCMOS technology, and its operation is successfully confirmed with measurement.
(32) A Temperature-Aware Large-Signal SPICE Model for Depletion-Type Silicon Ring Modulators
M. Kim, Y. Jo, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
IEEE Photonics Technology Letters 33(17), 947 (2021)
DOI: 10.1109/LPT.2021.3098760
We present a large-signal SPICE model for the depletion-type silicon ring (RM) modulator that includes temperature dependence. The model is based on the temperature-dependent equivalent circuit for the RM and allows easy simulation of RM modulation characteristics in SPICE. The accuracy of the model is verified with the measurement results of 25-Gb/s NRZ modulation at several different temperatures. In addition, simulation of the temperature-dependent transient responses of the RM together with the RM temperature control circuit is demonstrated in the standard IC design environment.
(33) Plasmonics - High-Speed Photonics for Co-Integration with Electronics
U. Koch, C. Uhl, H. Hettrich, Y. Fedoryshyn, D. Moor, M. Baumann, C. Hoessbacher, W. Heni, B. Baeuerle, B.I. Bitachon, A. Josten, M. Ayata, H. Xu, D.L. Elder, L.R. Dalton, E. Mentovich, P. Bakopoulos, St. Lischke, A. Krüger, L. Zimmermann, D. Tsiokos, N. Pleros, M. Möller, J. Leuthold
Japanese Journal of Applied Physics 60(SB), SB0806 (2021)
DOI: 10.35848/1347-4065/abef13
New high-speed photonic technologies and co-integration with electronics are required to keep up with the demand of future optical communication systems. In this paper, plasmonics is presented as one of the most promising next-generation photonic technologies that already fulfils these requirements in proof-of-concept demonstrations. Plasmonics features not only modulators and detectors of highest speed, but also compactness, cost- and energy-efficiency, and compatibility with CMOS electronics. Recently, co-integration with electronics was demonstrated with record performances of 222 GBd in a hybrid InP electronic-plasmonic transmitter assembly and of 120 GBd with a monolithic BiCMOS electronic-plasmonic transmitter.
(34) Cross-Layer Digital Design Flow for Space Applications
M. Krstic, M. Andjelkovic, O. Schrape, A. Breitenreiter, J.-C. Chen, A. Balashov, A. Simevski
Proc. 32nd International Conference on Microelectronics (MIEL 2021), 45 (2021)
DOI: 10.1109/MIEL52794.2021.9569065, (MORAL)
(35) Cross-Layer Digital Design Flow for Space Applications
M. Krstic, M. Andjelkovic, O. Schrape, A. Breitenreiter, J.-C. Chen, A. Balashov, A. Simevski
Proc. 32nd International Conference on Microelectronics (MIEL 2021), 45 (2021)
DOI: 10.1109/MIEL52794.2021.9569065, (ELICSIR)
(36) Cross-Layer Digital Design Flow for Space Applications
M. Krstic, M. Andjelkovic, O. Schrape, A. Breitenreiter, J.-C. Chen, A. Balashov, A. Simevski
Proc. 32nd International Conference on Microelectronics (MIEL 2021), 45 (2021)
DOI: 10.1109/MIEL52794.2021.9569065, (Space Region)
(37) Very High-Speed Waveguide Integrated Germanium Photo Detectors
St. Lischke, A. Peczek, D. Steckler, F. Korndörfer, J. Morgan, A. Beling, L. Zimmermann
Proc. 47th European Conference on Optical Communication (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9606091, (plaCMOS)
(38) Ultra-Fast Germanium Photodiode with 3-dB Bandwidth of 265 GHz
St. Lischke, A. Peczek, J.S. Morgan, K. Sun, D. Steckler, Y. Yamamoto, F. Korndörfer, Ch. Mai, St. Marschmeyer, M. Fraschke, A. Krüger, A. Beling, L. Zimmermann
Nature Photonics 15, 925 (2021)
DOI: 10.1038/s41566-021-00893-w, (plaCMOS)
On a scalable silicon technology platform, we demonstrate photodetectors matching or even surpassing state-of-the-art III–V devices. As key components in high-speed optoelectronics, photodetectors with bandwidths greater than 100 GHz have been a topic of intense research for several decades. Solely InP-based detectors could satisfy the highest performance specifications. Devices based on other materials, such as germanium-on-silicon devices, used to lag behind in speed, but enabled complex photonic integrated circuits and co-integration with silicon electronics. Here we demonstrate waveguide-coupled germanium photodiodes with optoelectrical 3-dB bandwidths of 265 GHz and 240 GHz at a photocurrent of 1 mA. This outstanding performance is achieved by a novel device concept in which a germanium fin is sandwiched between complementary in situ-doped silicon layers. Our photodetectors show internal responsivities of 0.3 A W−1 (265 GHz) and 0.45 A W−1 (240 GHz) at a wavelength of 1,550 nm. The internal bandwidth–efficiency product of the latter device is 86 GHz. Low dark currents of 100–200 nA are obtained from these ultra-fast photodetectors.
(39) Waveguide-Coupled Ge Photodiodes with 3-dB Bandwidth ≥110 GHz
St. Lischke, A. Peczek, D. Steckler, F. Korndörfer, Ch. Mai, L. Zimmermann
Proc. IEEE Photonics Conference (IPC 2021), (2021)
DOI: 10.1109/IPC48725.2021.9593030, (PEARLS)
(40) Waveguide-Coupled Ge Photodiodes with 3-dB Bandwidth ≥110 GHz
St. Lischke, A. Peczek, D. Steckler, F. Korndörfer, Ch. Mai, L. Zimmermann
Proc. IEEE Photonics Conference (IPC 2021), (2021)
DOI: 10.1109/IPC48725.2021.9593030, (DFG EPIDAC)
(41) Waveguide-Coupled Ge Photodiodes with 3-dB Bandwidth ≥110 GHz
St. Lischke, A. Peczek, D. Steckler, F. Korndörfer, Ch. Mai, L. Zimmermann
Proc. IEEE Photonics Conference (IPC 2021), (2021)
DOI: 10.1109/IPC48725.2021.9593030, (plaCMOS)
(42) Epitaxial GeSn/Ge Vertical Nanowires for P-Type Field-Effect Transistors with Enhanced Performance
M. Liu, D. Yang, A. Shkurmanov, J.H. Bae, V. Schlykow, J.-M. Hartmann, Z. Ikonic, F. Bärwolf, I. Costina, A. Mai, J. Knoch, D. Grützmacher, D. Buca, Q.-T. Zhao
ACS Applied Nano Materials 4(1), 94 (2021)
DOI: 10.1021/acsanm.0c02368
Harvesting the full potential of single-crystal semiconductor nanowires (NWs) for advanced nanoscale field-effect transistors (FETs) requires a smart combination of charge control architecture and functional semiconductors. In this article, high-performance vertical gate-all-around NW p-type FETs (p-FETs) are presented. The device concept is based on advanced Ge0.92Sn0.08/Ge group IV epitaxial heterostructures, employing quasi–one-dimensional semiconductor NWs fabricated with a top-down approach. The advantage of using a heterostructure is the possibility of electronic band engineering with band offsets tunable by changing the semiconductor stoichiometry and elastic strain. The use of a Ge0.92Sn0.08 layer as the source in GeSn/Ge NW p-FETs results in a small subthreshold slope of 72 mV/dec and a high ION/IOFF ratio of 3 × 106. A ∼32% drive current enhancement is obtained compared to the vertical Ge homojunction NW control devices. More interestingly, the drain-induced barrier lowering is much smaller with GeSn instead of Ge as the source. The general improvement of the transistor’s key figures of merits originates from the valence band offset at the Ge0.92Sn0.08/Ge heterojunction, as well as from a smaller NiGeSn/GeSn contact resistivity.
(43) Influence of Plasma Treatment on SiO2/Si and Si3N4/Si Substrates for Large-Scale Transfer of Graphene
R. Lukose, M. Lisker, F. Akhtar, M. Fraschke, T. Grabolla, A. Mai, M. Lukosius
Scientific Reports 11, 13111 (2021)
DOI: 10.1038/s41598-021-92432-4, (GIMMIK)
One of the limiting factors of graphene integration into electronic, photonic, or sensing devices is the unavailability of large-scale graphene directly grown on the isolators. Therefore, it is necessary to transfer graphene from the donor growth wafers onto the isolating target wafers. In the present research, graphene was transferred from the chemical vapor deposited 200mm Germanium/Silicon (Ge/Si) wafers onto isolating (SiO2/Si and Si3N4/Si) wafers by electrochemical delamination procedure, employing poly(methylmethacrylate) as an intermediate support layer. In order to influence the adhesion properties of graphene, the wettability properties of the target substrates were investigated in this study. To increase the adhesion of the graphene on the isolating surfaces, they were pre-treated with oxygen plasma prior the transfer process of graphene. The wetting contact angle measurements revealed the increase of the hydrophilicity after surface interaction with oxygen plasma, leading to improved adhesion of the graphene on 200 mm target wafers and possible proof-of-concept development of graphene-based devices in standard Si technologies.
(44) Measurements and Analysis of Different Front-End Configurations for Monolithic SiGe BiCMOS Pixel Detectors for HEP Applications
F. Martinelli, C. Magliocca R. Cardella,E. Charbon, G. Iacobucci, M. Nessi, L. Paolozzi, H. Rücker, P. Valerio
Journal of Instrumentation 16, 12038 (2021)
DOI: 10.1088/1748-0221/16/12/P12038, (SG13G3)
This paper presents a small-area monolithic pixel detector ASIC designed in 130 nm SiGe BiCMOS technology for the upgrade of the pre-shower detector of the FASER experiment at CERN. The purpose of this prototype is to study the integration of fast front-end electronics inside the sensitive area of the pixels and to identify the configuration that could satisfy at best the specifications of the experiment. Self-induced noise, instabilities and cross-talk were minimised to cope with the several challenges associated to the integration of pre-amplifiers and discriminators inside the pixels. The methodology used in the characterisation and the design choices will also be described. Two of the variants studied here will be implemented in the pre-production ASIC of the FASER experiment pre-shower for further tests.
(45) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (Total Resilience)
(46) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (KI-PRO)
(47) Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits
V. Milo, A. Glukhov, E. Perez, C. Zambelli, N. Lepri, M.K. Mahadevaiah, E. Perez-Bosch Quesada, P. Olivo, Ch. Wenger, D. Ielmini
IEEE Transactions on Electron Devices 68(8), 3832 (2021)
DOI: 10.1109/TED.2021.3089995, (Neutronics)
Resistive switching memory (RRAM) is a promising technology for embedded memory and their application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations which might cause a degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slope in the programming characteristics. We test the accuracy of a 2-layer fully-connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a trade-off between the FC-NN accuracy, size and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.
(48) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (NeuroMem)
(49) Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits
V. Milo, A. Glukhov, E. Perez, C. Zambelli, N. Lepri, M.K. Mahadevaiah, E. Perez-Bosch Quesada, P. Olivo, Ch. Wenger, D. Ielmini
IEEE Transactions on Electron Devices 68(8), 3832 (2021)
DOI: 10.1109/TED.2021.3089995, (Total Resilience)
Resistive switching memory (RRAM) is a promising technology for embedded memory and their application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations which might cause a degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slope in the programming characteristics. We test the accuracy of a 2-layer fully-connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a trade-off between the FC-NN accuracy, size and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.
(50) High Frequency Magnetic Sheet Materials – Performance Factor Comparisons and Design of Toroidal Inductors Embedded in PCB
R. Murphy, P. McCloskey, Z. Cao, C. Ó Mathúna, S. ODriscoll
Proc. IEEE Applied Power Electronics Conference and Exposition (APEC 2021), 2897 (2021)
DOI: 10.1109/APEC42165.2021.9487131, (GaNonCMOS)
(51) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10, 083002 (2021)
Proc. 239th ECS Meeting (2021)
(NeuroMem)
(52) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10, 083002 (2021)
Proc. 239th ECS Meeting (2021)
(Total Resilience)
(53) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10, 083002 (2021)
Proc. 239th ECS Meeting (2021)
(KI-PRO)
(54) Performance Assessment of Amorphous HfO2-Based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10(8), 083002 (2021)
DOI: 10.1149/2162-8777/ac175c
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.
(55) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
DOI: 10.1149/10202.0029ecst, (NeuroMem)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.
(56) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
DOI: 10.1149/10202.0029ecst, (Total Resilience)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.
(57) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
DOI: 10.1149/10202.0029ecst, (KI-PRO)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.
(58) A High-Gain SiGe BiCMOS LNA for 5G In-Band Full-Duplex Applications
T.A. Ozkan, A. Burak, I. Kalyoncu, M. Kaynak, Y. Gurbuz
Proc. 15th European Microwave Integrated Circuits Conference (EuMIC 2020), 53 (2021)
(59) A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells
S. Pechmann, T. Mai, M. Völkel, M.K. Mahadevaiah, E. Perez, E. Perez-Bosch Quesada, M. Reichenbach, Ch. Wenger, A. Hagelauer
Electronics (MDPI) 10(5), 530 (2021)
DOI: 10.3390/electronics10050530, (KI-PRO)
In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.
(60) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (Neutronics)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.
(61) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (KI-PRO)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.
(62) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (Total Resilience)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.
(63) Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
E. Perez-Bosch Quesada, R. Romero-Zaliz, E. Perez, M.K. Mahadevaiah, J. Reuben, M.A. Schubert, F. Jimenez-Molinos, J.B. Roldan, Ch. Wenger
Electronics (MDPI) 10(6), 645 (2021)
DOI: 10.3390/electronics10060645, (NeuroMem)
In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.
(64) Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
E. Perez-Bosch Quesada, R. Romero-Zaliz, E. Perez, M.K. Mahadevaiah, J. Reuben, M.A. Schubert, F. Jimenez-Molinos, J.B. Roldan, Ch. Wenger
Electronics (MDPI) 10(6), 645 (2021)
DOI: 10.3390/electronics10060645, (Total Resilience)
In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.
(65) Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
E. Perez-Bosch Quesada, R. Romero-Zaliz, E. Perez, M.K. Mahadevaiah, J. Reuben, M.A. Schubert, F. Jimenez-Molinos, J.B. Roldan, Ch. Wenger
Electronics (MDPI) 10(6), 645 (2021)
DOI: 10.3390/electronics10060645, (KI-PRO)
In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.
(66) Memristive-Based In-Memory Computing: From Device to Large-Scale CMOS Integration
E. Perez-Bosch Quesada, E. Perez, M.K Mahadevaiah, Ch. Wenger
Neuromorphic Computing and Engineering 1(2), 024006 (2021)
DOI: 10.1088/2634-4386/ac2cd4
With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal-insulator-metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments.
(67) Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays
E. Perez, M.K. Mahadevaiah, E. Perez-Bosch Quesada, Ch. Wenger
IEEE Transactions on Electron Devices 68(6), 2693 (2021)
DOI: 10.1109/TED.2021.3072868, (Neutronics)
Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.
(68) Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays
E. Perez, M.K. Mahadevaiah, E. Perez-Bosch Quesada, Ch. Wenger
IEEE Transactions on Electron Devices 68(6), 2693 (2021)
DOI: 10.1109/TED.2021.3072868, (Total Resilience)
Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.
(69) Sensitivity of HfO2-based RRAM Cells to Laser Irradiation
D. Petryk, Z. Dyka, E. Perez, I. Kabin, J. Katzer, J. Schäffner, P. Langendörfer
Microprocessors and Microsystems 87, 104376 (2021)
(RESCUE)
(70) Efficient Ultra-Broadband C-to-O Band Converter Based on Multi-Mode Silicon-on-Insulator Waveguides
G. Ronniger, I. Sackey, T. Kernetzky, U. Höfler, Ch. Mai, C. Schubert, N. Hanik, L. Zimmermann, R. Freund, K. Petermann
Proc. 47th European Conference on Optical Communications (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9606033, (DFG ULTRA)
(71) Synthesis of a Tunable Ring Filter: Proof-of-Concept with Fixed Implementations at D-Band
P. Rynkiewicz, A.-L. Franc, F. Coccetti, M. Wietstruck, M. Kaynak, G. Prigent
International Journal of RF and Microwave Computer-Aided Engineering 31(9), e22761 (2021)
DOI: 10.1002/mmce.22761
The working frequencies of telecommunication systems are rapidly increasing and sub-THz applications will soon be required. In that context, the current article presents the synthesis of a tunable ring filter. The considered filter introduces a new degree of freedom that allows to meet targeted specifications in terms of central frequency and bandwidth. Thanks to a capacitor displacement, the equivalent characteristic impedance can be tuned independently of its equivalent electrical length. The existing filter synthesis is modified to take this concept into account and thus provide a synthesis tunable in central frequency and bandwidth. The proof-of-concept of the design procedure is achieved in SiGe BiCMOS 0.25 μm technology with the implementation and measurement of eight non-tunable circuits in the D-band.
(72) Reliable Technology Evaluation of SiGe HBTs and MOSFETs: fMAX Estimation from Measured Data
B. Saha, S. Fregonese, B. Heinemann, P. Scheer, P. Chevalier, K. Aufinger, A. Chakravorty, T. Zimmer
IEEE Electron Device Letters 42(1), 14 (2021)
DOI: 10.1109/LED.2020.3040891, (Taranto)
Maximumoscillation frequency (fMAX) of mmwave transistors is one of the key figures of merit (FOMs) for evaluating the HF-performance of a given technology. However, accurate measurements of fMAX are very difficult. Determination of fMAX is significantly affected by the measurement uncertainties in the admittance (y) parameters. In order to get rid of the random measurement error and to obtain a reliable and stable fMAX value, the frequency dependent y-parameters are described by rational functions formulated from the small-signal hybrid -model of the transistor under investigation. The parameters of these functions are determined following a least square error technique that minimizes the functional error with the measured data. The approach is especially useful for a fast and reliable evaluation of fMAX value. Devices from two different SiGe and an FDSOI (Fully Depleted Silicon On Insulator) MOS technology are measured and stable fMAX values are estimated following this approach.
(73) Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops
O. Schrape, M. Andjelkovic, A. Breitenreiter, St. Zeidler, A. Balashov, M. Krstic
IEEE Transactions on Circuits and Systems I 68(11), 4796 (2021)
DOI: 10.1109/TCSI.2021.3109080, (Scale4Edge)
Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ( 32.4 MeV⋅cm2/mg ) to ( 62.5 MeV⋅cm2/mg ), depending on the variant.
(74) Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops
O. Schrape, M. Andjelkovic, A. Breitenreiter, St. Zeidler, A. Balashov, M. Krstic
IEEE Transactions on Circuits and Systems I 68(11), 4796 (2021)
DOI: 10.1109/TCSI.2021.3109080, (MORAL)
Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ( 32.4 MeV⋅cm2/mg ) to ( 62.5 MeV⋅cm2/mg ), depending on the variant.
(75) Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops
O. Schrape, M. Andjelkovic, A. Breitenreiter, St. Zeidler, A. Balashov, M. Krstic
IEEE Transactions on Circuits and Systems I 68(11), 4796 (2021)
DOI: 10.1109/TCSI.2021.3109080, (SPAD)
Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ( 32.4 MeV⋅cm2/mg ) to ( 62.5 MeV⋅cm2/mg ), depending on the variant.
(76) Power Efficiency Improvements in Coherent O-Band Data Center Interconnects
P.M. Seiler, L. Zimmermann
Proc. Photonics in Switching and Computing (PSC 2021), Tu4C.3 (2021)
(77) Towards Coherent O-Band Data Center Interconnects
P.M. Seiler, G. Georgieva, G. Winzer, A. Peczek, K. Voigt, St. Lischke, A. Fatemi, L. Zimmermann
Frontiers of Optoelectronics (2021)
DOI: 10.1007/s12200-021-1242-0, (DFG EPIDAC)
Upcoming generations of coherent intra-/inter data center interconnects currently lack a clear path towards a reduction of cost and power consumption, which are the driving factors for these data links. In this work, the trade-offs associated with a transition from coherent C-band to O-band silicon photonics are addressed and evaluated. The discussion includes the fundamental components of coherent data links, namely the optical components, fiber link and transceivers. As a major component of these links, a monolithic silicon photonic BiCMOS O-band coherent receiver is evaluated for its potential performance and compared to an analogous C-band device in the same technology.
(78) Ultra-Wideband Silicon Photonic BiCMOS Coherent Receiver for O- and C-Band
P.M. Seiler, K. Voigt, St. Lischke, A. Malignaggi, L. Zimmermann
Proc. 47th European Conference on Optical Communications (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9606051, (ORIONAS)
(79) Ultra-Wideband Silicon Photonic BiCMOS Coherent Receiver for O- and C-Band
P.M. Seiler, K. Voigt, St. Lischke, A. Malignaggi, L. Zimmermann
Proc. 47th European Conference on Optical Communications (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9606051, (DFG EPIDAC)
(80) Ultra-Wideband Silicon Photonic BiCMOS Coherent Receiver for O- and C-Band
P.M. Seiler, K. Voigt, St. Lischke, A. Malignaggi, L. Zimmermann
Proc. 47th European Conference on Optical Communications (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9606051, (PEARLS)
(81) Towards Coherent O-Band Data Center Interconnects
P.M. Seiler, G. Georgieva, G. Winzer, A. Peczek, K. Voigt, St. Lischke, A. Fatemi, L. Zimmermann
Frontiers of Optoelectronics (2021)
DOI: 10.1007/s12200-021-1242-0, (ORIONAS)
Upcoming generations of coherent intra-/inter data center interconnects currently lack a clear path towards a reduction of cost and power consumption, which are the driving factors for these data links. In this work, the trade-offs associated with a transition from coherent C-band to O-band silicon photonics are addressed and evaluated. The discussion includes the fundamental components of coherent data links, namely the optical components, fiber link and transceivers. As a major component of these links, a monolithic silicon photonic BiCMOS O-band coherent receiver is evaluated for its potential performance and compared to an analogous C-band device in the same technology.
(82) Towards Coherent O-Band Data Center Interconnects
P.M. Seiler, G. Georgieva, G. Winzer, A. Peczek, K. Voigt, St. Lischke, A. Fatemi, L. Zimmermann
Frontiers of Optoelectronics (2021)
DOI: 10.1007/s12200-021-1242-0, (PEARLS)
Upcoming generations of coherent intra-/inter data center interconnects currently lack a clear path towards a reduction of cost and power consumption, which are the driving factors for these data links. In this work, the trade-offs associated with a transition from coherent C-band to O-band silicon photonics are addressed and evaluated. The discussion includes the fundamental components of coherent data links, namely the optical components, fiber link and transceivers. As a major component of these links, a monolithic silicon photonic BiCMOS O-band coherent receiver is evaluated for its potential performance and compared to an analogous C-band device in the same technology.
(83) JICG CMOS Transistors for Reduction of Total Ionizing Dose and Single Event Effects in a 130 nm Bulk SiGe BiCMOS Technology
R. Sorge, J. Schmidt, Ch. Wipf, F. Reimer, F. Teply, F. Korndörfer
Nuclear Instruments and Methods in Physics Research Section A 987, 164832 (2021)
DOI: 10.1016/j.nima.2020.164832, (Total Resilience)
We report on a novel radiation hardening by design (RHBD) approach for mitigation of total ionization dose (TID) induced drain leakage currents and single event transient (SET) in digital circuits fabricated in a 130 nm bulk SiGe BiCMOS technology. In order to avoid significant TID induced increase of drain leakage currents for NMOS transistors and channel pinch-off for PMOS transistors due to positive charges trapped at the lateral shallow trench insulator silicon interface we introduced junction isolation (JI) for the lateral MOS channel regions. The device construction measures applied also support to suppress the generation SETs. The tolerance of JI MOS transistors against TID induced drain leakage currents was verified up to a TID > 1.3 Mrad(Si). SET tests performed at four different inverter types varying in the arrangement the deep well in the layout. For CMOS inverters with isolated NMOS transistors a LET threshold > 130 MeV cm2 mg−1 was obtained.
(84) The H2020-SPACE-ORIONAS Project: “Lasercom-on-Chip” for High-Speed Satellite Constellation Interconnectivity
L. Stampoulidis, A. Osman, I. Sourikopoulos, G. Winzer, L. Zimmermann, A. Maho, M. Faugeron, M. Sotom, F. Caccavale, A. Serrano Rodrigo, M. Chiesa, D. Rotta, G.B. Preve, J. Edmunds, M. Welch, E. Kehayas, W. Dorward, F. Duport, R. Costa, D. Mesquita, L. Stampoulidis
Proc. SPIE International Conference on Space Optics (ICSO 2021), 11852, 118521L (2021)
DOI: 10.1117/12.2599248
(85) Silicon-Organic Hybrid Photonics: An Overview of Recent Advances, Electro-Optical Effects and CMOS-Integration Concepts
P. Steglich, Ch. Mai, C. Villringer, B. Dietzel, S. Bondarenko, V. Ksianzou, F. Villasmunta, C. Zesch, S. Pulwer, M. Burger, J. Bauer, F. Heinrich, S. Schrader, F. Vitale, F. De Matteis, P. Prosposito, M. Casalboni, A. Mai
Journal of Physics: Photonics 3(2), 022009 (2021)
DOI: 10.1088/2515-7647/abd7cf
In the last decades, much research effort has been invested to develop photonic integrated circuits and the silicon-on-insulator technology was established as reliable platform for highly scalable silicon-based electro-optical modulators. However, the device performance of such devices is restricted by the inherent material properties of silicon. A perspective approach to overcome these deficiencies is the integration of organic materials with exceptional high optical nonlinearities into a silicon-on-insulator photonic platform. Silicon-organic hybrid photonics has been shown to overcome drawbacks of silicon-based modulators in terms of operation speed, bandwidth and energy consumption. This work reviews recent advances in silicon-organic hybrid photonics and covers latest improvements of single components and device concepts. Special emphasis is given to the in-device performance of novel electro-optical polymers and the use of different electro-optical effects such as the linear and quadratic electro-optical effect as well as the electric field-induced linear electro-optical effect. Finally, the inherent challenges of implementing nonlinear optical polymers into a silicon photonic platform are discussed and a perspective for future directions is given.
(86) Photonisch integrierte Schaltkreise für die Bioanalytik
P. Steglich, A. Mai
GIT Labor-Fachzeitschrift 11-12, 26 (2021)
Biosensoren auf Basis von photonisch integrierten Schaltkreisen zeigen aufgrund ihrer hohen Empfindlichkeit, des geringen Platzbedarfs und der Möglichkeit einer digitalen Datenverarbeitung großes Potenzial für zahlreiche Anwendungen in der Vor-Ort-Analyse. Photonische Biosensoren können eine wichtige Rolle im Gesundheitswesen spielen, wenn der Schritt vom Forschungslabor zur Industrieanwendung gelingt. An dieser Schwelle befindet sich die Forschung, was eine große Chance für innovative Vor-Ort-Analysen im Gesundheitsund Umweltsektor mit sich bringt.
(87) Defining Sensitivity of Integrated Optical Biosensors: A Multidisciplinary Lesson Approach
P. Steglich
Proc. Education and Training in Optics and Photonics Conference (ETOP 2021), Th3A.7 (2021)
(88) Optische Biosensoren: Neues Analyseverfahren ermöglicht schnellere Therapieentscheidungen
P. Steglich
kma : Klinikmanagement Aktuell 26(11), 60 (2021)
DOI: 10.1055/s-0041-1739942
Wissenschaftler des Leibniz-Instituts für innovative Mikroelektronik (IHP) in Frankfurt (Oder) haben Mikro chip-basierte optische Biosensoren entwickelt, die nicht nur eine hohe Empfindlichkeit aufweisen, sondern auch eine Miniaturisierung und eine kostengünstige Massenfertigung ermöglichen.
(89) Analysis of BTO-on-Si-Waveguides for Energy-Efficient Electro-Optical Modulators
P. Steglich, A. Mai
Proc. SPIE Integrated Optics: Design, Devices, Systems and Applications VI (2021), 11775, 117750L (2021)
DOI: 10.1117/12.2592501
(90) A Monolithically Integrated Microfluidic Channel in a Silicon-based Photonic-Integrated-Circuit Technology for Biochemical Sensing
P. Steglich, M. Paul, Ch. Mai, A. Böhme, S. Bondarenko, M.G. Weller, A. Mai
Proc. SPIE Optical Sensors (2021), 11772, 1177206 (2021)
DOI: 10.1117/12.2588791
(91) Silicon Photonic Micro-Ring Resonators for Chemical and Biological Sensing: A Tutorial
P. Steglich, D.G. Rabus, C. Sada, M. Paul, M.G. Weller, Ch. Mai, A. Mai
IEEE Sensors Journal (2021)
DOI: 10.1109/JSEN.2021.3119547
Silicon photonic micro-ring resonators (MRR) developed on the silicon-on-insulator (SOI) platform, owing to their high sensitivity and small footprint, show great potential for many chemical and biological sensing applications such as label-free detection in environmental monitoring, biomedical engineering, and food analysis. In this tutorial, we provide the theoretical background and give design guidelines for SOI-based MRR as well as examples of surface functionalization procedures for labelfree detection of molecules. After introducing the advantages and perspectives of MRR, fundamentals of MRR are described in detail, followed by an introduction to the fabrication methods, which are based on a complementary metal-oxide semiconductor (CMOS) technology. Optimization of MRR for chemical and biological sensing is provided, with special emphasis on the optimization of waveguide geometry. At this point, the difference between chemical bulk sensing and label-free surface sensing is explained, and definitions like waveguide sensitivity, ring sensitivity, overall sensitivity as well as the limit of detection (LoD) of MRR are introduced. Further, we show and explain chemical bulk sensing of sodium chloride (NaCl) in water and provide a recipe for label-free surface sensing.
(92) CMOS-Compatible Bias-Tunable Dual-Band Detector based on GeSn/Ge/Si Coupled Photodiodes
E. Talamas Simola, V. Kiyek, A. Ballabio, V. Schlykow, J. Frigerio, C. Zucchetti, A. De Iacovo, L. Colace, Y. Yamamoto, G. Capellini, D. Grützmacher, D. Buca, G. Isella
ACS Photonics 8(7), 2166 (2021)
DOI: 10.1021/acsphotonics.1c0061, (SiGeSn NanoFETs)
Infrared (IR) multispectral detection is attracting an increasing interest with the rising demand for high spectral sensitivity, room temperature operation, CMOS compatible devices. Here, we present a two-terminal dual-band detector, which provides a bias-switchable spectral response in two distinct IR bands. The device is obtained from a vertical GeSn/Ge/Si stack, forming a double junction n-i-p-i-n structure, epitaxially grown on a Si wafer. The photoresponse can be switched, by inverting the bias polarity, between the near and the short-wave IR bands, with specific detectivities of 1.9×1010 and 4.0×109 cm·(Hz)1/2/W, respectively. The possibility of detecting two spectral bands with the same pixel opens up interesting applications in the field of IR imaging and material recognition, as shown in a solvent detection test. The continuous voltage tuning, combined with the non-linear photoresponse of the detector, enables a novel approach to spectral analysis, demonstrated by identifying the wavelength of a monochromatic beam.
(93) Analog 2:1 Multiplexer with over 110 GHz Bandwidth in SiGe BiCMOS Technology
T. Tannert, M. Grözing, M. Berroth, C. Schmidt, J. H. Choi, C. Caspar, J. Schostak, V. Jungnickel, R. Freund, H. Rücker
Proc. IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS 2021), (2021)
(SG13G3)
(94) Designs Break Bandwidth Record
U. Troppenz, J. Kreißl
Nature Photonics 15, 4 (2021)
DOI: 10.1038/s41566-020-00739-x
Two independent reports of directly modulated lasers with bandwidths of >60 GHz may help bring data rates beyond 200 Gb s–1 to low-cost optical communication systems. Key to the successes has been managing photonic feedback effects within the laser cavities.
(95) Numerical Simulation of Optical Through-Silicon Waveguide for 3D Photonic Interconnections
F. Villasmunta, P. Steglich, S. Schrader, H. Schenk, A. Mai
Proc. International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD 2021), 115 (2021)
DOI: 10.1109/NUSOD52207.2021.9541464
(96) Electro-Optical Properties of Doped Polymers with High Transparency in the Visible Wavelength Range
C. Villringer, P. Steglich, S. Pulwer, S. Schrader, J. Laufer
Optical Materials Express 11(11), 3801 (2021)
DOI: 10.1364/OME.435953
The electro-optical (EO) properties of poly(methyl methacrylate) and the photopolymer poly(vinyl cinnamate) doped with varying concentrations of the EO chromophore 2-Methyl-4-nitroaniline were measured. The EO polymers were embedded in Fabry-Pérot etalons for the simultaneous determination of the Pockels and Kerr coefficients from measurements of the fringe shift induced by an external electric field. It was found that the host polymer has a significant impact on the EO performance and that the undoped host polymers exhibit a significant Pockels effect. Moreover, the Kerr effect provides a substantial contribution of 27% to the total change of the refractive index at relatively high electric field strengths of E = 91.2 MV m−1.
(97) Quantitative Scanning Microwave Microscopy of Few-Layer Platinum Diselenide
X. Wang, K. Xiong, L. Li, J.C.M. Hwang, X. Jin, G. Fabi, M. Farina, O. Hartwig, M. Prechtl, G.S. Düsberg, A. Göritz, M. Wietstruck, M. Kaynak
Proc. 50th European Microwave Conference (EuMC 2020), 987 (2021)
DOI: 10.23919/EuMC48046.2021.9338192
(98) An Experimental Load-Pull Based Large-Signal RF Reliability Study of SiGe HBTs
C. Weimer, P. Sakalas, M. Müller, G.G. Fischer, M. Schröter
Proc. IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS 2021)
(SIGEREL)
(99) BiCMOS Through-Silicon Via (TSV) Signal Transition at 240/300 GHz for MM-Wave & Sub-THz Packaging and Heterogeneous Integration
M. Wietstruck, St. Marschmeyer, Ch. Wipf, M. Stocchi, M. Kaynak
Proc. 50th European Microwave Conference (EuMC 2020), 244 (2021)
DOI: 10.23919/EuMC48046.2021.9338247
(100) High-Frequency Tellurene MOSFETs with Biased Contacts
K. Xiong, G. Qiu, Y. Wang, L. Li, A. Göritz, M. Lisker, M. Wietstruck, M. Kaynak, W. Wu, P.D. Ye, A. Madjar, J.C.M. Hwang
Proc. IEEE MTT-S International Microwave Symposium (IMS 2021), 319 (2021)
(101) Threading Dislocation Reduction of Ge by Introducing a SiGe/Ge Superlattice
Y. Yamamoto, C. Corley, M.A. Schubert, M.H. Zoellner, B. Tillack
ECS Journal of Solid State Science and Technology 10(3), 034005 (2021)
DOI: 10.1149/2162-8777/abea5e
The influence of introducing a SiGe/Ge superlattice (SL) between Ge layers and Si substrate for the sake of the reduction of the threading dislocation density (TDD) without additional annealing is investigated. By introducing the SiGe/Ge SL and optimizing the layer stack, the TDD of the Ge layer becomes ~1/3. In the case of 2.8 μm thick Ge without introducing the SiGe/Ge SL, the TDD at the surface is 7.6 × 108 cm−2. A slight TDD reduction is observed by introducing a Si0.2Ge0.8/Ge SL between the Si substrate and the Ge layer. By inserting 5, 10 and 20 cycles of Si0.2Ge0.8/Ge, the TDD is reduced to 7.1 × 108, 5.9 × 108 and 5.3 × 108 cm−2, respectively. The lateral lattice parameters of these SLs are ~5.656 Å, which is a smaller value compared to that of bulk Ge, indicating plastic relaxation by misfit dislocation formation. Further TDD reduction is realized with increasing Si concentration in the SiGe/Ge SL without changing the cycle of the SL. However, surface roughening due to pit formation occurs if the Si concentration in the SL is higher than 50% because of increased strain at the interfaces between SiGe and Ge. With increasing SiGe and Ge thickness ratio in the SL layer and maintaining periodicity and cycles, the TDD is reduced to 2.8 × 108 cm−2 without degrading the surface roughness. This improvement is related to a relaxation of the SiGe/Ge SL by plastic deformation.
(102) Emerging Terahertz Integrated Systems in Silicon
X. Yi, C. Wang, Z. Hu, J. Holloway, M.I.W. Khan, M.I. Ibrahim, M. Kim, G.C. Dogiamis, B. Perkins, M. Kaynak, R.T. Yazicigil, A.P. Chandrakassan, R. Han
IEEE Transactions on Circuits and Systems I 68(9), 3537 (2021)
DOI: 10.1109/TCSI.2021.3087604
Silicon-based terahertz (THz) integrated circuits (ICs) have made rapid progress over the past decade. The demonstrated basic component performance, as well as the maturity of design tools and methodologies, have made it possible to build high-complexity THz integrated systems. Such implementations are undoubtedly highly attractive due to their low cost and high integration capability; however, their unique characteristics, both advantageous and disadvantageous, also call for research investigations into unconventional systematic architectures and novel THz applications. In this paper, we review the current status and future trend of silicon-based THz ICs, with the focus on state-of-the-art THz microsystems for emerging sensing and communication applications in the last few years, such as high-resolution imaging, high medium/long-term stability time keeping, high-speed wireline/wireless communications, and miniaturization of RF tags, as well as THz packaging technologies.
(103) SiGe HBTs and BiCMOS Technology for Present and Future Millimeter-Wave Systems
T. Zimmer, J. Böck, F. Buchali, P. Chevalier, M. Collisi, B. Debaillie, M. Deng, P. Ferrari, S. Fregonese, C. Gaquiere, H. Ghanem, H. Hettrich, A. Karakuzulu, T. Maiwald, M. Margalef-Rovira, C. Maye, M. Möller, A. Mukherjee, H. Rücker, P. Sakalas, R. Schmid, K. Schneider, K. Schuh, W. Templ, A. Visweswaran, T. Zwick
IEEE Journal of Microwaves 1(1), 288 (2021)
DOI: 10.1109/JMW.2020.3031831
This paper gives an overall picture from BiCMOS technologies up to THz systems integration, which were developed in the European Research project TARANTO. The European high performance BiCMOS technology platforms are presented, which have special advantages for addressing applications in the submillimeter-wave and THz range. The status of the technology process is reviewed and the integration challenges are examined. A detailed discussion on millimeter-wave characterization and modeling is given with emphasis on harmonic distortion analysis, power and noise figure measurements up to 190 GHz and 325 GHz respectively and S-parameter measurements up to 500 GHz. The results of electrical compact models of active (HBTs) and passive components are presented together with benchmark circuit blocks for model verification. BiCMOS-enabled systems and applications with focus on future wireless communication systems and high-speed optical transmission systems up to resulting net data rates of 1.55 Tbit/s are presented.
O. Aktas, Y. Yamamoto, M. Kaynak, A.C. Peacock
Communication Physics 4, 132 (2021)
DOI: 10.1038/s42005-021-00632-1
Advanced solid-state devices, including lasers and modulators, require semiconductor heterostructures for nanoscale engineering of the electronic bandgap and refractive index. However, existing epitaxial growth methods are limited to fabrication of vertical heterostructures grown layer by layer. Here, we report the use of finite-element-method-based phase-field modelling with thermocapillary convection to investigate laser inscription of in-plane heterostructures within silicon-germanium films. The modelling is supported by experimental work using epitaxially-grown Si0.5Ge0.5 layers. The phase-field simulations reveal that various in-plane heterostructures with single or periodic interfaces can be fabricated by controlling phase segregation through modulation of the scan speed, power, and beam position. Optical simulations are used to demonstrate the potential for two devices: graded-index waveguides with Ge-rich (>70%) cores, and waveguide Bragg gratings with nanoscale periods (100–500 nm). Periodic heterostructure formation via sub-millisecond modulation of the laser parameters opens a route for post-growth fabrication of in-plane quantum wells and superlattices in semiconductor alloy films.
(2) Physical Attacks through the Chip Backside: Threats, Challenges and Opportunities
E. Amini, K. Bartels, C. Boit, M. Eggert, N. Herfurth, T. Kiyan, T. Krachenfels, J.-P. Seifert, S. Tajik
Proc. 39th Symposium on VLSI Technology and Circuits (VLSI Symposia 2021), (2021)
DOI: 10.1109/VTS50974.2021.9441006
(3) Bestimmung der optischen Konstanten und Streueigenschaften von transparenten Kunststoffen auf Polyurethanbasis für den Einsatz in der Optoelektronik
J. Bauer, O. Fursenko, F. Heinrich, M. Gutke, B. Dietzel, E. Kornejew, O. Broedel, A. Kaltenbach, M. Burkhardt, M. Edling, S. Pulwer, P. Steglich, M. Herzog, S. Schrader
Proc. 122. Tagung der DGaO (Deutsche Gesellschaft für angewandte Optik), A17 (2021)
(4) Impedance Matching in Dielectrophoresis Experiments
N. Boldt, D.E. Malti, S. Damm, A. Barai, M. Birkholz, R. Thewes
Proc. IEEE Biomedical Circuits and Systems Conference (BioCas 2021), (2021)
(Bioelectronics)
(5) Fiber-to-Chip Light Coupling using a Graded-Index Lensed Fiber Collimator
S. Bondarenko, M. Hülsemann, A. Mai, P. Steglich
Optical Engineering 60(1), 014105 (2021)
DOI: 10.1117/1.OE.60.1.014105
Fiber-to-chip light coupling using a graded-index (GRIN) fiber collimator is investigated. Our experiments with grating couplers and strip waveguides fabricated in a photonic integrated circuit technology reveal that the peak coupling efficiency of a GRIN fiber collimator is 7.8 dB lower than that of a single-mode fiber. However, the 3-dB alignment tolerance is improved by a factor of about 5.7 giving rise to pluggable sensor solutions. This work opens a path toward a cost-effective and portable sensor platform based on pluggable photonic biosensors using GRIN fiber collimators.
(6) A 239-298 GHz Power Amplifier in an Advanced 130 nm SiGe BiCMOS Technology for Communications Applications
T. Bücher, J. Grzyb, P. Hillger, H. Rücker, B. Heinemann, U.R. Pfeiffer
Proc. 47th European Solid-State Circuits Conference (ESSCIRC 2021), 369 (2021)
DOI: 10.1109/ESSCIRC53450.2021.9567853, (DFG-Dotseven2IC)
(7) An Academic Framework for IC Physical Design Algorithms Development
D. Bulakh, A. Korshunov, A. Datsuk
Proc. International Seminar on Electron Devices Design and Production (SED 2021), (2021)
DOI: 10.1109/SED51197.2021.9444528, (Design Kit)
(8) The Wafer-Level Package Integration of a K/ Ka Band Diplexer-on-PCB
Z. Cao, M. Stocchi, M. Wietstruck, M. Kaynak
Proc. International Microwave Filter Workshop (IMFW 2021), (2021)
(FLEXCOM)
(9) N-Type Ge/Si Antennas for THz Sensing
C.A. Chavarin, E. Hardt, S. Gruessing, O. Skibitzki, I. Costina, D. Spirito, W. Seifert, W.M. Klesse, C.L. Manganelli, C. You, J. Flesch, J. Piehler, M. Missori, L. Baldassarre, B. Witzigmann, G. Capellini
Optics Express 29(5), 7680 (2021)
DOI: 10.1364/OE.418382, (DFG-ESSENCE)
Ge-on-Si plasmonics holds the promise for compact and low-cost solutions in the manipulation of THz radiation. We discuss here the plasmonic properties of doped Ge bow-tie antennas made with a low-point cost CMOS mainstream technology. These antennas display resonances between 500 and 700 GHz, probed by THz Time Domain Spectroscopy. We show surface functionalization of the antennas with a thin layer of α-lipoic acid, that red-shifts the antenna resonances by about 20 GHz. Moreover, we show that also antennas covered with a protective silicon nitride cap layer exhibit a comparable red-shift when covered with the biolayer. This suggests that the electromagnetic fields at the hotspot extend well beyond the cap layer, enabling the possibility to use the antennas with an improved protection of the plasmonic material in conjunction with microfluidics.
(10) Biomolecule Sensing in THz Range with N-Ge/Si Antennas
C.A. Chavarin, A.A. Wiciak, E. Hardt, S. Gruessing, O. Skibitzki, I. Costina, W. Seifert, W.M. Klesse, C.L. Manganelli, C. You, J. Flesch, J. Piehler, M. Missori, W. Koczorowski, L. Baldassarre, B. Witzigmann, G. Capellini, D. Spirito
Proc. 46th International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz 2021), (2021)
DOI: 10.1109/IRMMW-THz50926.2021.9567579, (DFG-ESSENCE)
(11) An Integrated Development Environment for Robust Interoperable PDK Implementation
A. Datsuk, C. Wieden, D. Bulakh, T. Krupkina
Proc. IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus 2021), 2067 (2021)
DOI: 10.1109/ElConRus51938.2021.9396695
(12) A -115 dBc/Hz Integrated Optoelectronic Oscillator in a BiCMOS Silicon Photonic Technology
G. Dziallas, A. Fatemi, A. Peczek, M. Tarar, D. Kissinger, L. Zimmermann, A. Malignaggi, G. Kahmen
Proc. IEEE MTT-S International Microwave Symposium (IMS 2021), 23 (2021)
(13) Photonic Contact Thermometry using Silicon Ring Resonators and Tuneable Laser-based Spectroscopy
R. Eisermann, S. Krenek, G. Winzer, S. Rudtsch
tm-Technisches Messen 88(10), 640 (2021)
DOI: 10.1515/teme-2021-0054, (PhotOQant)
Photonic sensors offer the possibility of purely optical measurement in contact thermometry. In this work, silicon-based ring resonators were used for this purpose. These can be manufactured with a high degree of reproducibility and uniformity due to the established semiconductor manufacturing process. For the precise characterisation of these photonic sensors, a measurement setup was developed which allows laser-based spectroscopy around 1550 nm and stable temperature control from 5 °C to 95 °C. This was characterised in detail and the resulting uncertainty influences of both the measuring set-up and the data processing were quantified. The determined temperature stability at 20 °C is better than 0.51 mK for the typical acquisition time of 10 s for a 100 nm spectrum. For a measurement of >24 h at 30 °C a standard deviation of 2.6 mK could be achieved. A hydrogen cyanide reference gas cell was used for traceable in-situ correction of the wavelength. The determined correction function has a typical uncertainty of 0.6 pm. The resonance peaks of the ring resonators showed a high optical quality of 157 000 in the average with a filter depth of up to 20 dB in the wavelength range from 1525 nm to 1565 nm. When comparing different methods for the determination of the central wavelength of the resonance peaks, an uncertainty of 0.3 pm could be identified. A temperature-dependent shift of the resonance peaks of approx. 72 pm/K was determined. This temperature sensitivity leads together with the analysed uncertainty contributions to a repeatability of better than 10 mK in the analysed temperature range from 10 °C to 90 °C.
(14) Millimeter-Wave Amplifier-Based Noise Sources in SiGe BiCMOS Technology
H. Forsten, J.H. Saijets, M. Kantanen, M. Varonen, M. Kaynak, P. Piironen
IEEE Transactions on Microwave Theory and Techniques 69(11), 4689 (2021)
DOI: 10.1109/TMTT.2021.3104028
This article describes the development and characterization of wideband millimeter-wave noise sources based on SiGe BiCMOS amplifiers. Two single-ended three-stage amplifier-based noise sources reached excess noise ratio (ENR) values over 20 dB from 120 to 220 GHz with 20 mA of the bias current from a 2.3-V supply. We also introduce a novel switchable noise source employing the Lange coupler for providing wideband matching in both ON and OFF configurations of the noise source. The Lange coupler-based noise source has better than 12-dB matching from 90 to 270 GHz with an ENR of better than 15 dB from 125 to 235 GHz.
(15) Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance
S. Fregonese, C. Mukherjee, H. Rücker, P. Chevalier, G.G. Fischer, D. Celi, M. Deng, F. Marc, C. Maneux, T. Zimmer
Proc. IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS 2021), (2021)
(SG13G3)
(16) Modeling and Analysis of the Electrolyte Voltage Drop in Dielectrophoresis Actuators
A. Frey, N. Boldt, A. Barai, M. Birkholz, I. Kuehne, R. Thewes
Proc. IEEE Biomedical Circuits and Systems Conference (BioCas 2021), (2021)
(Bioelectronics)
(17) 2D Grating Coupler Induced Polarization Crosstalk in Coherent Transceivers for Next Generation Data Center Interconnects
G. Georgieva, P.M. Seiler, Ch. Mai, K. Petermann, L. Zimmermann
Proc. Optical Fiber Communications Conference and Exhibition (OFC 2021), W1C.4 (2021)
(18) A 112 Gb/s Radiation-Hardened Mid-Board Optical Transceiver in 130-nm SiGe BiCMOS for Intra-Satellite Links
S. Giannakopoulos, I. Sourikopoulos, L. Stampoulidis, P. Ostrovskyy, F. Teply, K. Tittelbach-Helmrich, G. Panic, G. Fischer, A. Grabowski, H. Zirath, P. Ayzac, N. Venet, A. Maho, M. Sotom, S. Jones, G. Wood, I. Oxtoby
Frontiers in Physics 9, 672941 (2021)
DOI: 10.3389/fphy.2021.672941, (SIPhoDiAS)
We report the design of a 112 Gb/s radiation-hardened (RH) optical transceiver applicable to intra-satellite optical interconnects. The transceiver chipset comprises a vertical-cavity surface-emitting laser (VCSEL) driver and transimpedance amplifier (TIA) integrated circuits (ICs) with four channels per die, which are adapted for a flip-chip assembly into a mid-board optics (MBO) optical transceiver module. The ICs are designed in the IHP 130 nm SiGe BiCMOS process (SG13RH) leveraging proven robustness in radiation environments and high-speed performance featuring bipolar transistors (HBTs) with fT/fMAX values of up to 250/340 GHz. Besides hardening by technology, radiation-hardened-by-design (RHBD) components are used, including enclosed layout transistors (ELTs) and digital logic cells. We report design features of the ICs and the module, and provide performance data from post-layout simulations. We present radiation evaluation data on analog devices and digital cells, which indicate that the transceiver ICs will reliably operate at typical total ionizing dose (TID) levels and single event latch-up thresholds found in geostationary satellites.
(19) BEOL Modifications of a 130 nm SiGe BiCMOS Technology for Monolithic Integration of Thin-Film Wafer-Level Encapsulated D-Band RFMEMS Switches
A. Göritz, S. Tolunay Wipf, M. Wietstruck, M. Kaynak, M. Fraschke, A. Krüger, M. Lisker
23rd IEEE Design, Test, Integration & Packaging of MEMS/MOEMS (DTIP 2021), (2021)
DOI: 10.1109/DTIP54218.2021.9568672
(20) Functionalization of Oxide-Free Silicon Surfaces for Biosensing Applications
A. Henriksson, P. Neubauer, M. Birkholz
Advanced Materials Interfaces 2100927 (2021)
DOI: 10.1002/admi.202100927, (Bioelectronics)
As an alternative to standard silicon biofunctionalization protocol based on alkoxysilanes that bind to SiO2 on oxidized silicon substrates, several protocols to form bifunctional interlayers that directly bind to the silicon surface via a strong Si-C bond have been developed during the last decades. These interlayers are more stable, and the lack of an insulating layer between the substrate and the interlayer reduces electric noise in biosensor devices.
Si-C monolayers are not yet regularly applied as the protocols are more complex and generally require an inert gas atmosphere. However, a variety of applications and new methods to form bifunctional Si-C interlayers were recently developed. Here, we review the role these innovative protocols and interlayers can play in biofunctionalization of silicon surfaces and report their applications in electrochemical, microelectromechanical and optical biosensing. From the analysis of the current situation, it can be concluded that the advantageous properties offered with this approach in many cases more than outweigh the additional processes to form Si-C bonded interlayers and the approach is predicted expand the applications of future silicon-based biosensors.
(21) Design, Simulations and Manufacturing of a Microring Resonator Biosensor Assisted by Dielectrophoresis
A. Henriksson, M. Jäger, L. Kasper, P. Neubauer, M. Birkholz
Proc. 3rd European BioSensor Symposium (EBS 2021), abstr. (2021)
(22) Meticulous SPEM System Calibration as a Key for Extracting Correct Photon Emission Spectra
N. Herfurth, C. Boit
Proc. 28th edition of the IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2021), (2021)
DOI: 10.1109/IPFA53173.2021.9617231
(23) Erratum to “High-Power Radiation at 1 THz in Silicon: A Fully Scalable Array Using a Multi-Functional Radiating Mesh Structure”
Z. Hu, M. Kaynak, R. Han
IEEE Journal of Solid-State Circuits 56(10), 3202 (2021)
DOI: 10.1109/JSSC.2021.3080556
In the above article [1] , in (19) , a factor of 2 is missing. Equations (6) , (8) , and (19) – (27) are impacted by this error. The corrected text from the line above (19) in the Appendix of [1] is as follows.
(24) Performance Comparison of Broadband Traveling Wave Amplifiers in 130 nm SiGe:C SG13G2 and SG13G3 BiCMOS Technologies
M. Inac, A. Fatemi, F. Korndörfer, H. Rücker, F. Gerfers, A. Malignaggi
Proc. IEEE MTT-S International Microwave Symposium (IMS 2021), (2021)
(25) Performance Comparison of Broadband Traveling Wave Amplifiers in 130 nm SiGe:C SG13G2 and SG13G3 BiCMOS Technologies
M. Inac, A. Fatemi, F. Korndörfer, H. Rücker, F. Gerfers, A. Malignaggi
IEEE Microwave and Wireless Components Letters 31(6), 744 (2021)
DOI: 10.1109/LMWC.2021.3067099
In this letter, a comparison between two ultra-wideband traveling wave amplifiers (TWAs) designed in two different SiGe:C technologies consuming only 500 mW is presented. The first design utilizes the IHP’s 130-nm SiGe:C BiCMOS SG13G2 technology, featuring fT /fMAX =300 /500 GHz, while the second design uses the IHP’s 130-nm SiGe:C BiCMOS SG13G3 technology, featuring fT /fMAX =470/700 GHz. For a fair comparison, the same architecture has been used for the design of both amplifiers. On-wafer measurements of the SG13G2 amplifier show 15.3 dB gain and 87.4 GHz bandwidth, while the design in SG13G3 technology reaches 16.9 dB gain and more than 110 GHz bandwidth. There is a 1% difference in the output power efficiency where it is 4.1% and 5.1% on SG13G2 and SG13G3 technologies, respectively. In both cases, time-domain measurements show a reliable 120 Gbps non-return-to-zero (NRZ) operation. The presented SG13G3-based TWA shows state-of-the-art performance among similar SiGe BiCMOS amplifiers.
(26) Parametric Monte-Carlo Characterization of Si Ring Modulators
Y. Jo, Y. Ji, M. Kim, St. Lischke, Ch. Mai,L. Zimmermann, W.-Y. Choi
Proc. IEEE 17th International Conference on Group IV Photonics (GFP 2021)
DOI: 10.1109/GFP51802.2021.9673952, (MPW_ePIC)
(27) Modulation Linearity Characterization of Si Ring Modulators
Y. Jo, Ch. Mai, St. Lischke, L. Zimmermann, W.-Y- Choi
IEEE Journal of Lightwave Technology 39(24), 7842 (2021)
DOI: 10.1109/JLT.2021.3093463
Modulation linearity of Si ring modulators (RMs) is investigated through the numerical simulation based on the coupled-mode theory and experimental verification. Numerical values of the key parameters needed for the simulation are experimentally extracted. Simulation and measurement results agree well. With these, the influence of input optical wavelength and power on the Si RM linearity are characterized.
(28) Numerical Optimization and CW Measurements of SOI Waveguides for Ultra-Broadband C-to-O-Band Conversion
T. Kernetzky, G. Ronniger, U. Höfler, L. Zimmermann, N. Hanik
Proc. 47th European Conference Optical Communications (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9605944, (DFG ULTRA)
(29) Silicon Electronic-Photonic Integrated 25-Gb/s Ring Modulator Transmitter with a Built-In Temperature Controller
M. Kim, M.-H. Kim, Y. Jo, H.-K. Kim, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
Photonics Research 9(4), 507 (2021)
DOI: 10.1364/PRJ.413407
We demonstrate a silicon electronic-photonic integrated 25-Gb/s non-return-to-zero transmitter that includes driver circuits, depletion-type Si ring modulator, Ge photodetector, temperature sensor, on-chip heater, and temperature controller, all monolithically integrated on 0.25-μm photonic BiCMOS technology platform. The integrated transmitter successfully provides stable and optimal 25-Gb/s modulation characteristics against any external temperature fluctuation.
(30) Terahertz Signal Source and Receiver Operating Near 600 GHz and their 3-D Imaging Application
J. Kim, D. Yoon, H. Son, D. Kim, J. Yoo, J. Yun, H.J. Ng, M. Kaynak, J.-S. Rieh
IEEE Transactions on Microwave Theory and Techniques 69(5), 2762 (2021)
DOI: 10.1109/TMTT.2021.3061596
In this article, a set of oscillators and a heterodyne image receiver operating near 600 GHz have been developed, each based on a 250-nm InP heterojunction bipolar transistor (HBT) technology and a 130-nm SiGe HBT technology, respectively. The oscillators are based on the common-base cross-coupled push-push topology, which employed coupled-line loads for improved output power and efficiency with a small area. The measured oscillation frequency ranges of the three oscillators with different coupled-line lengths were 628-682, 556-610, and 509-548 GHz, respectively, with a tuning capability achieved with bias variation. The maximum output power and the dc-to-RF efficiency achieved with the oscillators were -10 dBm and 0.19%, respectively. The heterodyne receiver, which consists of a mixer, an IF amplifier, and an IF detector, exhibited a maximum responsivity of 469 kV/W and a minimum noise equivalent power (NEP) of 0.64 pW/Hz1/2. A transmission-mode 3-D THz tomography imaging setup was established with one of the fabricated oscillators and the heterodyne receiver employed as the signal source and the image detector, respectively. With the imaging setup, a successful reconstruction of 3-D images of a target object was demonstrated based on the filtered back-projection algorithm.
(31) Si Photonic-Electronic Monolithically Integrated Optical Receiver with a Built-In Temperature-Controlled Wavelength Filter
H.-K. Kim, M. Kim, M.-H. Kim, Y. Jo, St. Lischke, Ch. Mai, L. Zimmermann, W. Choi
Optics Express 29(6), 9565 (2021)
DOI: 10.1364/OE.418222
We present a Si photonic-electronic integrated ring-resonator based optical receiver that contains a temperature-controlled ring-resonator filter (RRF), a Ge photodetector, and receiver circuits in a single chip. The temperature controller automatically determines the RRF temperature at which the maximum transmission of the desired WDM signal is achieved and maintains this condition against any temperature or input wavelength fluctuation. This Si photonic-electronic integrated circuit is realized with 0.25-µm photonic BiCMOS technology, and its operation is successfully confirmed with measurement.
(32) A Temperature-Aware Large-Signal SPICE Model for Depletion-Type Silicon Ring Modulators
M. Kim, Y. Jo, St. Lischke, Ch. Mai, L. Zimmermann, W.-Y. Choi
IEEE Photonics Technology Letters 33(17), 947 (2021)
DOI: 10.1109/LPT.2021.3098760
We present a large-signal SPICE model for the depletion-type silicon ring (RM) modulator that includes temperature dependence. The model is based on the temperature-dependent equivalent circuit for the RM and allows easy simulation of RM modulation characteristics in SPICE. The accuracy of the model is verified with the measurement results of 25-Gb/s NRZ modulation at several different temperatures. In addition, simulation of the temperature-dependent transient responses of the RM together with the RM temperature control circuit is demonstrated in the standard IC design environment.
(33) Plasmonics - High-Speed Photonics for Co-Integration with Electronics
U. Koch, C. Uhl, H. Hettrich, Y. Fedoryshyn, D. Moor, M. Baumann, C. Hoessbacher, W. Heni, B. Baeuerle, B.I. Bitachon, A. Josten, M. Ayata, H. Xu, D.L. Elder, L.R. Dalton, E. Mentovich, P. Bakopoulos, St. Lischke, A. Krüger, L. Zimmermann, D. Tsiokos, N. Pleros, M. Möller, J. Leuthold
Japanese Journal of Applied Physics 60(SB), SB0806 (2021)
DOI: 10.35848/1347-4065/abef13
New high-speed photonic technologies and co-integration with electronics are required to keep up with the demand of future optical communication systems. In this paper, plasmonics is presented as one of the most promising next-generation photonic technologies that already fulfils these requirements in proof-of-concept demonstrations. Plasmonics features not only modulators and detectors of highest speed, but also compactness, cost- and energy-efficiency, and compatibility with CMOS electronics. Recently, co-integration with electronics was demonstrated with record performances of 222 GBd in a hybrid InP electronic-plasmonic transmitter assembly and of 120 GBd with a monolithic BiCMOS electronic-plasmonic transmitter.
(34) Cross-Layer Digital Design Flow for Space Applications
M. Krstic, M. Andjelkovic, O. Schrape, A. Breitenreiter, J.-C. Chen, A. Balashov, A. Simevski
Proc. 32nd International Conference on Microelectronics (MIEL 2021), 45 (2021)
DOI: 10.1109/MIEL52794.2021.9569065, (MORAL)
(35) Cross-Layer Digital Design Flow for Space Applications
M. Krstic, M. Andjelkovic, O. Schrape, A. Breitenreiter, J.-C. Chen, A. Balashov, A. Simevski
Proc. 32nd International Conference on Microelectronics (MIEL 2021), 45 (2021)
DOI: 10.1109/MIEL52794.2021.9569065, (ELICSIR)
(36) Cross-Layer Digital Design Flow for Space Applications
M. Krstic, M. Andjelkovic, O. Schrape, A. Breitenreiter, J.-C. Chen, A. Balashov, A. Simevski
Proc. 32nd International Conference on Microelectronics (MIEL 2021), 45 (2021)
DOI: 10.1109/MIEL52794.2021.9569065, (Space Region)
(37) Very High-Speed Waveguide Integrated Germanium Photo Detectors
St. Lischke, A. Peczek, D. Steckler, F. Korndörfer, J. Morgan, A. Beling, L. Zimmermann
Proc. 47th European Conference on Optical Communication (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9606091, (plaCMOS)
(38) Ultra-Fast Germanium Photodiode with 3-dB Bandwidth of 265 GHz
St. Lischke, A. Peczek, J.S. Morgan, K. Sun, D. Steckler, Y. Yamamoto, F. Korndörfer, Ch. Mai, St. Marschmeyer, M. Fraschke, A. Krüger, A. Beling, L. Zimmermann
Nature Photonics 15, 925 (2021)
DOI: 10.1038/s41566-021-00893-w, (plaCMOS)
On a scalable silicon technology platform, we demonstrate photodetectors matching or even surpassing state-of-the-art III–V devices. As key components in high-speed optoelectronics, photodetectors with bandwidths greater than 100 GHz have been a topic of intense research for several decades. Solely InP-based detectors could satisfy the highest performance specifications. Devices based on other materials, such as germanium-on-silicon devices, used to lag behind in speed, but enabled complex photonic integrated circuits and co-integration with silicon electronics. Here we demonstrate waveguide-coupled germanium photodiodes with optoelectrical 3-dB bandwidths of 265 GHz and 240 GHz at a photocurrent of 1 mA. This outstanding performance is achieved by a novel device concept in which a germanium fin is sandwiched between complementary in situ-doped silicon layers. Our photodetectors show internal responsivities of 0.3 A W−1 (265 GHz) and 0.45 A W−1 (240 GHz) at a wavelength of 1,550 nm. The internal bandwidth–efficiency product of the latter device is 86 GHz. Low dark currents of 100–200 nA are obtained from these ultra-fast photodetectors.
(39) Waveguide-Coupled Ge Photodiodes with 3-dB Bandwidth ≥110 GHz
St. Lischke, A. Peczek, D. Steckler, F. Korndörfer, Ch. Mai, L. Zimmermann
Proc. IEEE Photonics Conference (IPC 2021), (2021)
DOI: 10.1109/IPC48725.2021.9593030, (PEARLS)
(40) Waveguide-Coupled Ge Photodiodes with 3-dB Bandwidth ≥110 GHz
St. Lischke, A. Peczek, D. Steckler, F. Korndörfer, Ch. Mai, L. Zimmermann
Proc. IEEE Photonics Conference (IPC 2021), (2021)
DOI: 10.1109/IPC48725.2021.9593030, (DFG EPIDAC)
(41) Waveguide-Coupled Ge Photodiodes with 3-dB Bandwidth ≥110 GHz
St. Lischke, A. Peczek, D. Steckler, F. Korndörfer, Ch. Mai, L. Zimmermann
Proc. IEEE Photonics Conference (IPC 2021), (2021)
DOI: 10.1109/IPC48725.2021.9593030, (plaCMOS)
(42) Epitaxial GeSn/Ge Vertical Nanowires for P-Type Field-Effect Transistors with Enhanced Performance
M. Liu, D. Yang, A. Shkurmanov, J.H. Bae, V. Schlykow, J.-M. Hartmann, Z. Ikonic, F. Bärwolf, I. Costina, A. Mai, J. Knoch, D. Grützmacher, D. Buca, Q.-T. Zhao
ACS Applied Nano Materials 4(1), 94 (2021)
DOI: 10.1021/acsanm.0c02368
Harvesting the full potential of single-crystal semiconductor nanowires (NWs) for advanced nanoscale field-effect transistors (FETs) requires a smart combination of charge control architecture and functional semiconductors. In this article, high-performance vertical gate-all-around NW p-type FETs (p-FETs) are presented. The device concept is based on advanced Ge0.92Sn0.08/Ge group IV epitaxial heterostructures, employing quasi–one-dimensional semiconductor NWs fabricated with a top-down approach. The advantage of using a heterostructure is the possibility of electronic band engineering with band offsets tunable by changing the semiconductor stoichiometry and elastic strain. The use of a Ge0.92Sn0.08 layer as the source in GeSn/Ge NW p-FETs results in a small subthreshold slope of 72 mV/dec and a high ION/IOFF ratio of 3 × 106. A ∼32% drive current enhancement is obtained compared to the vertical Ge homojunction NW control devices. More interestingly, the drain-induced barrier lowering is much smaller with GeSn instead of Ge as the source. The general improvement of the transistor’s key figures of merits originates from the valence band offset at the Ge0.92Sn0.08/Ge heterojunction, as well as from a smaller NiGeSn/GeSn contact resistivity.
(43) Influence of Plasma Treatment on SiO2/Si and Si3N4/Si Substrates for Large-Scale Transfer of Graphene
R. Lukose, M. Lisker, F. Akhtar, M. Fraschke, T. Grabolla, A. Mai, M. Lukosius
Scientific Reports 11, 13111 (2021)
DOI: 10.1038/s41598-021-92432-4, (GIMMIK)
One of the limiting factors of graphene integration into electronic, photonic, or sensing devices is the unavailability of large-scale graphene directly grown on the isolators. Therefore, it is necessary to transfer graphene from the donor growth wafers onto the isolating target wafers. In the present research, graphene was transferred from the chemical vapor deposited 200mm Germanium/Silicon (Ge/Si) wafers onto isolating (SiO2/Si and Si3N4/Si) wafers by electrochemical delamination procedure, employing poly(methylmethacrylate) as an intermediate support layer. In order to influence the adhesion properties of graphene, the wettability properties of the target substrates were investigated in this study. To increase the adhesion of the graphene on the isolating surfaces, they were pre-treated with oxygen plasma prior the transfer process of graphene. The wetting contact angle measurements revealed the increase of the hydrophilicity after surface interaction with oxygen plasma, leading to improved adhesion of the graphene on 200 mm target wafers and possible proof-of-concept development of graphene-based devices in standard Si technologies.
(44) Measurements and Analysis of Different Front-End Configurations for Monolithic SiGe BiCMOS Pixel Detectors for HEP Applications
F. Martinelli, C. Magliocca R. Cardella,E. Charbon, G. Iacobucci, M. Nessi, L. Paolozzi, H. Rücker, P. Valerio
Journal of Instrumentation 16, 12038 (2021)
DOI: 10.1088/1748-0221/16/12/P12038, (SG13G3)
This paper presents a small-area monolithic pixel detector ASIC designed in 130 nm SiGe BiCMOS technology for the upgrade of the pre-shower detector of the FASER experiment at CERN. The purpose of this prototype is to study the integration of fast front-end electronics inside the sensitive area of the pixels and to identify the configuration that could satisfy at best the specifications of the experiment. Self-induced noise, instabilities and cross-talk were minimised to cope with the several challenges associated to the integration of pre-amplifiers and discriminators inside the pixels. The methodology used in the characterisation and the design choices will also be described. Two of the variants studied here will be implemented in the pre-production ASIC of the FASER experiment pre-shower for further tests.
(45) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (Total Resilience)
(46) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (KI-PRO)
(47) Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits
V. Milo, A. Glukhov, E. Perez, C. Zambelli, N. Lepri, M.K. Mahadevaiah, E. Perez-Bosch Quesada, P. Olivo, Ch. Wenger, D. Ielmini
IEEE Transactions on Electron Devices 68(8), 3832 (2021)
DOI: 10.1109/TED.2021.3089995, (Neutronics)
Resistive switching memory (RRAM) is a promising technology for embedded memory and their application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations which might cause a degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slope in the programming characteristics. We test the accuracy of a 2-layer fully-connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a trade-off between the FC-NN accuracy, size and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.
(48) Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks
V. Milo, F. Anzalone, C. Zambelli, E. Perez, M.K. Mahadevaiah, O.G. Ossorio, P. Olivo, Ch. Wenger, D. Ielmini
Proc. International Reliability Physics Symposium (IRPS 2021), (2021)
DOI: 10.1109/IRPS46558.2021.9405119, (NeuroMem)
(49) Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits
V. Milo, A. Glukhov, E. Perez, C. Zambelli, N. Lepri, M.K. Mahadevaiah, E. Perez-Bosch Quesada, P. Olivo, Ch. Wenger, D. Ielmini
IEEE Transactions on Electron Devices 68(8), 3832 (2021)
DOI: 10.1109/TED.2021.3089995, (Total Resilience)
Resistive switching memory (RRAM) is a promising technology for embedded memory and their application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations which might cause a degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slope in the programming characteristics. We test the accuracy of a 2-layer fully-connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a trade-off between the FC-NN accuracy, size and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.
(50) High Frequency Magnetic Sheet Materials – Performance Factor Comparisons and Design of Toroidal Inductors Embedded in PCB
R. Murphy, P. McCloskey, Z. Cao, C. Ó Mathúna, S. ODriscoll
Proc. IEEE Applied Power Electronics Conference and Exposition (APEC 2021), 2897 (2021)
DOI: 10.1109/APEC42165.2021.9487131, (GaNonCMOS)
(51) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10, 083002 (2021)
Proc. 239th ECS Meeting (2021)
(NeuroMem)
(52) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10, 083002 (2021)
Proc. 239th ECS Meeting (2021)
(Total Resilience)
(53) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10, 083002 (2021)
Proc. 239th ECS Meeting (2021)
(KI-PRO)
(54) Performance Assessment of Amorphous HfO2-Based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Dueñas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Journal of Solid State Science and Technology 10(8), 083002 (2021)
DOI: 10.1149/2162-8777/ac175c
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.
(55) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
DOI: 10.1149/10202.0029ecst, (NeuroMem)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.
(56) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
DOI: 10.1149/10202.0029ecst, (Total Resilience)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.
(57) Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
O.G. Ossorio, G. Vinuesa, H. Garcia, B. Sahelices, S. Duenas, H. Castan, E. Perez, M.K. Mahadevaiah, Ch. Wenger
ECS Transactions 102(2), 29 (2021)
DOI: 10.1149/10202.0029ecst, (KI-PRO)
The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.
(58) A High-Gain SiGe BiCMOS LNA for 5G In-Band Full-Duplex Applications
T.A. Ozkan, A. Burak, I. Kalyoncu, M. Kaynak, Y. Gurbuz
Proc. 15th European Microwave Integrated Circuits Conference (EuMIC 2020), 53 (2021)
(59) A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells
S. Pechmann, T. Mai, M. Völkel, M.K. Mahadevaiah, E. Perez, E. Perez-Bosch Quesada, M. Reichenbach, Ch. Wenger, A. Hagelauer
Electronics (MDPI) 10(5), 530 (2021)
DOI: 10.3390/electronics10050530, (KI-PRO)
In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.
(60) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (Neutronics)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.
(61) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (KI-PRO)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.
(62) Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
E. Perez, A.J. Perez-Avila, R. Romero-Zaliz, M.K. Mahadevaiah, E. Perez-Bosch Quesada, J.B. Roldan, F. Jimenez-Molinos, Ch. Wenger
Electronics (MDPI) 10(9), 1084 (2021)
DOI: 10.1016/j.mee.2019.05.004, (Total Resilience)
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8x8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6 % compared with the use of non-optimized parameters.
(63) Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
E. Perez-Bosch Quesada, R. Romero-Zaliz, E. Perez, M.K. Mahadevaiah, J. Reuben, M.A. Schubert, F. Jimenez-Molinos, J.B. Roldan, Ch. Wenger
Electronics (MDPI) 10(6), 645 (2021)
DOI: 10.3390/electronics10060645, (NeuroMem)
In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.
(64) Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
E. Perez-Bosch Quesada, R. Romero-Zaliz, E. Perez, M.K. Mahadevaiah, J. Reuben, M.A. Schubert, F. Jimenez-Molinos, J.B. Roldan, Ch. Wenger
Electronics (MDPI) 10(6), 645 (2021)
DOI: 10.3390/electronics10060645, (Total Resilience)
In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.
(65) Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
E. Perez-Bosch Quesada, R. Romero-Zaliz, E. Perez, M.K. Mahadevaiah, J. Reuben, M.A. Schubert, F. Jimenez-Molinos, J.B. Roldan, Ch. Wenger
Electronics (MDPI) 10(6), 645 (2021)
DOI: 10.3390/electronics10060645, (KI-PRO)
In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.
(66) Memristive-Based In-Memory Computing: From Device to Large-Scale CMOS Integration
E. Perez-Bosch Quesada, E. Perez, M.K Mahadevaiah, Ch. Wenger
Neuromorphic Computing and Engineering 1(2), 024006 (2021)
DOI: 10.1088/2634-4386/ac2cd4
With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal-insulator-metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments.
(67) Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays
E. Perez, M.K. Mahadevaiah, E. Perez-Bosch Quesada, Ch. Wenger
IEEE Transactions on Electron Devices 68(6), 2693 (2021)
DOI: 10.1109/TED.2021.3072868, (Neutronics)
Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.
(68) Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays
E. Perez, M.K. Mahadevaiah, E. Perez-Bosch Quesada, Ch. Wenger
IEEE Transactions on Electron Devices 68(6), 2693 (2021)
DOI: 10.1109/TED.2021.3072868, (Total Resilience)
Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.
(69) Sensitivity of HfO2-based RRAM Cells to Laser Irradiation
D. Petryk, Z. Dyka, E. Perez, I. Kabin, J. Katzer, J. Schäffner, P. Langendörfer
Microprocessors and Microsystems 87, 104376 (2021)
(RESCUE)
(70) Efficient Ultra-Broadband C-to-O Band Converter Based on Multi-Mode Silicon-on-Insulator Waveguides
G. Ronniger, I. Sackey, T. Kernetzky, U. Höfler, Ch. Mai, C. Schubert, N. Hanik, L. Zimmermann, R. Freund, K. Petermann
Proc. 47th European Conference on Optical Communications (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9606033, (DFG ULTRA)
(71) Synthesis of a Tunable Ring Filter: Proof-of-Concept with Fixed Implementations at D-Band
P. Rynkiewicz, A.-L. Franc, F. Coccetti, M. Wietstruck, M. Kaynak, G. Prigent
International Journal of RF and Microwave Computer-Aided Engineering 31(9), e22761 (2021)
DOI: 10.1002/mmce.22761
The working frequencies of telecommunication systems are rapidly increasing and sub-THz applications will soon be required. In that context, the current article presents the synthesis of a tunable ring filter. The considered filter introduces a new degree of freedom that allows to meet targeted specifications in terms of central frequency and bandwidth. Thanks to a capacitor displacement, the equivalent characteristic impedance can be tuned independently of its equivalent electrical length. The existing filter synthesis is modified to take this concept into account and thus provide a synthesis tunable in central frequency and bandwidth. The proof-of-concept of the design procedure is achieved in SiGe BiCMOS 0.25 μm technology with the implementation and measurement of eight non-tunable circuits in the D-band.
(72) Reliable Technology Evaluation of SiGe HBTs and MOSFETs: fMAX Estimation from Measured Data
B. Saha, S. Fregonese, B. Heinemann, P. Scheer, P. Chevalier, K. Aufinger, A. Chakravorty, T. Zimmer
IEEE Electron Device Letters 42(1), 14 (2021)
DOI: 10.1109/LED.2020.3040891, (Taranto)
Maximumoscillation frequency (fMAX) of mmwave transistors is one of the key figures of merit (FOMs) for evaluating the HF-performance of a given technology. However, accurate measurements of fMAX are very difficult. Determination of fMAX is significantly affected by the measurement uncertainties in the admittance (y) parameters. In order to get rid of the random measurement error and to obtain a reliable and stable fMAX value, the frequency dependent y-parameters are described by rational functions formulated from the small-signal hybrid -model of the transistor under investigation. The parameters of these functions are determined following a least square error technique that minimizes the functional error with the measured data. The approach is especially useful for a fast and reliable evaluation of fMAX value. Devices from two different SiGe and an FDSOI (Fully Depleted Silicon On Insulator) MOS technology are measured and stable fMAX values are estimated following this approach.
(73) Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops
O. Schrape, M. Andjelkovic, A. Breitenreiter, St. Zeidler, A. Balashov, M. Krstic
IEEE Transactions on Circuits and Systems I 68(11), 4796 (2021)
DOI: 10.1109/TCSI.2021.3109080, (Scale4Edge)
Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ( 32.4 MeV⋅cm2/mg ) to ( 62.5 MeV⋅cm2/mg ), depending on the variant.
(74) Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops
O. Schrape, M. Andjelkovic, A. Breitenreiter, St. Zeidler, A. Balashov, M. Krstic
IEEE Transactions on Circuits and Systems I 68(11), 4796 (2021)
DOI: 10.1109/TCSI.2021.3109080, (MORAL)
Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ( 32.4 MeV⋅cm2/mg ) to ( 62.5 MeV⋅cm2/mg ), depending on the variant.
(75) Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops
O. Schrape, M. Andjelkovic, A. Breitenreiter, St. Zeidler, A. Balashov, M. Krstic
IEEE Transactions on Circuits and Systems I 68(11), 4796 (2021)
DOI: 10.1109/TCSI.2021.3109080, (SPAD)
Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ( 32.4 MeV⋅cm2/mg ) to ( 62.5 MeV⋅cm2/mg ), depending on the variant.
(76) Power Efficiency Improvements in Coherent O-Band Data Center Interconnects
P.M. Seiler, L. Zimmermann
Proc. Photonics in Switching and Computing (PSC 2021), Tu4C.3 (2021)
(77) Towards Coherent O-Band Data Center Interconnects
P.M. Seiler, G. Georgieva, G. Winzer, A. Peczek, K. Voigt, St. Lischke, A. Fatemi, L. Zimmermann
Frontiers of Optoelectronics (2021)
DOI: 10.1007/s12200-021-1242-0, (DFG EPIDAC)
Upcoming generations of coherent intra-/inter data center interconnects currently lack a clear path towards a reduction of cost and power consumption, which are the driving factors for these data links. In this work, the trade-offs associated with a transition from coherent C-band to O-band silicon photonics are addressed and evaluated. The discussion includes the fundamental components of coherent data links, namely the optical components, fiber link and transceivers. As a major component of these links, a monolithic silicon photonic BiCMOS O-band coherent receiver is evaluated for its potential performance and compared to an analogous C-band device in the same technology.
(78) Ultra-Wideband Silicon Photonic BiCMOS Coherent Receiver for O- and C-Band
P.M. Seiler, K. Voigt, St. Lischke, A. Malignaggi, L. Zimmermann
Proc. 47th European Conference on Optical Communications (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9606051, (ORIONAS)
(79) Ultra-Wideband Silicon Photonic BiCMOS Coherent Receiver for O- and C-Band
P.M. Seiler, K. Voigt, St. Lischke, A. Malignaggi, L. Zimmermann
Proc. 47th European Conference on Optical Communications (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9606051, (DFG EPIDAC)
(80) Ultra-Wideband Silicon Photonic BiCMOS Coherent Receiver for O- and C-Band
P.M. Seiler, K. Voigt, St. Lischke, A. Malignaggi, L. Zimmermann
Proc. 47th European Conference on Optical Communications (ECOC 2021), (2021)
DOI: 10.1109/ECOC52684.2021.9606051, (PEARLS)
(81) Towards Coherent O-Band Data Center Interconnects
P.M. Seiler, G. Georgieva, G. Winzer, A. Peczek, K. Voigt, St. Lischke, A. Fatemi, L. Zimmermann
Frontiers of Optoelectronics (2021)
DOI: 10.1007/s12200-021-1242-0, (ORIONAS)
Upcoming generations of coherent intra-/inter data center interconnects currently lack a clear path towards a reduction of cost and power consumption, which are the driving factors for these data links. In this work, the trade-offs associated with a transition from coherent C-band to O-band silicon photonics are addressed and evaluated. The discussion includes the fundamental components of coherent data links, namely the optical components, fiber link and transceivers. As a major component of these links, a monolithic silicon photonic BiCMOS O-band coherent receiver is evaluated for its potential performance and compared to an analogous C-band device in the same technology.
(82) Towards Coherent O-Band Data Center Interconnects
P.M. Seiler, G. Georgieva, G. Winzer, A. Peczek, K. Voigt, St. Lischke, A. Fatemi, L. Zimmermann
Frontiers of Optoelectronics (2021)
DOI: 10.1007/s12200-021-1242-0, (PEARLS)
Upcoming generations of coherent intra-/inter data center interconnects currently lack a clear path towards a reduction of cost and power consumption, which are the driving factors for these data links. In this work, the trade-offs associated with a transition from coherent C-band to O-band silicon photonics are addressed and evaluated. The discussion includes the fundamental components of coherent data links, namely the optical components, fiber link and transceivers. As a major component of these links, a monolithic silicon photonic BiCMOS O-band coherent receiver is evaluated for its potential performance and compared to an analogous C-band device in the same technology.
(83) JICG CMOS Transistors for Reduction of Total Ionizing Dose and Single Event Effects in a 130 nm Bulk SiGe BiCMOS Technology
R. Sorge, J. Schmidt, Ch. Wipf, F. Reimer, F. Teply, F. Korndörfer
Nuclear Instruments and Methods in Physics Research Section A 987, 164832 (2021)
DOI: 10.1016/j.nima.2020.164832, (Total Resilience)
We report on a novel radiation hardening by design (RHBD) approach for mitigation of total ionization dose (TID) induced drain leakage currents and single event transient (SET) in digital circuits fabricated in a 130 nm bulk SiGe BiCMOS technology. In order to avoid significant TID induced increase of drain leakage currents for NMOS transistors and channel pinch-off for PMOS transistors due to positive charges trapped at the lateral shallow trench insulator silicon interface we introduced junction isolation (JI) for the lateral MOS channel regions. The device construction measures applied also support to suppress the generation SETs. The tolerance of JI MOS transistors against TID induced drain leakage currents was verified up to a TID > 1.3 Mrad(Si). SET tests performed at four different inverter types varying in the arrangement the deep well in the layout. For CMOS inverters with isolated NMOS transistors a LET threshold > 130 MeV cm2 mg−1 was obtained.
(84) The H2020-SPACE-ORIONAS Project: “Lasercom-on-Chip” for High-Speed Satellite Constellation Interconnectivity
L. Stampoulidis, A. Osman, I. Sourikopoulos, G. Winzer, L. Zimmermann, A. Maho, M. Faugeron, M. Sotom, F. Caccavale, A. Serrano Rodrigo, M. Chiesa, D. Rotta, G.B. Preve, J. Edmunds, M. Welch, E. Kehayas, W. Dorward, F. Duport, R. Costa, D. Mesquita, L. Stampoulidis
Proc. SPIE International Conference on Space Optics (ICSO 2021), 11852, 118521L (2021)
DOI: 10.1117/12.2599248
(85) Silicon-Organic Hybrid Photonics: An Overview of Recent Advances, Electro-Optical Effects and CMOS-Integration Concepts
P. Steglich, Ch. Mai, C. Villringer, B. Dietzel, S. Bondarenko, V. Ksianzou, F. Villasmunta, C. Zesch, S. Pulwer, M. Burger, J. Bauer, F. Heinrich, S. Schrader, F. Vitale, F. De Matteis, P. Prosposito, M. Casalboni, A. Mai
Journal of Physics: Photonics 3(2), 022009 (2021)
DOI: 10.1088/2515-7647/abd7cf
In the last decades, much research effort has been invested to develop photonic integrated circuits and the silicon-on-insulator technology was established as reliable platform for highly scalable silicon-based electro-optical modulators. However, the device performance of such devices is restricted by the inherent material properties of silicon. A perspective approach to overcome these deficiencies is the integration of organic materials with exceptional high optical nonlinearities into a silicon-on-insulator photonic platform. Silicon-organic hybrid photonics has been shown to overcome drawbacks of silicon-based modulators in terms of operation speed, bandwidth and energy consumption. This work reviews recent advances in silicon-organic hybrid photonics and covers latest improvements of single components and device concepts. Special emphasis is given to the in-device performance of novel electro-optical polymers and the use of different electro-optical effects such as the linear and quadratic electro-optical effect as well as the electric field-induced linear electro-optical effect. Finally, the inherent challenges of implementing nonlinear optical polymers into a silicon photonic platform are discussed and a perspective for future directions is given.
(86) Photonisch integrierte Schaltkreise für die Bioanalytik
P. Steglich, A. Mai
GIT Labor-Fachzeitschrift 11-12, 26 (2021)
Biosensoren auf Basis von photonisch integrierten Schaltkreisen zeigen aufgrund ihrer hohen Empfindlichkeit, des geringen Platzbedarfs und der Möglichkeit einer digitalen Datenverarbeitung großes Potenzial für zahlreiche Anwendungen in der Vor-Ort-Analyse. Photonische Biosensoren können eine wichtige Rolle im Gesundheitswesen spielen, wenn der Schritt vom Forschungslabor zur Industrieanwendung gelingt. An dieser Schwelle befindet sich die Forschung, was eine große Chance für innovative Vor-Ort-Analysen im Gesundheitsund Umweltsektor mit sich bringt.
(87) Defining Sensitivity of Integrated Optical Biosensors: A Multidisciplinary Lesson Approach
P. Steglich
Proc. Education and Training in Optics and Photonics Conference (ETOP 2021), Th3A.7 (2021)
(88) Optische Biosensoren: Neues Analyseverfahren ermöglicht schnellere Therapieentscheidungen
P. Steglich
kma : Klinikmanagement Aktuell 26(11), 60 (2021)
DOI: 10.1055/s-0041-1739942
Wissenschaftler des Leibniz-Instituts für innovative Mikroelektronik (IHP) in Frankfurt (Oder) haben Mikro chip-basierte optische Biosensoren entwickelt, die nicht nur eine hohe Empfindlichkeit aufweisen, sondern auch eine Miniaturisierung und eine kostengünstige Massenfertigung ermöglichen.
(89) Analysis of BTO-on-Si-Waveguides for Energy-Efficient Electro-Optical Modulators
P. Steglich, A. Mai
Proc. SPIE Integrated Optics: Design, Devices, Systems and Applications VI (2021), 11775, 117750L (2021)
DOI: 10.1117/12.2592501
(90) A Monolithically Integrated Microfluidic Channel in a Silicon-based Photonic-Integrated-Circuit Technology for Biochemical Sensing
P. Steglich, M. Paul, Ch. Mai, A. Böhme, S. Bondarenko, M.G. Weller, A. Mai
Proc. SPIE Optical Sensors (2021), 11772, 1177206 (2021)
DOI: 10.1117/12.2588791
(91) Silicon Photonic Micro-Ring Resonators for Chemical and Biological Sensing: A Tutorial
P. Steglich, D.G. Rabus, C. Sada, M. Paul, M.G. Weller, Ch. Mai, A. Mai
IEEE Sensors Journal (2021)
DOI: 10.1109/JSEN.2021.3119547
Silicon photonic micro-ring resonators (MRR) developed on the silicon-on-insulator (SOI) platform, owing to their high sensitivity and small footprint, show great potential for many chemical and biological sensing applications such as label-free detection in environmental monitoring, biomedical engineering, and food analysis. In this tutorial, we provide the theoretical background and give design guidelines for SOI-based MRR as well as examples of surface functionalization procedures for labelfree detection of molecules. After introducing the advantages and perspectives of MRR, fundamentals of MRR are described in detail, followed by an introduction to the fabrication methods, which are based on a complementary metal-oxide semiconductor (CMOS) technology. Optimization of MRR for chemical and biological sensing is provided, with special emphasis on the optimization of waveguide geometry. At this point, the difference between chemical bulk sensing and label-free surface sensing is explained, and definitions like waveguide sensitivity, ring sensitivity, overall sensitivity as well as the limit of detection (LoD) of MRR are introduced. Further, we show and explain chemical bulk sensing of sodium chloride (NaCl) in water and provide a recipe for label-free surface sensing.
(92) CMOS-Compatible Bias-Tunable Dual-Band Detector based on GeSn/Ge/Si Coupled Photodiodes
E. Talamas Simola, V. Kiyek, A. Ballabio, V. Schlykow, J. Frigerio, C. Zucchetti, A. De Iacovo, L. Colace, Y. Yamamoto, G. Capellini, D. Grützmacher, D. Buca, G. Isella
ACS Photonics 8(7), 2166 (2021)
DOI: 10.1021/acsphotonics.1c0061, (SiGeSn NanoFETs)
Infrared (IR) multispectral detection is attracting an increasing interest with the rising demand for high spectral sensitivity, room temperature operation, CMOS compatible devices. Here, we present a two-terminal dual-band detector, which provides a bias-switchable spectral response in two distinct IR bands. The device is obtained from a vertical GeSn/Ge/Si stack, forming a double junction n-i-p-i-n structure, epitaxially grown on a Si wafer. The photoresponse can be switched, by inverting the bias polarity, between the near and the short-wave IR bands, with specific detectivities of 1.9×1010 and 4.0×109 cm·(Hz)1/2/W, respectively. The possibility of detecting two spectral bands with the same pixel opens up interesting applications in the field of IR imaging and material recognition, as shown in a solvent detection test. The continuous voltage tuning, combined with the non-linear photoresponse of the detector, enables a novel approach to spectral analysis, demonstrated by identifying the wavelength of a monochromatic beam.
(93) Analog 2:1 Multiplexer with over 110 GHz Bandwidth in SiGe BiCMOS Technology
T. Tannert, M. Grözing, M. Berroth, C. Schmidt, J. H. Choi, C. Caspar, J. Schostak, V. Jungnickel, R. Freund, H. Rücker
Proc. IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS 2021), (2021)
(SG13G3)
(94) Designs Break Bandwidth Record
U. Troppenz, J. Kreißl
Nature Photonics 15, 4 (2021)
DOI: 10.1038/s41566-020-00739-x
Two independent reports of directly modulated lasers with bandwidths of >60 GHz may help bring data rates beyond 200 Gb s–1 to low-cost optical communication systems. Key to the successes has been managing photonic feedback effects within the laser cavities.
(95) Numerical Simulation of Optical Through-Silicon Waveguide for 3D Photonic Interconnections
F. Villasmunta, P. Steglich, S. Schrader, H. Schenk, A. Mai
Proc. International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD 2021), 115 (2021)
DOI: 10.1109/NUSOD52207.2021.9541464
(96) Electro-Optical Properties of Doped Polymers with High Transparency in the Visible Wavelength Range
C. Villringer, P. Steglich, S. Pulwer, S. Schrader, J. Laufer
Optical Materials Express 11(11), 3801 (2021)
DOI: 10.1364/OME.435953
The electro-optical (EO) properties of poly(methyl methacrylate) and the photopolymer poly(vinyl cinnamate) doped with varying concentrations of the EO chromophore 2-Methyl-4-nitroaniline were measured. The EO polymers were embedded in Fabry-Pérot etalons for the simultaneous determination of the Pockels and Kerr coefficients from measurements of the fringe shift induced by an external electric field. It was found that the host polymer has a significant impact on the EO performance and that the undoped host polymers exhibit a significant Pockels effect. Moreover, the Kerr effect provides a substantial contribution of 27% to the total change of the refractive index at relatively high electric field strengths of E = 91.2 MV m−1.
(97) Quantitative Scanning Microwave Microscopy of Few-Layer Platinum Diselenide
X. Wang, K. Xiong, L. Li, J.C.M. Hwang, X. Jin, G. Fabi, M. Farina, O. Hartwig, M. Prechtl, G.S. Düsberg, A. Göritz, M. Wietstruck, M. Kaynak
Proc. 50th European Microwave Conference (EuMC 2020), 987 (2021)
DOI: 10.23919/EuMC48046.2021.9338192
(98) An Experimental Load-Pull Based Large-Signal RF Reliability Study of SiGe HBTs
C. Weimer, P. Sakalas, M. Müller, G.G. Fischer, M. Schröter
Proc. IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS 2021)
(SIGEREL)
(99) BiCMOS Through-Silicon Via (TSV) Signal Transition at 240/300 GHz for MM-Wave & Sub-THz Packaging and Heterogeneous Integration
M. Wietstruck, St. Marschmeyer, Ch. Wipf, M. Stocchi, M. Kaynak
Proc. 50th European Microwave Conference (EuMC 2020), 244 (2021)
DOI: 10.23919/EuMC48046.2021.9338247
(100) High-Frequency Tellurene MOSFETs with Biased Contacts
K. Xiong, G. Qiu, Y. Wang, L. Li, A. Göritz, M. Lisker, M. Wietstruck, M. Kaynak, W. Wu, P.D. Ye, A. Madjar, J.C.M. Hwang
Proc. IEEE MTT-S International Microwave Symposium (IMS 2021), 319 (2021)
(101) Threading Dislocation Reduction of Ge by Introducing a SiGe/Ge Superlattice
Y. Yamamoto, C. Corley, M.A. Schubert, M.H. Zoellner, B. Tillack
ECS Journal of Solid State Science and Technology 10(3), 034005 (2021)
DOI: 10.1149/2162-8777/abea5e
The influence of introducing a SiGe/Ge superlattice (SL) between Ge layers and Si substrate for the sake of the reduction of the threading dislocation density (TDD) without additional annealing is investigated. By introducing the SiGe/Ge SL and optimizing the layer stack, the TDD of the Ge layer becomes ~1/3. In the case of 2.8 μm thick Ge without introducing the SiGe/Ge SL, the TDD at the surface is 7.6 × 108 cm−2. A slight TDD reduction is observed by introducing a Si0.2Ge0.8/Ge SL between the Si substrate and the Ge layer. By inserting 5, 10 and 20 cycles of Si0.2Ge0.8/Ge, the TDD is reduced to 7.1 × 108, 5.9 × 108 and 5.3 × 108 cm−2, respectively. The lateral lattice parameters of these SLs are ~5.656 Å, which is a smaller value compared to that of bulk Ge, indicating plastic relaxation by misfit dislocation formation. Further TDD reduction is realized with increasing Si concentration in the SiGe/Ge SL without changing the cycle of the SL. However, surface roughening due to pit formation occurs if the Si concentration in the SL is higher than 50% because of increased strain at the interfaces between SiGe and Ge. With increasing SiGe and Ge thickness ratio in the SL layer and maintaining periodicity and cycles, the TDD is reduced to 2.8 × 108 cm−2 without degrading the surface roughness. This improvement is related to a relaxation of the SiGe/Ge SL by plastic deformation.
(102) Emerging Terahertz Integrated Systems in Silicon
X. Yi, C. Wang, Z. Hu, J. Holloway, M.I.W. Khan, M.I. Ibrahim, M. Kim, G.C. Dogiamis, B. Perkins, M. Kaynak, R.T. Yazicigil, A.P. Chandrakassan, R. Han
IEEE Transactions on Circuits and Systems I 68(9), 3537 (2021)
DOI: 10.1109/TCSI.2021.3087604
Silicon-based terahertz (THz) integrated circuits (ICs) have made rapid progress over the past decade. The demonstrated basic component performance, as well as the maturity of design tools and methodologies, have made it possible to build high-complexity THz integrated systems. Such implementations are undoubtedly highly attractive due to their low cost and high integration capability; however, their unique characteristics, both advantageous and disadvantageous, also call for research investigations into unconventional systematic architectures and novel THz applications. In this paper, we review the current status and future trend of silicon-based THz ICs, with the focus on state-of-the-art THz microsystems for emerging sensing and communication applications in the last few years, such as high-resolution imaging, high medium/long-term stability time keeping, high-speed wireline/wireless communications, and miniaturization of RF tags, as well as THz packaging technologies.
(103) SiGe HBTs and BiCMOS Technology for Present and Future Millimeter-Wave Systems
T. Zimmer, J. Böck, F. Buchali, P. Chevalier, M. Collisi, B. Debaillie, M. Deng, P. Ferrari, S. Fregonese, C. Gaquiere, H. Ghanem, H. Hettrich, A. Karakuzulu, T. Maiwald, M. Margalef-Rovira, C. Maye, M. Möller, A. Mukherjee, H. Rücker, P. Sakalas, R. Schmid, K. Schneider, K. Schuh, W. Templ, A. Visweswaran, T. Zwick
IEEE Journal of Microwaves 1(1), 288 (2021)
DOI: 10.1109/JMW.2020.3031831
This paper gives an overall picture from BiCMOS technologies up to THz systems integration, which were developed in the European Research project TARANTO. The European high performance BiCMOS technology platforms are presented, which have special advantages for addressing applications in the submillimeter-wave and THz range. The status of the technology process is reviewed and the integration challenges are examined. A detailed discussion on millimeter-wave characterization and modeling is given with emphasis on harmonic distortion analysis, power and noise figure measurements up to 190 GHz and 325 GHz respectively and S-parameter measurements up to 500 GHz. The results of electrical compact models of active (HBTs) and passive components are presented together with benchmark circuit blocks for model verification. BiCMOS-enabled systems and applications with focus on future wireless communication systems and high-speed optical transmission systems up to resulting net data rates of 1.55 Tbit/s are presented.
